|
| |
|
|
Advancing Microelectronics • Volume 29, No. 3 • May/June, 2002
|
| | Table
of Contents | Previous
Page | Next
Page | |
Chip in Polymer - Next Step in Miniaturization
A. Ostmann, A. Neumann, Technical University of Berlin (TUB), Gustav-Meyer-Allee 25, 13355 Berlin, Germany, phone: +49 30 314 72836, fax: +49 30 314 72835, email: ostmann@izm.fhg.de, E. Jung, L. Boettcher, and H. Reichl, Fraunhofer Institute for Reliability and Microintegration (IZM), Gustav-Meyer-Allee 25, 13355 Berlin, Germany
Introduction
The coming generations of portable products require significant improvement of the packaging technologies, mainly due to increasing signal frequencies and the demand for higher density of functions. State of the art is organic substrates with micro-via build-up layers, equipped on both sides with discrete passive and active components. The space requirement of active chips can be already reduced to a minimum by implementing CSPs (chip size packages) or flip chips. However a further miniaturization requires a 3D integration of active and passive components. In a short time the signal frequencies will increase to several GHz in high speed digital applications. In order to maintain signal integrity, much shorter and impedance-matched interconnects between chips and passive components are required.
Chip in Polymer concept
At Fraunhofer IZM, together with the Technical University of Berlin (TUB), a new packaging concept has been developed, the Chip in Polymer (CIP) technology. It aims to solve problems of current and future packaging. The CIP technology is based on the embedding of thin chips (about 50 µm thickness) into the build-up layers of a printed circuit board (PCB). The principle structure is shown in Figure 1. Wafer thinning down to 50 µm is still not common but a number of manufacturers have already presented equipment for this technology and the first services offer extreme wafer thinning and dicing.
The thin chip is die bonded to the substrate, which consists of a single or multilayer FR4 laminate or an other organic material. Then the chip is embedded in a build-up dielectric, which can be either a liquid epoxy or a laminated RCC® (resin-coated copper) film. Via holes are opened to the bondpads of the chip and to the substrate contacts. Finally the vias are metallized and a Cu layer is applied that makes the electrical contacts to the chip. In order to be compatible with via opening and interconnect metallization, the chips need to have an additional pad metallization or a re-wiring layer on top of its intrinsic Al or Cu pad metal. Besides the active chips, passive components like resistors and capacitors have to be integrated, too. While integrated resistors can be already manufactured in the PCB process integrated capacitors with high capacities are still not available. Here the use of so-called Integrated Passive Devices (IPDs) can solve the problem of integration. IPDs, which are manufactured on a Si substrate, can contained complex R, C and L networks with very low tolerances. Using thinned IPDs they can be integrated in the CIP technology as well as active chips.
By this approach, it is possible to use the top layer over the chip for other devices like SMDs or additional flip chips. The materials chosen for this process are standard materials from the PCB industry. This allows a low-cost and easy handling of the materials. Two technological approaches for CIP are being developed at IZM and TUB together with industrial partners: One is the chip embedding using liquid photo-dielectric and embedding by build-up lamination (see Figure 2a). The other is the embedding of chips into the laminated build-up layer on a PCB (see Figure 2b)
Chip embedding by liquid photo-dielectric
This approach for CIP is based on the chip embedding into a liquid, photo-sensitive build-up dielectric and a metallization using electroless Cu. The dielectric chosen is Probelec XB7081 from Vantico. In order to create a bondpad surface on the chips, compatible with electroless Cu deposition, a thin Ni/Cu layer is applied, using IZM’s electroless bumping process. A first challenge in development was the die bonding of Si chips with a thickness of only 50 µm. Conventional die bond adhesives were often flowing on top of the chips, contaminating the pads. This problem could be solved by the use of small volumes of a low-viscous adhesive, which resulted in a self-adjusting gap of about 10 µm height. A further issue was the planar embedding into the dielectric. Similar to wafer-processes, spin-coating was used for the epoxy application to the square substrates. However the coverage of the chip edges was poor, resulting in shorts of the deposited Cu lines by the Si. A solution was the application of a 50 µm epoxy layer prior to die bonding containing cavities for the chips. Around the chips these cavities have a space of about 100 µm, allowing an easy placement. After die bonding a further dielectric layer is applied by spin-coating, containing vias to the chip pads. Special attention was paid to a void-free filling of the gap around the chips. The whole surface of this via layer is chemically roughened and activated in a Pd solution, which can initiate the later electroless Cu deposition. A further dielectric layer is applied by spin-coating and structured, opening only the areas for Cu line deposition. In an electroless bath the Cu lines and the vias to the chip and to the substrate are plated. Finally an electroless Ni/Au surface finish is applied to the Cu. Pictures of different process states are shown in Figure 3.
First evaluations of this technology have shown that it is possible to achieve via diameters to the chip of 40 µm and lines and spaces of 30 µm over the edge of the embedded chips. First reliability test, using a few samples only, did not reveal intrinsic problems. The samples were stable during multiple reflows, 1000 h humidity storage 85°C / 85%r.h. and 1000 thermal cycles -55°C / 125°C. Further tests on a larger amount of samples will be done in the near future. A first modelling of the thermo-mechanical behaviour of a CIP structure during thermal cycles was performed. Also here no critical stresses, which might give the risk of delamination or chip cracking, were revealed.
Realization of a stackable CSP
As a first demonstrator of the CIP technology a stackable CSP (3D CSP) has been realized. It consists of a 100x100 mm FR4 substrate of 0.5 mm thickness and sites for 25 single chip packages (3D CSPs). The substrate has a double-sided Cu metallization and conventionally drilled through-holes. Test chips of 60 µm thickness, 10x10 mm size and 120 I/Os are die bonded to the substrate. The Al bondpads have a pitch of 300 µm and are covered by electrolessly deposited layers of 5 µm Ni / 2 µm Cu. After embedding by the epoxy dielectric the chips are electrically connected to the substrate by the fully-additive electroless Cu deposition of the conductor lines (see Figure 4). Finally a solder mask is applied on the top side, solder balls are printed on the bottom and the substrate is cut into single packages. Figure 4 shows a cross-section of a 3D CSP. Each package now has solderable pads on the top and solder balls at the bottom side. Electrical connections from top to the bottom are enabled by the vias in the build-up layer to the substrate metal and the drilled through holes of the board, as shown in Figure 6a. Two stacked 3D CSPs mounted on an interconnect test board are shown in Figure 6b. The design of the 3D CSP allows four-point and daisy-chain measurements of stacks with up to four packages
Embedding by build-up lamination
While the above described process utilizes mask lithography and spin-coating of liquid dielectric, a mass manufacturing oriented approach is based upon the PCB industry’s infrastructure. Here, build-up lamination, laser drilling of via holes and electrolytic deposition of Cu are used to connect the embedded chips. Thin chips are added into the established process flow for minimal impact on the manufacturing capabilities. The chips are die bonded on the core layer, e.g. consisting of a multi-layer FR4 panel. Using resin clad copper foil, sequential build-up layers are laminated over the thin die without changing the topography of the top layer. Vias to the chip are opened using laser drilling. Due to the decreasing contact pitch, an additional redistribution layer on the chips may be necessary. This allows to interconnect with today’s state of the art in via drilling.
The CIP approach using chip embedding by lamination is under investigation by Fraunhofer IZM together with PCB manufacturers in a German R&D project. So far the die bonding and planar embedding on 18”x24” production panels has been demonstrated. Figure 7 shows a cross section of a 60 µm chip into a build-up laminate layer. The goal of this project is to demonstrate the CIP compatibility with a PCB production process.
Outlook
In the future, the development efforts for Chip in Polymer will be continued for both of the above mentioned technology approaches. A possible application is the stacking of multiple memory chips as shown in the draft Figure 8a. A big challenge for such a construction will be the thermal management, however it gives the possibility for extreme integration. A further application can be a RF power module for mobile phone base stations. By chip soldering to a metal substrate a high power dissipation can be handled due to the short thermal path from the active semiconductor region on top through the thin bulk Si. The required passives with low tolerances can be achieved by Integrated Passive Devices (IPDs) close to the active chip, connected by very short impedance-matched interconnects.
In order to realize the above mentioned applications a number of activities has been planned or started already. Besides lithography the structuring by an UV laser will be implemented, allowing rapid prototyping and flexible processing. New dielectrics will be investigated, having low-k and low thermal expansion (CTE). For low-cost products the formation of integrated resistors using highly resistive electroless Ni layers is under development. The general goal is to develop technology ways towards highly integrated and cost-effective System-in-Packages.
Summary
Chip in Polymer is an enabling technology for the future interconnect needs. Two process approaches for Chip in Polymers have been presented. The embedding of thin chips into a photo-sensitive liquid epoxy and interconnection using electroless Cu deposition has been developed. As a first demonstrator a stackable single chip package (3D CSP) has been manufactured on 100x100 mm² FR4 panels. First reliability evaluations have shown encouraging results. A further approach is the chip embedding into laminated build-up layers, using the capabilities of advanced PCB manufacturing, like laser drilling of micro-vias. Here the die bonding and chip embedding using 18”x24” panels have been demonstrated in cooperation with high-volume PCB manufacturers. The further development aims for ultra-dense and high frequency applications manufactured by cost-effective processes.
Part of the work described is done in the German BMBF-funded project “Systemintegration in polymere Schaltungstraeger,” contract no. 02PP2051, with the partners AT&S, ILFA, Wuerth, ANDUS and Diehl.
| |
|
