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Advancing Microelectronics • Volume 29, No. 5 • September/October, 2002
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HiTCE Ceramics: Bridging the Gap Between Ceramics and Organic Packaging

Richard Sigliano, Kyocera America

Abstract

The ongoing trend in the semiconductor packaging industry is the swift conversion from ceramic materials to organic materials. The reasons are many for this conversion and are not limited to the following, including; lower piece part cost, higher electrical performance, superior second level reliability and general market acceptance of organic materials. The ceramic packaging companies have struggled against this trend witnessing eroding market shares and lower profit margins.

To stem this eroding market trend, a new ceramic material was developed that exhibits very similar material, mechanical and electrical characteristics as today organic materials, but with the design rules and densities of ceramic multilayer technology. This material is a glass/ceramic composite LTCC (Low Temperature Co-fired Ceramic) material titled “HiTCE” ceramics. Named for its TCE (Temperature Coefficient of Expansion) properties, this material has demonstrated superior second level reliability characteristics equal to current organic materials.

This paper will discuss this new LTCC material and its corresponding material characteristics as it relates and compares to organic packaging materials.

Introduction

As the integration of functions and I/Os increase in today’s ASIC devices, the wiring density and layer counts have increased pushing the overall sizes of today’s current packages. It is not uncommon to have packages extending 50 mm on a side, which puts a strain on the first and second level reliability. Compound this trend with ceramic materials that have a greater difference in range of TCEs between the mounting board and package, catastrophic failures will occur with multiple temperature excursions. It is widely assumed in the industry that large ceramic packages are unsuitable for surface mounting onto organic printed circuit boards due to this effect.

Although the advantages of multilayer ceramic packages are numerous, these characteristics cannot be utilized due to this reliability concern. A new class of LTCC materials has been developed to closely match the TCE of the mounting organic board materials with that of the package, increasing temperature cycling life. A surfaced mounted package such as a BGA (Ball Grid Array) has a low height interconnection to the PWB (Printed Wiring Board). If there is large difference of TCE between the package and the PWB, a BGA package receives more severe shear strain, damaging the integrity and reliability of the solder joint. Second level mounting of a ceramic package on a organic PWB, the shear strain becomes a large problem since Alumina ceramics has a TCE of 7.1ppm/°C while a typical FR-4 PWB has a TCE of 12 to 16 ppm predicated upon the amount of copper planes as illustrated in figure1.

The solution to overcome the TCE mismatches of the package and PWB materials is to limit the shear strain failures, by closely matching the TCE of the materials. Hence, both materials will expand and contract at the same rates through a range of temperature excursions. There are several solutions to maximize the shear strain of the solder joint by either increasing the stand-off height such as with CGA (Column Grid Array) and DBGA (Dimple Ball Grid Array) or by using ceramic circuit boards. These solutions are expensive and not well adopted in the industry, ex-cept for very high-end applications. By numerical simulation, a new ceramic material was developed and formulated to optimize the TCE of the package to match closely with the TCE of organic PWB. This material is newly named as “HiTCE” and is a LTCC formulation. The material characteristics are depicted in figure 2 and are compared to standard Alumina and FR-4 organic PWB materials. The TCE of the HiTCE material is 12.3 and closely matches the TCE of the PWB materials. The advantages of this new material are:

1. It has a high TCE of 12.3 which closely matches PWB materials

2. The conductor metallization is Copper, which has a 3X superior sheet resistance over Tungsten or Molybdenum metallization systems

3. Has a lower dielectric constant: e = 5.2/5.3

4. Fired at a lower temperature (LTCC)= 850-950C

5. Has the same design rules as Alumina cofired ceramics

Second Level Reliability

Temperature cycling tests were conducted comparing conventional multilayer Alumina packages were carried out on a 33mm x 33mm square BGA package attached to a 65 square mm board with a high melting point solder ball attached to the package and the PWB with a eutectic solder. The temperature cycling test was conducted at a temperature range of -40°C to +125°C with a dwell time of .5 hours at each time temperature. As depicted in the Weibull chart (Figure 3) a HiTCE package with a body size of 33mm square has a 2.58x longer life as does an Alumina packages at two different package thicknesses (1.2mm and 1.8mm thick). This data corresponds with previous FEM data simulated previously.

Temperature cycling tests were also conducted for a larger package (50mm square) with the same parameters as the last figure at two different thicknesses (same as before). Illustrated in figure 4, tests have shown under the same stringent requirements, 1000 cycles is still achievable and would meet most second level industry requirements.

It is important to note that second level reliability is affected by a number of parameters as illustrated in figure 5 and is not limited to the following:

First Level Reliability

Because of the High TCE of this material first level reliability was of some concern. Experimentation was performed and TCT were initiated to ascertain any issues, which would be affected at the chip interface. Assembly was preformed for a 10mm square high melting point solder flip chip attached device with underfill on a 1mm thick HiTCE board. Preconditioning and configuration of this test is illustrated in figure 6.

Using the same temperature parameters as the previous TCT (-40°C to +125°C) on a 12 x 15 mm flip chip device attached to a 21mm square HiTCE package, no failures were detected after 2000 cycles (Figure 7). In fact, this test was conducted until over 3000 cycles were completed without any failures.

Package Applications

Varieties of applications are suited for this new material and have been designed and fabricated. In the market, common applications include packages for high speed telecommunication switching devices designed for flip chip attachment, MUX, DeMux devices, high speed SRAM memory chips, chipsets, ASICS for Main Frame computers, FPGAs and MPUs. Pictured in Figure 8 is a 45mm square, 2.4mm thick, 10 layers, 1600 I/O Flip Chip Package fabricated with the new HiTCE material.

Conclusion

A new LTCC formulation has been developed to improve the second level reliability concerns of cer-amic materials surfaced mounted on organic PWB materials. The TCE and Young Modulus of this material are 12.3 ppm/C and 75Gpa, respectively. By temperature cycling test, we have confirmed that the solder joint reliability for both first and second level attachment of the High TCE LTCC ma-terial ceramic package has significantly increased.

References

1. Kouichi Yama- guchi, Masahiko Hi- gashi, Noriaki Ha- mada, Hideto Yone- kura and Yasuyoshi Kunimatsu, “Improvement of Solder Joint Reliability Between Multilayer Ceramic Package and Printed Wiring Board by New Ceramic Material,” Proceedings of the 1997 Electronic Component & Technology Conference, San Jose, pp1277-1282.

2. Kazutaka Maeda, Masahiko Higashi, Masanari Kokubu and Shoichi Nakagawa, The Application of HiTCE Ceramic Material for LGA-type Chip Scale Package,” Proceedings of the 2000 Electronic Component & Technology Conference, Las Vegas, May/2000.

3. Raj Pendse, B. Afshari, N. Butel and J. Leibovitz, “New CBGA Package with Improved 2nd Level Reliability,” Proceeding of the 2002 Electronic Component & Technology Conference, San Diego, May/2002.

4. Shoji Uegaki, Seigo Matsuzono, Shingo Sato, Takeshi Kubota, Shin Matsuda and Masahiro Fukui, “Development of Array Format Ceramic CSP,” 1999 Fourth Annual Pan Pacific Microelectronics Symposium, Feb. 2-5, 1999, pp 26-31.

   

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