Advanced Technology Workshop on
Chip-Package Interactions with
Fanout Wafer Level Packaging and Embedded Die in Substrate 2016

April 6-7, 2016
DoubleTree San Diego - Hotel Circle
1515 Hotel Circle South
San Diego, California 92108

Organizing Committee:

General Chair
Urmi Ray
General Co-Chair
Tengfei Jiang
University of Central Florida

General Co-Chair
Rajiv Roy
Rudolph Tech

Program Committee:

Rich Rice – ASE
Venky Sundaram – Georgia Tech

Steffen Kroehnert – Nanium
Horst Clauberg – K&S
John Hunt – ASE
Bob Chylak – Kulicke & Soffa
Raja Swaminathan – INTEL


CPI 2016 Focus:
The International Microelectronics Assembly and Packaging Society (IMAPS) will host an Advanced Technical Workshop in San Diego on CHIP-PACKAGE INTERACTIONS WITH FANOUT WAFER LEVEL PACKAGING on 6-7 April, 2016. Fanout wafer level packaging is a rapidly growing segment of the semiconductor packaging industry. Miniaturized mobile and IOT applications are driving the need for thin, low cost packaging with high pincount to chip area ratio. As fanout packaging is being extended to thinner and larger form factors and applied to 2.5D/3D system-in-package solutions, chip-packaging interactions (CPI) including warpage, mechanical and electrical stress effects, potential barriers to wide scale adoption of this promising technology. This workshop will provide a venue for papers, poster sessions, and brainstorming discussions, bringing together product designers with the fanout packaging supply chain to explore cost-effective solutions to the CPI challenges, including new materials, design techniques and EDA tools, and process flows and equipment.

Wednesday, April 6, 2016

12:00 pm - 5:00 pm: Registration Open

2:00pm - 6:00pm:
IMAPS Workshop on RF/Microwave Packaging (RaMP) & the CPI Workshop will come together for a joint session, panel discussion, and networking! This is a great opportunity to both topical/industry segments to network and discuss common challenges, solutions and technologies.

2:00pm - 2:15pm : Opening of Joint Session: Objectives of joint session, and Introduction of Keynote speaker
RaMP General Chair: Ken Kuang, Torrey Hills Technologies, LLC
CPI Workshop General Chair: Urmi Ray, Qualcomm

2:15pm - 3:15pm: KEYNOTE PRESENTATION:

Keynote - Karim

System-in-Package (SiP) Solution for RF and Digital System Integration and Miniaturization

ABSTRACT: The demand for product miniaturization is driving the need for highly integrated systems in today’s mobile wireless, IoT/Wearable, Solid State Drive (SSD), automotive and other applications. RF and digital system miniaturization is a complex set of design challenges including high performance, small footprint, reduced process geometries and increased test and reliability, all requiring new and innovative techniques in System-in-Package (SiP) solutions. SiP lets system designers to mix and match technologies, such as RF/Microwave in silicon and Gallium Arsenide forms, digital, mix-mode, power, MEMS, sensors, antenna, crystals, conformal/compartmental shielding and other passives components in the same package. SiP comes in different package platform from 2.5D/3D package, WLFOUT, stacked die, Package on Package, Package in Package, leadframe package, BGA & LGA packages, including embedded active and passive components in a substrate.

Nozad Karim presently is the Vice President of SiP & System Integration at Amkor Technology. He has over 30 years of experience working with semiconductor packaging, System in Package, circuit and system designs for digital, analog, and RF/Microwave applications. Prior to Amkor, he served in engineering and management roles with Motorola Communication, Texas Instruments, & Compaq/HP.


3:15pm - 4:00pm: Networking Break in RaMP Exhibits

4:00-6:00: PANEL SESSION:

Industry Expert Panel Session on:
Challenges of RF integration into Fan-Out Wafer Level Packaging
and Embedded Die in Substrate

The panelists will spend a few minutes speaking to the audience to lay the framework for this topic, before interactive Q/A with the audience!

MODERATORS: Urmi Ray, Qualcomm; Rajiv Roy, Rudolph Tech

Tanja Braun, Fraunhofer IZM
Franklin Kim, Kyocera America

Mark Nakamoto, Qualcomm
Ray Petit, Pacific Rim Engineering
Rich Rice, ASE
Rick Sigliano, Kyocera
Susan Trulli, Raytheon Integrated Defense Systems
Jan Vardaman, TechSearch International

7:00pm - 9:00pm: Group Networking/Social Event: REGISTER ONLINE

San Diego Bay Cruise Social
Sponsored by:
Torrey Hills Technologies - Materion Ceramics - EMD Materials

April 6, 2016 | 7pm-9pm
(Bus pickup from hotel at 6:30pm)

$15 per person

Enjoy an evening social cruising the San Diego Bay on the private catamaran Aolani! Light hors d’ouevres will be provided, along with a cash bar, after the catamaran departs the Sheraton Harbor Island Hotel and Marina. This private charter will cruise the bay for two hours before returning. Transportation to/from the Doubletree San Diego Hotel Circle (RaMP and CPI workshop location) will be provided. Register early – the vessel has limited capacity of 48 cruisers!


Thursday, April 7, 2016

7:00am - 5:00pm: Registration

7:00am - 8:15am: Continental Breakfast

8:15am - 8:30am: Opening Remarks
General Chair: Urmi Ray, Qualcomm

8:30am - 9:15am: KEYNOTE PRESENTATION:

Keynote - Nakamoto

Chip Package Interaction Considerations in Fan-out Wafer Level Packaging

ABSTRACT: With the advent of thinner die/packages, new materials and more complex packages Chip Package Interaction has become a larger concern for the industry. Wafer Level Packages and variants such as Fan Out Wafer Level Packages (FOWLP) have an additional risk which we refer to as Chip Board Interaction. This talk will discuss some of the basics of the CPI and CBI risks to FOWLP which include both mechanical and electrical risks to products. These mechanisms span the Design, Process and Package domains and as such requires a collaborative efforts to manage the risks and trade-offs.

Mark Nakamoto, Qualcomm
Mark Nakamoto currently is a member of Qualcomm’s Advanced Technology Team in the Packaging Organization. He leads the eCPI Team working on the development of Modeling, Characterization and Analysis of the electrical impacts of Chip Package Interaction. Mark has over 30 years of experience in the Semiconductor Industry spanning Silicon Process Development, Process and Device Characterization, Test Structure Design, Reliability, Modeling, Design for Manufacturability and 2.5D and 3D Development. Prior to Qualcomm Mark held various positions in PDF Solutions, Cadence Design Systems, and Unisys/Burroughs.


Session Chair: Rich Rice, ASE
9:15am - 10:30am

INVITED PRESENTATION: FO-WLP: A Disruptive Technology (45 Minutes)
Jan Vardaman, TechSearch International

High Density Fan-Out (HD-FO) Package Platform for Mobility, Networking and Consumer Applications
Gaurav Sharma, GLOBALFOUNDRIES US Inc. (Adam Beece, Ramakanth Alapati)

10:30am - 11:00am: Networking Break

Session Chair: Raja Swaminathan, Intel
11:00am - 12:30pm

Interaction of Active Dies,Passives, Sensors and already Packaged Components in WLFO based WLSiP and WL3D Packages
Steffen Kroehnert, NANIUM

On the Way from Fan-out Wafer to Fan-out Panel Level Packaging
Tanja Braun, Fraunhofer IZM

A Fully Molded Fan-out Wafer Level Packaging Technology
Chris Scanlan, DECA

12:30pm - 1:30pm: Lunch & Networking


Session Chair: TBD
1:30pm - 3:00pm

Cost Reduced Far Back End of Line (FBEOL) for Advanced Si node (28/20/16nm) Lead free Chip packaging interaction (CPI)
Lei Fu, AMD (YS Low, Tom Dolbear)

Experimental Study on 28nm Chip/Package Interactions in eWLB (Embedded Wafer Level BGA) Fan-Out Wafer Level Packages
Dongkai Shangguan, STATS ChipPAC Inc. (Jian Lin, Won Kyung Choi, Seng Guan Chow, Seung Wook Yoon, STATS ChipPAC Ltd.)

Assessment of Optimized Process Quality and Reliability for Wafer Level Applications
Ennis Ogawa, Broadcom, Ltd.

3:00pm - 3:30pm: Networking Break

Session Chair: Bob Chylak, Kulicke & Soffa
3:30pm - 4:30pm

Enabling 2um line space panel or wafer based Lithography and Inspection
Keith Best, Rudolph Technologies (Gurvinder Singh)

Assembly Solutions for Fan-Out Wafer Level Packaging
Bob Chylak, Kulicke and Soffa Industries, Inc. (Horst Clauberg Tom Strothmann)

4:30pm: Closing Remarks



Registration Information: (Early Registration Deadline: March 11, 2016)

Member, Non-member, Speaker/Chair, Student and Chapter Officer registration fees include: access to all technical sessions, meals, refreshment breaks, and one (1) DOWNLOAD of presentations; download will contain the presentation as submitted by the presenter. Download will be available 15 business days after the event. Also includes a one-year IMAPS individual membership or membership renewal at no additional charge which does not apply to corporate or affiliate memberships. All prices below are subject to change.

Early Fee
Through 3/11/2016
Advance/Onsite Fee
After 3/11/2016
IMAPS Member
Premier Sponsorship
Includes 1 conference badge & advertisements

Speaker Dates/Information:

  • Abstracts Deadline Extended to: February 19, 2016
  • Speaker Notifications Sent: February 29, 2016
  • Early Registration and Hotel Deadlines: March 11, 2016
  • Speaker BIO & Photo Due: April 1, 2016
  • Powerpoint/Presentation for WORKSHOP DOWNLOAD file due not later than: April 6, 2016
  • Powerpoint/Presentation file used during session: Speaker's responsibility to bring to session on USB (recommended to have back-up emailed to prior to event)
  • Technical Presentation Time: 30 minutes (25 to present; 5 for Q&A)


Hotel Reservations: (Hotel Deadline: March 11, 2016)
Reservation must be made directly with the:

DoubleTree San Diego - Hotel Circle
1515 Hotel Circle South
San Diego, California 92108
Phone: 800-486-5315


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