Micross

12th International Conference and Exhibition on
Device Packaging
www.imaps.org/devicepackaging

WekoPa Resort and Casino
Fountain Hills, Arizona USA

IMAPS Device Packaging

Conference and Technical Workshops
March 15-17, 2016
Exhibition and Technology Showcase
March 15-16, 2016
Professional Development Courses
March 14, 2016
GBC Plenary Session
March 16, 2016



Device Packaging (Amkor Image)
Courtesy of Amkor Technology
Device Packaging (RDEDCOM image)
Courtesy of US Army RDEDCOM AMRDEC
 

 

Thank You to the DPC/GBC Premier Sponsors:
DPC/GBC Premier Sponsor: ASE US, Inc.
DPC/GBC Premier Sponsor: Amkor Technology
DPC/GBC Premier Sponsor: NAMICS



TECHNICAL PROGRAM | SHORT COURSES (PDCs) | SPEAKERS | SiP PANEL | POSTERS | GBC PLENARY/KEYNOTE
EXHIBITION | 2016 EXHIBITORS


Professional Development Courses (PDCs)

For those wishing to broaden their knowledge of device packaging, a selection of half-day courses and one full-day course (Intro to Microelectronics) will be offered on Monday, March 14th, preceding the technical conference. Morning PDCs will run from 8:00am until 12:00 noon. Afternoon PDCs will be held from 1:00pm until 5:00pm. The full-day "MEMS" course will run from 8:00am until 5:00pm. The Welcome Reception will immediately follow the PDCs from 5:00pm until 7:00pm in the foyer. A Microelectronics Foundation Texas Hold-em Tournament will be held this year from 7:00pm until 10:00pm. All are invited to register for this fun event which benefits the IMAPS Microelectronics Foundation.

PDCs are available for a separate fee/registration from the full conference (Tuesday-Thursday registration). When you register on-line for these courses, you should first select your Device Packaging Conference registration category on page 1, and then under SESSIONS (page 2 of registration) you will select your PDCs. If you DO NOT plan on attending the conference (Tuesday-Thursday), then simply select PDC ONLY on page 1 ($0 charge) and then select your PDCs on page 2. Contact blamm@imaps.org with questions..

7:00 am - 7:00 pm
Registration
7:00 am - 8:00 am
Continental Breakfast
8:00 am - 12:00 pm FULL-DAY PDC – 8:00am-5:00pm

PDC1:MEMS and the Internet of Things: Principles, Applications, Power Supplies and Device Packaging (8-hour)
CANCELLED
Morning Professional Development Courses (PDCs)
PDC2:Introduction to Microelectronics Packaging (Part 1)
Course Leader: Tom Green, TJ Green & Associates
PDC3: Introduction to Fan-Out Wafer Level Packaging (FO-WLP)
Course Leader: Beth Keser, Qualcomm Technologies, Inc.
PDC4: Electrical Modeling and Test Strategies for 3D Packages
Course Leader: Bruce Kim, City University of New York
PDC5: Performance based Roadmaps for Advanced Packaging
Course Leader: Dev Gupta, APSTL
10:00 am - 10:20 am
Break
12:00 pm - 1:00 pm
Lunch Only provided for those attendees registered for both Morning and Afternoon PDCs
1:00 pm - 5:00 pm
Afternoon Professional Development Courses (PDCs)
PDC6: Introduction to Microelectronics Packaging (Part 2)
Course Leader: Tom Green, TJ Green & Associates
PDC7: Emerging Challenges in Packaging
Course Leader: Raja Swaminathan, Intel Corporation
PDC8: Polymers for Electronic Packaging
Course Leaders: Jeffrey Gotro, InnoCentrix, LLC
 
3:00 pm - 3:20 pm
Break
5:00 pm - 7:00 pm
Welcome Reception (All Attendees Are Invited To Attend)
7:00 pm - 10:00 pm
Texas Hold'em Tournament (Limited Seating)
To Benefit the IMAPS Microelectronics Foundation


***************
Full-Day Professional Development Course
8:00 am - 5:00 pm
Monday, March 14

PDC1: MEMS and the Internet of Things: Principles, Applications, Power Supplies and Device Packaging (8-hour PDC: 8:00am-5:00pm)
Course Leader: Slobodan Petrovic, Oregon Institute of Technology
FULL-DAY (8-hr.) PDC: 8:00am – 5:00pm | $600 (Through 2/19/2016) - $650 (after 2/19/2016)

THIS PDC HAS BEEN CANCELLED

***************
Morning Professional Development Courses
8:00 am - Noon
Monday, March 14

PDC2: Introduction to Microelectronics Packaging (PART I)
Course Leader: Thomas Green, TJ Green Associates LLC
Morning PDC: 8:00am – 12:00pm | $400 (Through 2/19/2016) - $450 (after 2/19/2016)

Course Description:
Introduction and Overview of Microelectronic Packaging

  • What is microelectronic packaging
    • What are we trying to package and why?
  • Packaging drivers
    • Cost, Size, Weight, Thermal
  • Market segments
    • Commercial, Automotive, Medical, Aerospace etc.
  • Terminology and product definitions
  • Includes pass around of sample packages
  • Who are the players?
  • How does the supply chain work
  • Basic review of IC Fab processes
  • Wafer sawing and thinning
  • Substrates
    • HDI laminates, LTCC/HTCC, Flex, Teflon and RF board material
  • Fundamentals of component attach
    • Epoxy adhesives and eutectic solders
  • Wirebonding Interconnect technology
    • Gold and copper ball bonding, wedge bonding
  • Flip chip assembly processes
  • Transfer molding of high volume plastic packages
    • JEDEC Pub 95. registered outline drawings for micro packages
    • Dual Leadframe (SOT, SOIC, SSOP, TSSOP, PSOP, TSOP)
  • Hermetic packaging processes

Who Should Attend?
This overview course is intended for those unfamiliar with microelectronics packaging technology. People in sales, purchasing, program management, new engineers, managers, equipment/material suppliers, people new to this industry or anyone looking to get a broad industry overview and review of the industry drivers, history and future trends are welcome to attend.

Mr. Tom Green is the principle at TJ Green Associates LLC (www.tjgreenllc.com) a veteran owned small business focused on training and consulting for military, space and medical microelectronic devices. He teaches a variety of public courses around the globe and in plant at major corporations and consults for a variety of medical device companies. He has thirty two years of experience in microelectronics working at positions in industry, academia and government. Tom has demonstrated expertise in die attach, wirebond, visual inspection, hermetic seal and leak testing processes. He has gained valuable experience over the past ten years in packaging and testing of devices for use as Class III medical implants and is often called on as an expert witness for hermeticity related failures. Tom is an active IMAPS member and Society Fellow. He has a B.S. in Materials Engineering from Lehigh University and a Masters from the University of Utah.

PDC3: Introduction to Fan-Out Wafer Level Packaging
Course Leader: Beth Keser, Qualcomm Technologies, Inc.
Morning PDC: 8:00am – 12:00pm | $400 (Through 2/19/2016) - $450 (after 2/19/2016)

Course Description:
Fan-out wafer level packaging (FO-WLP) technologies have been developed across the industry over the past 15 years and have been in high volume manufacturing for over 8 years. FO-WLP has matured enough that it has come to a crossroads where it has the potential to change the electronic packaging industry by eliminating wirebond and bump interconnections, substrates, leadframes, and the traditional flip chip or wirebond chip attach and underfill assembly technologies across multiple applications. This course will cover the advantages of FO-WLP, potential application spaces, package structures available in the industry, process flows, material challenges, design rule roadmap, reliability, and benchmarking. This course has been updated with over 10% new material compared to the first time it was offered last year at the IMAPS Device Packaging Conference.

Outline:
1. Current Challenges in Packaging;
2. Definitions and Advantages;
3. Applications;
4. Package Structures including Advanced FO technologies;
5. Process;
6. Material Challenges;
7. Equipment Challenges;
8. Design Rules;
9. Technology Roadmap;
10. Reliability;
11. Benchmarking

Who Should Attend?
Engineers and managers responsible for advanced packaging development, package characterization, package quality, package reliability and package design should attend this course. Engineers and those in marketing and sales who supply equipment, materials, or services to the advanced packaging supply chain should also attend. Both newcomers and experienced practitioners are welcome.

Dr. Beth Keser has over 17 years’ experience in the semiconductor industry. Beth received her B.S. degree in Materials Science and Engineering from Cornell University and her Ph.D. in Materials Science and Engineering at the University of Illinois at Urbana-Champaign. Beth’s development of materials and packaging technologies for the semiconductor industry has resulted in 8 patents, 10 patents pending, and over 40 publications in this area. Currently, Beth is the Fan-Out Wafer Level Packaging Technology Manager at Qualcomm, San Diego.

Before joining Qualcomm in 2009, Beth Keser was instrumental in developing 2 packaging technologies during her career at Motorola and Freescale Semiconductor. Beth led the Wafer-Level Chip Scale packaging team at Motorola, which included directing the activities of process engineering, package characterization, package reliability, and mechanical modeling. In addition, Beth Keser was the lead technologist and manager of the Redistributed Chip Packaging Technology (RCP). Beth led the team that developed this technology for 6 years. Beth developed several process and material solutions for this new technology. Beth also volunteered as WLP Track co-chair at IMAPS Device Packaging Conference from 2006-2009.

PDC4: Electrical Modeling and Test Strategies for 3D Packages
Course Leader: Bruce Kim, City University of New York
Morning PDC: 8:00am – 12:00pm | $400 (Through 2/19/2016) - $450 (after 2/19/2016)

Course Description:
Today’s miniaturization and performance requirements result in the usage of high-density advanced packaging technologies, such as system-in-package (SIP), direct-chip-attach, chip-scale packaging (CSP), and ball-grid-arrays (BGA). Due to their physical access limitation, the complexity and cost associated with their test and diagnosis are considered major issues facing their use. This course introduces comprehensive knowledge of electrical modeling and test solutions for 3D packages. We begin by a short tutorial on 3D packages including interposers and TSV. We then place particular emphasis on electrical modeling; test and debugging approaches for 3D packages for RF, bio, power and MEMS packages. Finally, we cover diagnosis and repair techniques for assembled packages.

Course Outline:

  • What is 3D packaging?
  • Introduction to existing 3D package techniques in
    • Analog/Digital/RF device packages
    • Mixed-signal device packages
  • New Research Electrical Test strategies
    • RF testing
    • Mixed-signal testing
    • MEMS/Nano testing
  • 3D package modeling
  • TSV inductor design
  • 3D package testing
    • Interconnect modeling
    • Defect testing
    • Overview of existing techniques
    • Research substrate test strategies
  • Repair/diagnosis techniques for modules
  • Summary and Outlook

Who Should Attend?
This course is beneficial to all design and test engineers, scientists, technical managers, design and manufacturing personnel, and production staffs in automotive, consumer, communication, computer, and aerospace industries. Although the course reviews most recent advances in 3D packaging, the course does not assume prior knowledge of these issues and hence is of interest for both experts and newcomers in this area.

Dr. Bruce Kim is a professor of the Department of Electrical Engineering at City University of New York. He has about 300 publications in packaging and testing areas. He has instructed previous PDCs at IEEE EPTC and ECTC conferences. He is a Fellow of IMAPS and received the Outstanding Educator award in 2012. He has also been a student chapter advisor. His research interests are in 3D passive components and testing.

PDC5: Performance-based Roadmaps for Advanced Packaging
Course Leader: Dev Gupta, APSTL
Morning PDC: 8:00am – 12:00pm | $400 (Through 2/19/2016) - $450 (after 2/19/2016)

Course Description:
There have been long delays in both the development and implementation of revolutionary new Adv. Packaging technologies such as 3-d stacking of dice using Thru Silicon Vias (TSVs), especially for high performance but cost driven systems e,g. Smart Phones, which per forecast should have happened by now. To avoid such misses it is necessary for developers of new Packaging technologies to understand SYSTEM performance issues as well. This is what we do in this half day course. We will examine in detail performance metrics e,g. signal integrity that limits the bandwidth of data transfer between a SoC and Memory in a Smart Phone, the power required to transfer this data and aspects of Package design that affect them. We will also review trends in future system & chip designs in terms of these parameters. Next we will explore the performance gaps in current packages that would require transition to other technologies including 2.5 and 3d die stacks. The packages examined are PoP, used extensively in Smart Phones and Tablets, as well as modules in Servers. Then we will examine various 2.5d and 3d technologies already implemented and / or under development and discuss the performance point at which these new and expensive technologies will become indispensable. Lastly we will examine some intermediate technologies that are more cost effective in improving performance and thus amenable to consumer systems.

Who Should Attend?
Planners, Managers and Engineers involved in developing and marketing Adv. Packaging solutions

Dr. Dev Gupta has been involved in pioneering and developing Adv. Packaging technologies that have now become industry standards. In the early '90s at Motorola he led the team that developed electroplated solder bump flip chip technology and robotic bonding tools. Later he developed industry first micro pillar flip chip system including thermo-compression bonding and was put into mass production to build GaAs power amplifiers for mobile phones. At Intel Dr. Gupta managed the development of now standard organic substrates for flip chip microprocessors. At APSTL he has been working on low cost alternatives to TSV based die stacks. He is a frequent speaker and instructor at IEEE and IMAPS events.

Break: 10:00 am - 10:20 am

 

***************
Afternoon Professional Development Courses
1:00 pm - 5:00 pm

PDC6: Introduction to Microelectronics Packaging (PART II)
Course Leaders: Thomas Green, TJ Green Associates LLC
Afternoon PDC: 1:00pm – 5:00pm | $400 (Through 2/19/2016) - $450 (after 2/19/2016)

Course Description:
Advanced Micro Packaging and Emerging Technology

  • QFP (Quad Flat Packs) - QFN (Quad flat No lead)
  • BGA (Ball Grid Array) style packages
  • Wafer-level packaging (WLP)
    • Wafer Level Chip Scale Packaging (WLCSP)
    • Solder bumping processes
    • WLP (Fan In and Fan Out)
    • RDL (Redistribution Layers)
    • Stacked CSPs
  • SIP (System in a Package)
  • MCMs (Multi chip modules)
  • POP (Package on package)
  • PIP (Package in Package)
  • Emerging technologies 2.5 to 3D
    • What is the difference? What are the trends?
    • 3D Chip tacking
  • TSVs (Through Silicon Via) for 3D stacking •
  • Interposer technology
    • Glass vs Silicon
  • Integration of photonic devices
  • Thermal design - How to get the heat out
    • Thermal resistance test methods and JESD51-2A •
  • Electrical design concerns from a packaging perspective
  • Reliability of micro packages
    • Qualification testing of new package designs
    • Common failure modes
    • Plastic and hermetic type packages
  • Industry Roadmaps

Who Should Attend?
This overview course is intended for those unfamiliar with microelectronics packaging technology. People in sales, purchasing, program management, new engineers, managers, equipment/material suppliers, people new to this industry or anyone looking to get a broad industry overview and review of the industry drivers, history and future trends are welcome to attend.

Mr. Tom Green is the principle at TJ Green Associates LLC (www.tjgreenllc.com) a veteran owned small business focused on training and consulting for military, space and medical microelectronic devices. He teaches a variety of public courses around the globe and in plant at major corporations and consults for a variety of medical device companies. He has thirty two years of experience in microelectronics working at positions in industry, academia and government. Tom has demonstrated expertise in die attach, wirebond, visual inspection, hermetic seal and leak testing processes. He has gained valuable experience over the past ten years in packaging and testing of devices for use as Class III medical implants and is often called on as an expert witness for hermeticity related failures. Tom is an active IMAPS member and Society Fellow. He has a B.S. in Materials Engineering from Lehigh University and a Masters from the University of Utah.

PDC7: Emerging Challenges in Packaging
Course Leader: Raja Swaminathan, Intel Corporation
Afternoon PDC: 1:00pm – 5:00pm | $400 (Through 2/19/2016) - $450 (after 2/19/2016)

Course Description:
The course will begin with a broad description of electronic packaging types, functions, trends per industry to introduce the basic concepts of packaging. The first half of the course will focus on the key elements driving the definition of package architectures including form factor, z-height, cost, functional integration complexity, power delivery, high speed signaling and thermo-mechanical interactions with system, to name a few. The interactions between these elements towards enabling a successful package architecture for a given product will be reviewed with examples from different product segments (phones, tablets, PCs, servers etc.). The second half of the course will focus on the package, assembly, test and silicon integration and surface mount challenges towards enabling high volume manufacturing of the package architectures.

Who Should Attend?
The attendees are expected to have an in depth understanding of the fundamentals of packaging.

Dr. Raja Swaminathan is an IEEE senior member and is a package architect at Intel for next generation server, client and SOC products. His primary expertise is on delivering integrated HVM friendly package architectures with optimized electrical, mechanical, thermal solutions. He is an ITRS author and iNEMI technical WG chair on packaging and design. He has also served on IEEE micro-electronics and magnetics technical committees. He has 13 patents and 18 peer reviewed publications and holds a Ph.D in Materials Science and Engineering from Carnegie Mellon University.

PDC8: Polymers in Electronic Packaging
Course Leader: Jeff Gotro, InnoCentrix, LLC
Afternoon PDC: 1:00pm – 5:00pm | $400 (Through 2/19/2016) - $450 (after 2/19/2016)

Course Description:
The course will provide an overview of polymers and the important structure-property-process-performance relationships for electronic packaging. The main learning objectives will be: 1) learn how polymers are used in electronic packaging including die attach adhesives, underfills, mold compounds and substrate materials 2) gain insights on how polymers are used in 2.5D and 3D packaging, 3) learn the key polymer challenges and processes for 2.5D and 3D packaging, 4) learn how polymers testing procedures specific to electronic packaging are used 5) develop a foundation in rheology and rheology issues in electronic packaging. Participants are invited to bring problems for discussion.

Who Should Attend?
Packaging engineers involved in the development, production, and reliability testing of electronic packages would benefit. Those interested in gaining a basic understanding of the role of polymers and polymer-based materials used in electronic packaging will also find this PDC valuable.

Dr. Jeff Gotro has over thirty three years of experience in polymers for electronic applications and composites having held scientific and leadership positions at IBM, AlliedSignal, Honeywell, and Ablestik Laboratories. Jeff is a recognized authority in thermosetting polymers and has received invitations to speak at prestigious Gordon Research Conferences (Thermosetting Polymers and Composites). He has presented numerous invited lectures and short courses at technical meetings, has over 60 technical publications and 21 patents/patent applications. Jeff is a Fellow of IMAPS and was awarded the John A. Wagnon Technical Achievement Award in 2014 for his technical contributions in the area of polymers in electronic packaging. Jeff was an Adjunct Professor at Syracuse University in the Dept. of Chemical Engineering and Materials Science from 1986-1993. Jeff is a member of the American Chemical Society (ACS), the Institute for Management Consultants (IMC), the Forensic Expert Witness Association (FEWA), and IMAPS.

Break: 3:00 pm - 3:20 pm

 

Welcome Reception (All Attendees Are Invited To Attend)
5:00 pm - 7:00 pm

Microelectronics Foundation Texas Hold'Em Tournament (Separate Register Fees - limited seating)
7:00 pm - 10:00 pm

Device Packaging Home

When you register on-line for these courses, you should first select your Device Packaging Conference registration category on page 1, and then under SESSIONS (page 2 of registration) you will select your PDCs. If you DO NOT plan on attending the conference (Tuesday-Thursday), then simply select PDC ONLY on page 1 ($0 charge) and then select your PDCs on page 2.

 

 

 

Device Packaging/GBC Sponsorship
(Need to be ahead of your competition? Join this list today! A few spots remain)

PREMIER SPONSOR:
DPC/GBC Premier Sponsor: ASE US, Inc.

PREMIER SPONSOR:
Golf Hole Sponsor: Amkor Technology

PREMIER SPONSOR:
DPC/GBC Premier Sponsor: NAMICS

Corporate Sponsors
SPTS - Corporate Sponsor
Mentor Graphics - Corporate Sponsor
EMD Performance Materials - Corporate Sponsor
Event Sponsors

Mobile APP Sponsor: SETNA

Mobile "App" Sponsor

Applied Materials - Event Sponsor

Mobile Charging Station &
Evening Panel / Reception

VEECO - Mobile Charging Station & Golf Sponsor

Mobile Charging Station

Shenmao - Event Sponsor

Refreshment Breaks &
Attendee Bag Insert

Poster Session / Happy Hour Sponsor: XIA

Poster Session & Happy Hour Sponsor

 

 

 

Golf/Foundation Sponsors

"Eagle" Sponsor (3 holes):
DPC/GBC Premier Sponsor: ASE US, Inc.

Holes: #1, #12 - Closest to Pin, #16

"Birdie" Sponsor (1 hole):
Golf Hole Sponsor: Amkor Technology

Hole #3 - Longest Drive

"Eagle" Sponsor (3 holes):DPC/GBC Premier Sponsor: NAMICS

Holes: #2, #8 - Closest to Pin, #18

EMD Performance Materials - Corporate Sponsor

Hole #14 - Closest to Pin

Golf Hole Sponsor: Infinite Graphics

Hole #6 - Closest to Pin

MRSI - Break Sponsor

Hole #10

Golf Hole Sponsor: Coining Inc/SPM

Hole #5

Technic - Sponsor - Mobile Charging Station

Hole #7

VEECO - Golf Sponsor

Holes #4 - Longest Putt, #15

ASM Pacific - Hole Sponsor

Hole #11

Golf Hole Sponsor: AGC Electronics America

Hole #13

Golf Hole Sponsor: Dixon Golf

Hole #9 - Straight Drive Competition
Hole #17 - Hole-in-One Competition

Official Media Sponsors
Media Sponsor: MEMS Journal
Media Sponsor: Semiconductor Packaging News
Media Sponsor: Chip Scale Review
Media Sponsor: MEPTEC
Media Sponsor: Webcom - Antenna Systems & Technology
Media Sponsor: Webcom - Electronics Protection
Media Sponsor: Webcom - Thermal News
3D Incites - Media Sponsor
Solid State Technology - Media Sponsor
     



CORPORATE PREMIER MEMBERS
  • Amkor
  • ASE
  • Canon
  • EMD Performance Materials
  • Honeywell
  • Indium
  • Kester
  • Kyocera America
  • Master Bond
  • Micro Systems Technologies
  • MRSI
  • NGK NTK
  • Palomar
  • Plexus
  • Promex
  • Qualcomm
  • Quik-Pak
  • Raytheon
  • Specialty Coating Systems