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Advanced Technical Program
Tuesday, November 18 thru Thursday, November 20, 2003




Tuesday, November 18, 2003

TA1
Advanced Materials for Electronics Packaging
Chairs: Herbert J. Neuhaus, Scimaxx Solutions; Lee Gaherty, Scimaxx Solutions
8 am - 11:25 am

Advanced materials are a key element in microelectronics and packaging. The leading edge of materials development and application are reported, including Organic Electronics and OLEDs, LCPs, Opto-Electronic Packaging and NanoTechnology.

Organic Electronics: An Overview
Philip Garrou, Mitchell Dibbs, Paul Townsend, David Brennan, Adam Laubach, Dow Chemical - Advanced Electronic Materials

Advances in Deposition of OLEP Materials via Piezoelectric Ink Jet
Linda T. Creagh, Spectra, Inc.; Susanne Heun, Covion Organic Semiconductors GmbH; Neil Tallant, Avecia Ltd. - UK

Polymeric Material Solutions and Performance Criteria for Jettable Fluid Delivery Assembly and Harsh Environment Protection
Susan Krawiec, Chih-Min Cheng, Robert Palmer, Emerson & Cuming

The Liqid Crystal Polymer Packaging Solution
Brian Farrell, Paul B. Jaynes, Tom Tiano, Jeremy Bowman, Foster-Miller, Inc.

Epoxies for Opto-electronic Packaging; Applications and Materials Properties

Michael J. Hodgin, Epoxy Technology, Inc.

Middle-Permittivity Dielectric Compositions for Functional LTCC Substrate
Jae-Hwan Park, Byung-Kook Kim, Young-Jin Choi, Dong-soon Shin, Jae-Gwan Park, Korea Institute of Science and Technology

Electrical and Mechanical Characterization of Nanotube Filled Conductive Adhesives
Jing Li, Janet K. Lumpp, Moatasem Abu-Haleeqa, Eric Grulke, University of Kentucky


TA2
Advanced Thick Film Systems
Chairs: Harry Kellzi, Teledyne Electronic Technologies; John Menaugh, Dupont Microcircuit Materials
8 am - 11:25 am

The range of topics includes specialty inks for radiation sensors and varistors, automotive electronics, designing LTCC modules, lead-free materials and fine line printing for high frequency applications.

Fine Line Printing Technologies for Microwave and Millimeter Wave Applications
Liang Chai, Cristie Lopez, Aziz Shaikh, Ferro Electronic Material Systems.;
Shigekatsu Ohnishi, Masahisa Kakinuma, Taiyo Ink Mfg. Co., Ltd.

Novel Failure Mechanism Involving the Motion of Oxygen ION Vacancies in Chip Capacitors
Roy Tom Coyle, Jr., Northrup Grumman Space Tech

Thick Film Initiators for Automotive Applications
Walter Smetana, R. Reicher, H. Homolka, Vienna University of Technology

Cerium Oxide Based Screen-Printed Thick Film Components as Gamma Radiation Sensors
Khalil Arshak, Olga Korostynska, University of Limerick

Automotive Module Design with Zero Shrink Composite LTCC
Frans Lautzenhiser, Heraeus Inc. - Circuit Materials Division; Terry Bloom, CTS Corporation; Annette Kipka, Christina Modes, Heraeus GmbH & Co., KG

A Case Study of Lead Free Thick Film Conductors with Lead Free Solders
Theresa D. Sims, Heraeus Inc., Circuit Materials Division

Performances of High Voltage Screen-Printed ZnO Varistors
Marie-Pascale Martin, Hélène Debeda-Hickel, Claude Lucat, Francis Menil, University of Bordeaux


TA3
Fine-Pitch Interconnection Technologies I
Chair: Bruce Romenesko, The Johns Hopkins University/APL; Roupen Keusseyan, DuPont Microcircuit Materials
8 am - 11 am

The papers in this session cover performance limits of the designs or materials used in high density interconnections. Package types include both organic- and ceramic-based packages.

Quality and Reliability of 100 MU Pitch Flip Chip ICS on Flexible Substrates with Adhesive Interconnections
J. de Vries, Philips Center for Industrial Technology

A Study of Non-Flow Under-Fill Flip-Chip Bonding Process for LCP Based COF Components
Satoshi Furuki, Hiroyuki Takahashi, Chihiro Hatano, Makoto Yamasaki, Nippon Steel Chemical Co., Ltd.

A Comparison of Electromigration and Thermal Fatigue Performance Between Thin and Thick Film UBM
Po Jen (Robert) Zheng, C.Y. Hung, Z. J. Lee, C. W. Lee, C. S. Chung, J. D. Wu, Advanced Semiconductor Engineering (ASE), Inc.

High-Performance Liquid Crystalline Polymer Printed Circuits
Katsufumi Hiraishi, Katsumi Takata, Isamu Takarabe, Kazunori Ueda, Nippon Steel Chemical Co., Ltd.

System Packaging for Robust LGA Interconnect Technology in High Performance Computing Applications
Mark Hoffmeyer, John G. Torok, John L. Colbert, John S. Corbin, William L. Brodsky, IBM Corp.

An Approach to Custom CSP Package Fabrication
Joseph W. Soucy, Henry G. Clausen, Charles E. Busa, Fredrick J. Kasparian, Draper Laboratory


TA4
Advanced Wirebonding
Chairs: Bruce Romenesko, The Johns Hopkins University/APL; Lee Levine, Kulicke & Soffa Ind. Inc.
8 am - 11 am

This session deals with the challenges encountered by wire bonding at fine pitch, low temperature and on copper/Low K dielectric surfaces.

Process Optimization for the 0.13 Cu /Low K (Black Diamond) Dual Damascene Interconnection
Li Hongyu, Su Yong Jie, Tsang Chi Fo, Bliznetsov Vladimir, Sohan Singh Mehta, Zhang Lin, Singapore Institute of Microelectronics

Impact Analysis of Wirebonding on Cu/Low-K Structures
Chang-Lin Yeh, Yi-Shao Lai, Jenq-Dah Wu, Advanced Semiconductor Engineering, Inc.

Gold Ball Bonding on Copper Substrates at Ambient Temperatures
Ivan Lum, Naren Noolu, Norman Zhou, University of Waterloo

Wirebonding on Copper Low-k Wafers
Frank Keller, Jon Brunner, Kulicke & Soffa Ind., Inc.; Tony Pan, Applied Materials

Morphology of Ball Bonds at <50um Pitch
Lee R. Levine, Jon Brunner, Kulicke & Soffa Ind. Inc.

Dynamic Characterization of NiTiNOL for Interconnection Applications
Shivananda Pai Mizar, Ryszard J. Pryputniewicz, Worcester Polytechnic Institute


TA5
Passive Integration in LTCC, PWB and On Chip
Chair: Robert H. Heistand II, AVX Corporation
8 am - 11:25 am

The integration of passive elements into substrates and packages continues to break new ground. Examples of passive integration technologies, techniques and design attributes are presented for LTCC, PWB and on chip applications. The final paper compares LTCC and HDI organic technologies for RF applications.

A 5-6.5 GHz LTCC Power Amplifier Module
N. Ilkov, W. Bakalski, R. Matz, W. Simbürger, O. Dernovsek, S. Walter, P. Weger, Siemens AG

Modeling and Analysis of LTCC Stripline for Multi-Layer Packaging: Effect of Embedded Pores and Sharpened Edges
Jae Hyuk Jang, Seung Gyo Chung, Byung Gyu Chang, Samsung Electro-Mechanics

Performance of Co-Fired Buried Resistors in A6S Tape
Michail Moroz, Ferro Corporation

Wafer-Level Packaging Technology for Low-Loss On-Chip Transmission Lines and Inductors
Geert Carchon, X. Sun, W. De Raedt, E. Beyne, IMEC-MCP/HDIP

Laser Trimmed Thin Film NiCr Embedded Resistor Tolerance
Sid Clouser, Jiangtao Wang, Rocky Hilburn, Gould Electronics

Electrical Performance Advantages of Ultra-Thin Dielectrics in PCBs
Joel S. Peiffer, 3M

Comparison of HDI Organic and LTTC Substrate Technology with its Potential for RF Module Application
Grit Sommer, Gerhard Fotheringham, W. John, H. Reichl, FhG-IZM Berlin


TP1
Developments in Materials
Chair: Herbert J. Neuhaus, Scimaxx Solutions
2 pm - 4:35 pm

This session reports on the real-world application of some recent materials developments, including lead-free solder, adhesivies for stacked die, and some new ceramic materials.

Development of Low-K Encapsulating Film for Stacked Packages
Akiko Matsumura, Kazuki Uwada,Yuji Hotta, Nitto Denko Corporation

Application of Spacer Filled Silicone Die Adhesive in Stacked Chip Technology

Xuan Li, R. Wayne Johnson, Auburn University; Thomas E. Noll, Michael Watson, Dow Corning Corporation

Synthesis of Ferroelectric Films for Integral Capacitors - Processing, Characterization and Integration
Devarajan Balaraman, P. Markondeya Raj, Swapan Bhattacharya, Isaac Abothu, S. Dalmia, Lixi Wan, Michael D. Sacks, Madhavan Swaminathan, Rao Tummala, Georgia Institute of Technology

Cofireable Transfer Tape
Richard L. Wahlers, Alvin Feingold, Merrill Heinz, Electro Science Laboratories

The Investigation of Lead Free Package Reliability
Jeffrey C. B. Lee, Advanced Semiconductor Engineering


TP2
High Density Packaging

Chairs: Rajen Chanchani, Sandia National Laboratories; Andrew Strandjord, IC Interconnect
2 pm - 5:25 pm

New technologies on ultra-thin, high density substrate, 3-D die-stacking and embedded passives will be presented in this session.

Three-D Vertically Stacked Electronic Structures for Array Sensors
Raymond A. Fillion, Robert Wojnarowski, Chris Kapusta, Rich Saia, Kris Kwiatkowski, Jim Lyke, GE Global Research Center

SIP Solution for High-End Multimedia Cellular Phone
Heung-Kyu Kwon, Tae-je Cho, Ki-won Choi, Jong-bo Shim, Se-Nyon Kim, Yoon-Hyuk Lim, Dong-gil Shin, Un-ha Shin, Se-yong Oh, Samsung Electronics Co., Ltd.

New Approaches to 3-D Interconnections Systems in Package Applications
Christian M. Val, 3DPlus

Ultra-Thin High-Density Packaging Substrate for High-Performance CSP and SiP
Tadanori Shimoto, Kazuhiro Baba, Hideya Murai, Takehiko Maeda, Keiichirou Kata, Wataru Urano, Hironori Ohta, NEC Corporation

Stencil Printing Technology for 100µM Flip Chip Bumping
Dionysios Manessis, Rainer Patzelt, Andreas Ostmann, Rolf Aschenbrenner, Herbert Reichl, Technical University of Berlin

Industrial Scale Manufacturing Process for Embedding Active Components Inside Organic Substrate
Petteri Palm, Risto Tuominen, Imbera Electronics Oy

Crosstalk of Wiring in 3D Stacked Multichip Package for a System-in-Package
Jarmo J. Tanskanen, Janne Toikka, Eero O. Ristolainen, Tampere University of Technology


TP3
Fine-Pitch Interconnection Technologies II
Chair: R. Wayne Johnson, Auburn University
2 pm - 5:25 pm

Recent advances in fine pitch interconnection technologies, both flip-chip and wire-bond, will be discused in this session.

Flip Chip Mounting Technology for MID
Yoshihiko Yagi, Michirou Yoshino, Koujirou Nakamura, Kazuto Nishida, Yukihiro Otani, Fumikazu Harazono, Naoto Ikegawa, Matsushita Electric Industrial Co., Ltd.

Filled No-Flow Underfilling - Process and Materials
Ning-Cheng Lee, Wusheng Yin, Hong-Sik Hwang, Indium Corporation of America

Very High Pin Count Flip Chip Assembly using Conductive Polymer Adhesives
James E. Clayton, Polymer Assembly Technology

Novel Fine Pitch Interconnects
Richard LaBennett, MCNC Research and Development Institute (MCNC-RDI)

Application of 35µm Pitch Wire Bonding Technology to High Density Package
Yasuhide Ohno, K.Ohmisha, T.Takado, K.Noguchi, Kumamoto University

Bondability, Reliability and Yield Benchmarks for High Volume, Specialty Gold Fine Bonding Wire
Michael Zasowski, Gery Lovitz, Williams Advanced Materials

Laser Direct-Write of Fine Features for Low Temperature Co-fired Ceramic (LTCC) Applications
David Liu, Chengping Zhang, Todd Kegresse, Scott A. Mathews, John Graves, Potomac Photonics, Inc.


TP4
Power Packaging Technologies
Chair: Douglas C. Hopkins, State University of New York at Buffalo
2 pm - 5:25 pm

New heat sink techniques start the session with one approach using nano-layered foils for 10X improvement. Unique device packaging approaches are next and include wafer level packaging of power FETs.

Multiscale Multiphysics Analysis of Wirebonds for Electronic Packaging
Ryszard J. Pryputniewicz, Patrick W. Wilkerson, Andrzej J. Przekwas, Worcester Polytechnic Institute

Manufacturing and Evaluation of Thermal Expansion Behavior of Discontinuous Pitch Graphite Fiber Reinforced Copper Alloys for CTE Matching Heat Sink Applications
James A. Cornie, Shiyu Zhang, Metal Matrix Cast Composite, LLC

A Tenfold Reduction in Interface Thermal Resistance for Heat Sink Mounting
Timothy P. Weihs, David Van Heerden, Omar Knio, Reactive NanoTechnologies

Thermal Performance and Microstructure of Lead-free Solder Die Attach Interface in Power Device Packages
Dan Huff, Dimos Katsis, K. Stinson-Bagby, G-Q Lu, J. Daan van Wyk, Virginia Polytechnic Institute and State University

New Generation of Wafer-level Packaging Delivers Higher Levels of Power and Reliability Performance for Power MOSFET Devices
Mohammed Kasem, E. Tjhia, C. Chen, Vishay-Siliconix

Development of SOIC Exposed Pad Package for Dual Die Power Products
Mervi Paulasto-Kröckel, Anton Kolbeck, Gary Johnson, Hubert Wieser, Christina Bohm, Motorola

Development of Silicon-Carbide (SiC) Static-Induction-Transistor (SIT) Based Half-Bridge Power Converters
Alexander B. Lostetter, Kraig Olejniczak, Alan Mantooth, Aicha Elshabini, University of Arkansas


TP5
Printed Wiring Boards
Chairs: Timothy G. Lenihan, TGL Consulting; Peter Ludlow, Engineering Management Associates, Inc.
2 pm - 5:25 pm

The Printed Wiring Board Session is well balanced to cover a broad range of industry needs and new developments. Topics that will be covered include new processes, fine pitch manufacturing, new materials, design issues, thermal modeling, reliability evaluations, and systems applications.

Characteristics of Wet Etching of Copper Foil for Printed Circuit Boards by using Ferric Chloride Solution
Katsutoshi Matsumoto, Shingo Funahashi, Shoji Taniguchi, Tohoku University

Electrochemical Migration of Immersion Silver Finish: Test Vehicle and Material Evaluation
Jiming Zhou, Robert Clawson, Phil Wittmer, Rick Snyder, Jerry Badgett, Delphi Delco Electronics Systems

Evaluation of High Temperature Overmold Compounds for Manufacturing of Laminate Based Leadfree System in Package
Mohammed A. Wasef, Michael J. Anderson, ANADIGICS Inc.

Manufacturing Fine Pitch Flexible Substrate for MCM Module
Hyuek-Jae Lee, Jin Yu, KAIST

Board Level Underfill for CSP Applications
Prakorn Vijchulata, AMD Thailand

Thermal Investigation for an Advanced Graphic Module Board
Eason Chen, Carol Liang, Jeng Yung Lai, Yu-Po Wang, CS Hsiao, Siliconware Precision Industries Co., Ltd.

Vertically High Density Interconnection for Mobile Application
Takayoshi Katahira, Ilkka Kartio, Nokia - Japan Co., Ltd.; Hiroshi Segawa, Ibiden Co., Ltd.

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