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Monday PDCs
Monday, November 17, 2003

All PDCs run 9 am - 5 pm, unless otherwise noted.
All PDCs will be held at the Hynes Convention Center.

M1 | M2 | M3 | M4 | M5 | M6 | M7 | M8 | M9 | M10

Packaging Challenges and Solutions for 10 Gb/s and 40 Gb/s Systems
Course Leaders:
Roberto Coccioli and Hassan Hashemi, Inphi Corporation and Conexant Systems

Course Description:
The objectives of this course are to review challenges in 10G and 40G IC packaging considering requirements posed by mixed IC technologies and system architecture. Moreover, it is intended to review the technologies available to realize package and board interconnects assessing their relative performance and their impact on signal integrity on high speed digital signaling. The course material is based upon the instructors' experience on current practices used for GHz IC packaging for telecom, datacom, and storage infrastructure applications. The course is designed for engineers or engineering managers who want to understand more about technical challenges of high-speed packaging and the unique requirements posed on technology selection and design to assure the achievement of stringent electrical and thermal performance in cost-performance efficient manufacturing.

What will you learn?
After completing the course, you will be familiar with:
· Review of requirements for 10G and 40G interconnect technologies posed by mixed IC technologies and system architecture
· Substrate Technologies for 10Gb/s and 40Gb/s Applications - Ceramic
· Thick-Film, Thin-Film, HTCC, LTCC, Etched Thick Film - Organic
· PTFE glass fiber, PTFE ceramic
· Effects of interconnects on Signal Integrity
· Wire bonds vs. Flip-Chip
· Transmission Lines: CPW, Micro strip, Strip line
· 10Gbps and 40Gbps IC package examples
· Connectorized packages for 10 and 40Gbps ICs - Connector types
· Threaded, Push-on - Assembly and backside design - Examples
· Issues and challenges - Manufacturing tolerances and their effects
· Controlled impedance lines
· Transitions
· Conclusions

Who should attend?
The course is intended for both the packaging expert (Electrical and Mechanical Engineers) as well as persons new to the field. The course will review the existing substrate infrastructure capability and explore ways to extend its use to high volume packaging of ICs for telecom, storage, and datacom applications. The information presented will include the theoretical background with practical methods for implementing a design. These same techniques can be applied to other high frequency single or multichip designs.

Hassan Hashemi is Executive Director of Advanced Packaging & Product Development at Mindspeed Technologies, a Conexant Systems Business in Newport Beach, California. He is currently managing design and development of single and multi-chip packages for broadband digital, mixed-signal, and RF devices used in infrastructure communication and storage applications. He holds a Masters degree in electrical engineering from the University of Texas at Austin, and has over 18 years of experience in microelectronics package design, manufacturing, and product development. Prior to joining Conexant, he was a senior member technical staff at Microelectronics and Computer Corp. and Advanced Micro Devices. He holds 13 US patents, has authored three book chapters and over 40 technical papers in the areas of high-speed package electrical and thermal design and implementation.

Roberto Coccioli is Senior Design Engineer at Inphi Corporation, Westlake Village, CA, where he is currently working on development of ceramic and metal packages for GaAs and InP ICs for 10Gbps and 40Gbps systems. Prior to joining Inphi, he was a design engineer at Conexant Systems, Inc, Newport Beach, CA, where he worked on modeling, design and characterization of high-density organic and ceramic packages for Si and GaAs ICs for high-speed digital communications, organic packages for RFICs, and embedded antennas. Coccioli holds a Ph.D in Electrical Engineering from the University of Florence, Italy, and has been Visiting Scholar and Postdoctoral Fellow at UCLA from 1996 to 1999,where his research focused on numerical methods for electromagnetics and its applications to the analysis of microwave passive and active circuits, antennas, and photonic bandgap materials. He holds 1 US patent, has co-authored one book, and over 25 papers in the area of microwave and electromagnetic modeling. Roberto Coccioli is a member of IEEE.

Process Engineering Fundamentals
Course Leader:
Thomas J Green, National Training Center for Microelectronics


Advanced Materials for Microelectronic, Optoelectronic and MEMS/MOEMS Packaging and Thermal Management
Course Leader:
Dr. Carl Zweben, Advanced Packaging Materials and Composites Consultant

Course Description:
Materials impact performance, reliability, manufacturing yield and cost. Increasingly, traditional packaging materials are failing to meet the requirements of new microelectronics, optoelectronic and MEMS/MOEMS packaging designs. In response, numerous advanced composites and monolithic materials have been, and are continuing to be developed. Property improvements include: thermal conductivities ranging from extremely high (over 4X copper) to very low; low, tailorable coefficients of thermal expansion; electrical resistivities ranging from very low to very high; extremely high strengths and stiffnesses; low densities; and low cost, net shape fabrication processes. A new thermal interface material has a reported thermal conductivity of 750 W/m.K. Payoffs include: improved thermal performance; reduced thermal stresses and warpage; improved fiber alignment; simplified thermal design; possible elimination of thermal interface materials, liquid cooling and heat pipes; weight savings up to 85%; size reductions up to 65%; increased reliability; reduced electromagnetic radiation emissions; increased manufacturing yield; and potential cost reductions.

Advanced materials, such as Al/SiC metal matrix composites (first used in packaging by the course leader) and carbon fiber-reinforced polymer matrix composites, are now being used in a growing number of high volume commercial and aerospace production applications at the rate of millions of piece parts annually. Components include heat spreaders, microprocessor heat sinks, air-cooled and liquid-cooled cold plates, microwave modules, power semiconductor modules, optoelectronic packages, and heat pipe over molds. Products using these materials include servers, cellular telephone handsets and base stations, laptop computers, hybrid and electric vehicles, trains, wind turbine generators, data storage drives and aerospace/defense electronic systems. We cover traditional packaging materials and the large and increasing number of advanced materials, including: silicon carbide particle-reinforced aluminum (Al/SiC) and copper; carbon fiber-reinforced polymer matrix composites; aluminum and copper reinforced with discontinuous and continuous carbon fibers; diamond particle-reinforced aluminum, copper and silicon carbide; beryllia particle-reinforced beryllium; discontinuous carbon-graphite-reinforced aluminum; silicon-aluminum; silver/"Invar;" carbon/carbon composites; "natural graphite;" thermal- annealed- and highly oriented pyrolitic graphite; "ThermalGraph;" silicon carbide/silicon and others. This course provides an in-depth discussion of the materials, their properties, the processes by which they are made, and where they are being used. We also look at future directions.

Who should attend?
Engineers, scientists and managers involved in microelectronic, optoelectronic and MEMS/MOEMS packaging design, production and R&D. Packaging material suppliers.

Dr. Zweben, an independent consultant, has directed development and application of advanced packaging materials for over 30 years. For many years, he was Advanced Technology Manager and Division Fellow at GE Astro Space, later acquired by Lockheed Martin, where he directed the Composites Center of Excellence. Other affiliations have included Du Pont, Jet Propulsion Laboratory and the Georgia Institute of Technology NSF Packaging Research Center. Dr. Zweben was the first, and one of only two winners of both the GE One-in-a-Thousand and Engineer of the Year awards. He is a Fellow of ASME, ASM and SAMPE, an Associate Fellow of AIAA, and has been a Distinguished Lecturer for AIAA and ASME. He has published and lectured widely on advanced packaging materials and composites.

Fiber Optics Structures: Design for Reliability
Course Leader:
E. Suhir, University of Illinois at Chicago and ERS Co.


Die Products - Overcoming the Domination of Moore's Law
Course Leader:
Larry Gilg, Die Products Consortium


Wire Bonding in Microelectronics
Course Leader:
George G. Harman, National Institute of Standards and Technology

Course Description:
Wire bond manufacturing defects range typically from about 1000 to 100 ppm, with exceptions to >10,000 and <50 ppm. In order to achieve the lower numbers in production, one must understand all of the conditions that affect both bond yield and reliability (since they are interrelated). This course will discuss many large- and small-wire bonding problems, as well as subjects of specific interest to hybrid/MCM device bonding. In addition, a number of advanced topics, such as high yield, fine pitch, and flex bonding will be covered. New developments (e.g., high frequency ultrasonic bonding), are included along with a major discussion of wire bonding to multichip modules and other soft substrates. Wire bond testing and metallurgy (covering both aluminum and gold bonds); intermetallic compounds; cleaning for yield and reliability; failures resulting from electroplating; mechanical problems in wire bonding; new bond technologies and developments; how ultrasonic bonds are formed, and the metallurgy of gold and aluminum wire. It concludes with methods of implementing TAB and Flip Chip by using wire bonding techniques.

Who should attend?
Engineers in R&D, QA, QC, manufacturing, process development, and advanced technicians. It is assumed that participants have some familiarity with wire bonding and general device assembly technologies.

Special Course Materials:
All attendees will receive a complimentary copy of Wire Bonding in Microelectronics, by George Harman, McGraw Hill, NY, 1997 (List price $65), as well as course notes and explanations.

Mr. Harman is a Fellow of the National Institute of Standards and Technology (NIST), Department of Commerce. He received a BS in Physics from Virginia Polytechnic Institute & State University and a MS in Physics from the University of Maryland. Mr. Harman has published 50+ papers, two books on wire bonding, and holds four U.S.Patents. He was the 1995 President of ISHM and is a Fellow of IMAPS and the IEEE. He has received numerous awards for his work from IMAPS, IEEE, DVS and others. He has presented numerous talks, and has taught courses for the University of Arizona and IMAPS for over 15 years, as well as the IEEE, to name a few. He has presented many papers and given courses in the USA, Europe, and Asia.

Integrated Circuit Packaging Trends and Assembly Options
Course Leader:
William J. Greig, Greig Associates

Course Description:
This course addresses the impact of both the Integrated Circuit, and End Product requirements ("smaller, better, cheaper"), on packaging, assembly, and substrate interconnects. It focuses on packaging trends, namely, the Ball Grid Array (BGA) and Chip Scale Package (CSP), Multichip Packaging (MCP) and alternative formats, Chip On Board (COB), and 3-D initiatives at both the chip and package levels. Assembly options available for attachment of the IC in each case will be discussed with major emphasis on Flip Chip. The course also covers the High Density Interconnect (HDIs) substrates. The various substrate technologies (Thick Film, Co-fired Ceramic, and Thin Film) that are employed in the manufacture of packages and component assemblies for MCPs will be reviewed. Finally, the latest developments in PWBs, with high density, fine lines, and micro vias employing sequential processing (Build Up Technology - BUT) will be reviewed. Throughout the course, technical issues will be emphasized and reliability concerns addressed where appropriate.

Special Course Materials:
All attendees will receive a complimentary copy of the book, "Hybrid Microcircuit Technology Handbook," J. Licari, L. Enlow, 2nd Edition, Noyes Publications, 1998 (List price $125).

Who should attend?
The course provides an overview of microelectronic packaging and assembly and is intended for individuals in any way involved with electronics manufacturing. While introductory in nature it discusses current status and future trends, it is directed towards both the experienced or inexperienced engineer and technician, and management personnel with the "need to know." It should be of particular interest to those in support activities such as procurement, quality assurance, marketing and sales, and program office by providing a technology base in support of strategic planning and implementation.

Bill Greig is currently an independent consultant specializing in microelectronic packaging and assembly. His previous work experiences include RCA Semiconductor, General Electric Co., Lockheed Electronics, and NASA. His areas of expertise cover semiconductor wafer processing and assembly, hybrid circuit manufacture, and printed wiring board fabrication. He is experienced in assembly technologies such as chip & wire, TAB, and flip chip. He has been granted 6 patents and has published or presented numerous papers at the various technical symposia. He has developed and presented courses at national symposia and participated in CEE programs at U. of Wisconsin, Lehigh University and Rutgers University. He is a member of SMTA and IMAPS in which he is a Fellow, and Past President of the Garden State Chapter.

Technology of Screen Printing
Course Leaders:
Art Dobie, SEFAR America & Rudy Bacher, DuPont

Course Description:
The purpose of this course is to increase the understanding of the screen printing process thereby improving production yield and quality. The critical and integrated components for screen, such as frames, screen mesh and emulsion are presented. Presented are some of the latest advancements in the screens, the compositions and the printing process that enable screen printing to meet future circuit density requirements. The course is applications-oriented in terms of how to optimize the screen printing process; how to specify and use screens; rheology properties that affect the print; minimizing printing defects and trouble-shooting problems related to the screens and the printing process.

Who should attend?
This course is intended for production and process engineers, and others interested in learning how to optimize and increase the uses of the screen printing process.

Art Dobie is Manager of Screen Technology for SEFAR America (MEC) in Mount Holly, NJ. He has been with MEC more than 22 years since receiving his BS in Screen Printing Technology in 1980 from California University of Pennsylvania's School of Science and Technology. Art is an original instructor of IMAPS' Technology of Screen Printing Professional Development Course, and has delivered many technical papers and presentations relating to screen printing technology to the microelectronics industry at the local, National and International levels. Art Dobie has held numerous offices in the Keystone Chapter, including president. Mr. Dobie was Co-Chair of Exhibits for ISHM '97 and initiated the IMAPS Educational Foundation Silent Auction. Art is a Fellow of the Society of IMAPS and an inducted member of the Academy of Screen Printing Technology.

Rudy Bacher has worked 37 years in Thick Film Technology for DuPont Research and Development as a Ceramic Engineer and currently as a Development Associate. He is a recipient of the ISHM Technical Achievement Award-1984; Corporate Marketing Excellence Award-1994; and IMAPS Instructor "Technology of Screen Printing" 1990-1998.

1/2 Day Course - AM
M9 runs 9 AM - Noon

Lead-Free Electronic Packaging & Assembly: Technology and Manufacturing
Course Leader:
Dr. Jennie S. Hwang, H-Technologies Group, Inc.

Course Description:
Environment-friendly manufacturing and begin end-use products that are ultimately safe at the end of product life cycle is essential to technology-business competitiveness. This is a continuing challenge to the industry. Based on the newly released book: "Environment-Friendly Electronics-Lead Free Technology," this course will cover all relevant topics and issues including global legislative status, technological base, material fundamentals, product assessment, cost, applications, processes and other manufacturing considerations. The viable lead-free solder alloys will be ranked in their key performance parameters to facilitate implementation. The courses will emphasis on practical applications in the SMT infrastructure including reflow and wave soldering. Information is applicable to all types of electronic packages and assemblies including QFP, BGA, flip chip and CSP.

What will you learn?
· Driving forces and industry trends
· Legislation status - US, Japan, Europe
· General introduction of role of lead and key illustrations
· Lead-free technology base
· Comparison of viable lead free alloys
· Alloys wetting vs. manufacturing performance in reflow & wave soldering
· Reflow criteria vs. PCB assembly vs. lead free solder composition
· Fillet-lifting issue
· Lead-free solder balls and solder bumping for BGA, CSP and flip chip
· Lead-free PCB Surface Finishes
· Lead-free component coatings
· Tin whisker issue
· Differentiation of solder joint failure modes between Sn/Pb and lead-free
· Manufacturing factors - cost vs. performance
· Selection criteria of various lead-free alloys
· Global implementation status - recommendations to manufacturers

Special Course Materials:
All attendees will receive a copy of the newly released book entitled: "Environment-Friendly Electronics - Lead-free Technology," published by Electrochemical Publications, LTD, Great Britain (List Price US $238).

Who should attend?
Management, engineers, technicians, project managers, purchasing managers, QA engineers, researchers and others involved in electronics materials, electronics manufacturing and decision-making in forming and implementing manufacturing strategies through a general understanding of lead-free solders and environment-friendly electronics manufacturing.

Dr. Hwang received her doctorate in Materials Science & Engineering from Case Western Reserve University and two masters from Columbia University and Kent State University's Liquid Crystal Institute She has been a major contributor to Surface Mount Technology since its inception. Serving as an advisor to major OEMs/ODMs, U.S. government and contract manufacturers, she has provided solutions to many challenging production-floor problems in the last 20-years of SMT establishment, including U.S. F-22 program. Among her many honors and awards, Dr. Hwang is elected to the National Academy of Engineering, inducted to the WIT International Hall of Fame, and received Distinguished Alumni Award from her alma maters. She also received the U.S. Congressional Certificate of Recognition, YWCA Women of Achievement Award, and was named one of the 28 R&D-Stars-to-Watch by Industry Week. She has held various "Woman pioneering" capacities. She is an invited lecturer/keynote speaker worldwide and the author of over 200 publications, including the sole authorship of five internationally used textbooks and a co-author of several books related to electronic packaging and assembly technologies. She writes a monthly column for SMT Magazine. Contributing to corporate governance, education and community, Dr. Hwang has served on various corporate, educational, and civic boards. She is a member of various professional organizations, having served as the National President of Surface Mount Technology Association. She has held executive positions with Lockheed Martin, SCM and IEM Corp., currently the president of H-Technologies Group Inc., providing technology and business solutions to the electronics industry.

1/2 Day Course - PM
M10 runs 1 PM - 5 PM

Advanced Packaging Developments and Trends
Course Leader:
E. Jan Vardaman, TechSearch International, Inc.

Course Description:
The semiconductor industry has seen a major shift from leads to balls and from wires to bumps. This requires infrastructure developments and promises new opportunities. This course will cover developments and trends in area array packages. Ball grid array (BGA) packages are increasingly found in products including personal computers, portable communications devices, workstations/servers, mid-range and high-end computers, network and telecommunications systems, and even automotive applications. Package trends and new developments are described. Driven by the demand for smaller, lighter, thinner portable products has come the development of chip scale packages (CSPs). Discussed are the various types of CSPs in volume production and new developments such as wafer level packages. Flip chip's advantage over wire bond interconnection includes higher density mounting, improved electrical performance, and improved reliability for many applications. New applications for flip chip are described. Also included are trends such as bump pitch, bump metallurgy, and substrate feature sizes.

What will you learn?
· Driving forces and industry trends
· New applications for BGAs and CSPs
· Wafer level packaging applications
· Flip chip applications
· New package constructions
· Pitch trends
· Lead-free developments and trends
· Infrastructure developments
· Substrate developments
· Underfill material and equipment developments

Who should attend?
Managers, engineers, project managers, purchasing managers, sales and marketing personnel.

E. Jan Vardaman, President and Founder, TechSearch International, Inc., Austin, Texas. Ms. Vardaman analyzes international developments in the field of semiconductor packaging and assembly. Previously she served on the corporate staff of Microelectronics and Computer Technology Corporation (MCC) in Austin, Texas, where she analyzed international developments in semiconductor packaging and assembly. She is the editor of Surface Mount Technology: Recent Japanese Developments, published by IEEE. She is a columnist with Circuits Assembly magazine, and author of numerous publications on emerging trends in semiconductor packaging and assembly. She served on the NSF sponsored World Technology Evaluation Center (WTEC) study team involved in investigating electronics manufacturing in Asia and a U.S. Government study mission to China. She is a member of IEEE's CPMT society Board of Governors and IMAPS. Ms. Vardaman received her B.A. in Economics and Business from Mercer University in 1979 and her M.A. in Economics from the University of Texas in 1981.


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