Advance Technical Program
Thursday, November 18, 2004

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Unique Fabrication Processes
Chair: Jianbiao (John) Pan, California Polytechnic State University
8 am - 9:25 am

The rapid pace of innovation in electronics manufacturing technology makes for a constant demand for newer applications. This session presents two applications of ink-jet printing in electronics fabrication and a new diagnostic method in flip chip assemblies.

Low-Cost Solar Cell Fabrication by Drop-On-Demand Ink-jet Printing
Virang G. Shah, David B. Wallace, Kurt Wachtler, MicroFab Technologies, Inc.

Digitally Printing Electronics with Piezo Ink Jet
Linda T. Creagh, Spectra, Inc.

New Methods of the Nondestructive Quality Control and Reliability Forecasting for Modern Flip Chip Assemblies and Electronic Devices
Gennadii P. Zhigal’skii, Moscow Institute of Electronic Technology - Technical University

Integrated Low Cost Optoelectronics
Chair: Frank G. Shi, University of California – Irvine
8 am - 9:25 am

This session addresses some important issues which are critical to the low cost packaging of ultra small form factor 10GB integrated transmitters, optical interconnection modules and high power LEDs.

Ultra Small Form Factor 10GB Low Cost Integrated Transmitter
Marion Volpert, F. Berger, F. Marion, C. Louis, P. Grosse, C. Rossat, S. Bernabe, R. Stevens, CEA-LETI

Challenges of Pb-free Packaging of High-Power LEDs
Shatil Haque, Serge Rudaz, Chris Elpedes, Fernando Teixeira, Dan Steigerwald, Jerome Bhat, Frank Wall, Bob Steward, Paul S. Martin, Lumileds Lighting

Alignment Arrangement for Low-Cost Embedded Optical Interconnection Module
Takeshi Ohno, Masaki Ono, Susumu Wakamatsu, Ayako Kawamura, Toshikazu Horio, Atsushi Suzuki, Toshifumi Kojima, Toshikatsu Takada, NGK Spark Plug Co., Ltd.

Flip Chip Bumping and Wafer Applied Underfill
Chair: Alan Grieve, Aguila Technologies, Inc.
8 am - 9:25 am

Techniques for fine-pitch, flip-chip wafer level bumping will be presented in this session. This will include bumping with Pb-free materials. The relative merits of common bumping methods (stencil printing and electroplating) and their effects on reliability will be reviewed. In addition, with the drive towards lower cost, high yield flip-chip devices, a new method for wafer level encapsulation and bumping will also be presented.

Lead-Free Flip Chip Wafer Bumping using Stencil Printing Technology
Dionysios Manessis, R. Patzelt, A. Ostmann, R. Aschenbrenner, H. Reichl, J. Wiese, C. Modes, Technical University Berlin/Fraunhofer IZM Berlin

Benchmark of Printed and Plated Bumping Technologies - A (Die Level) Solder Bump Integrity Case Study
Jamin Ling, John Jackson, David Mackessy, Emman Alvarez, Byung-tai Do, Ted Tessier, Robert McCarthy, Zhiping Hu, Sheila M.Alvarez, Diane Sahakian, Il Kwon Shim, ST Assembly Testing Services

New Techniques for Wafer-Level Packaging of Flip-Chip Devices
Alan Grieve, M. Albert Capote, Howard Lenos, Arsenia Soriano, Aguila Technologies, Inc.

Solder Joint Reliability - Prediction and Experimentation
Chair: Thomas Green, North Hampton Community College
8 am - 9:25 am

Prediction of solder joint reliability is critical in electronic assemblies. Reliability of solder joints depends on many factors including packaging types and sizes, solder alloys, surface finishes, and more. This session focuses on the prediction and testing of board level solder joint reliability.

Solder Joint Reliability of Large Flip Chip Ball Grid Array Package
Leilei Zhang, Xilinx

Isothermal-Fatigue Tests of Lead-Free Solder Joints on Lead-Free Printed Circuit Board (PCB)
John H. Lau, S. W. Ricky Lee, Dongkai Shangguan, Agilent Technologies, Inc.

Constitutive Equations and Life Prediction Models for SnPb and SnAgCu Solder Joints
Ahmer Syed, Amkor Technology, Inc.

Microwaves and RF Design & Modeling
Chairs: Daniel Amey, DuPont Microcircuit Materials & John Gipprich, Northrop Grumman Corporation
8 am - 9:25 am

Design of Microwave and RF systems and subassemblies continues to be a challenge for a wide range of applications. This session will focus on design and modeling techniques as they relate to RF and Microwave packaging.

Factors Involved in Performance Optimisation of GHz Chip-Package Co-Design
Arun Chandrasekhar, Steven Brebels, Bart Vandevelde, Evelien Driessens, Jayaprakash Balachandran, Eric Beyne, Walter De Raedt, Bart Nauwelaers, Robert Mertens, Xavier Rottenberg, IMEC

Methodology for Efficient Modeling of BGA Packages at RF/Microwave Frequencies
N. Ivan Ndip, Grit Sommer, John Werner, Herbert Reichl, Fraunhofer Institute for Reliability and Microintegration (FhG-IZM)

Foundry Validation and Evaluation of a New LTCC Design Kit
Glenn Oliver, Michael Smith, DuPont MIcrocircuit Materials; Russ Bardlsey, Barry Industries

THA6 - Special Session - FREE TO ALL
GBC Business Spotlight Session - Outsourcing
Chair: David Saums, DS&A LLC
8:30 am - 11:20 am

This session will focus on issues and logistics associated with doing business with China, including an overview of import/export issues, regulatory and customs negotiations, supply chain management, factory relocation, business expansion, resource definitions and allocations, and product quality assurance.

Doing Business with China
Session Leader: Abe Wong, Managing Director, GMPSigma, LLC
Mr. Wong is also a Senior Consultant with California Manufacturing Technology Consulting (CMTC), a non-profit corporation organized by the U.S. Congress and funded by the U.S. Department of Commerce through the National Institute of Standards and Technology (NIST) and the State of California. Mr. Wong’s current position with CMTC specializes in helping business dealings between China and the US.

Global Sales and Marketing
Session Leader: Dick Jensen, Vice President and General Manager, Namics Technologies, Inc.
This presentation will discuss global sales and marketing strategy and implementation. The focus will be on creating a sales and marketing presence in locations outside of a businesses home market and making it a successful venture that increases sales and profitability. Various options for establishing a presence will be reviewed.

Emerging Technologies I
Chair: Ronald Jensen, Honeywell Solid State Electronics Center
8 am - 9:25 am

This session will present several novel fabrication techniques applied to wafer and die-level packaging, including stressed metal springs, nano laser marking, and piezo elements in a solid state cooler device.

Wafer Level Packaging using Stressed Metal Technology
David K. Fork, Christopher L. Chua, Koenraad Van Schuylenbergh, Eugene M. Chow, Thomas Hantschel, Lai Wong, Vicki Geluz, Palo Alto Research Center

Nano and Micro Laser Marking for Wafers and Chip Scale Packages
Bo Gu, GSI Lumonics, Inc.

Packaging Challenges in Building and Maintaining 5-10nm Gaps for Cool Chips Active Solid-State Coolers
Isaiah Cox, Avto Tavkhelidze, Jim Magdych, Cool Chips PLC

Advanced Processes for Optoelectronics Packaging
Chair: Thomas Green, North Hampton Community College
8 am - 9:25 am

This session looks at state of the art optoelectronics packaging techniques including laser welding used in external cavity tunable laser diode (ECTLD) with a fixed diffraction grating mirror and laser welding of fibers internal to the package and issues with post weld shift. Another advanced opto assembly technique presented is hermetically sealed transparent combo lids that transmit optical, infrared and ultraviolet spectrums.

An External Cavity Tunable Laser Diode Module with Fixed Diffraction Grating Mirror
Ho-Gyeong Yun, Yong-sung Eom, Jong-Hyun Lee, Byung-seok Choi, Oh-Kee Kwon, Kang-Ho Kim, Jong-Tae Moon, and Kwang-Ryong Oh, Electronics and Telecommunication Research Institute

Toward Targeted Laser Welding Optimization: Influence of Laser Pulse Shape on WIAD in Butterfly Laser Diode Module Packages
Yaomin Lin, Frank G. Shi, University of California - Irvine

VisiLid:Transparent Combo Lids
Heiner Lichtenberger, Michael Zasowski, Gery Lovitz, Joe Alfano, Williams Advanced Materials

Pb Free Flip Chip Bumping
Chair: Roupen Keusseyan, DuPont Microcircuit Materials
8 am - 9:25 am

Technical challenges in the adoption of lead-free flip chip and bumping approaches are discussed. New deposition and electroplating approaches, in addition to process and composition modifications are presented, paving the way to meet critical requirements for lead-free flip chip adoption.

Study of Needle-Like Crystal in Lead Free Bump
Akihiro Masuda, Masayoshi Kohinata, Mitsubishi Materials Corporation

Tin-Silver-Copper Electrodeposition of Pb-Free Wafer Bumps
Rozalia Beica, Danny Y.K. Lau, Rohm and Haas Electronic Materials

Reliability and Electrical Property of Pb-free and Eutectic SnPb Bumped Flip Chip
Seyoung Jeong, In-Young Lee, Sung-Ki Lee, Jongho Lee, Soonbum Kim, Namseog Kim, Sungmin Sim, Younghee Song, Seyong Oh, Samsung Electronics

Area Array Packages, Assembly and Reliability
Chairs: Reza Ghaffarian, Jet Propulsion Laboratory & Jamin Ling, ST Assembly and Testing Services (STATS - US)
8 am - 9:25 am

Come and learn all aspects of 2nd level area array reliability issues only in one session! Electronic miniaturization demands robust area array packages with higher I/Os and finer pitches imposing stringent requirement for substrates and printed circuit board materials as well as 2nd level interconnects. Key product reliability issues are addressed in this session by dissecting each element of the system. The first paper provides both FEA modeling approach substantiated by experimental test results to assist users in selection of substrate materials and design to optimize solder joint reliability. The second paper uses both modeling and experimental results to understand the effect of printed circuit board warpage on 2nd level reliability. The last paper covers other system issues such as PWB thickness and double-sided assembly on 2nd level reliability.

Substrate Structure and Material Impact on Solder Joint Reliability
Frank Liang, Rick Williams, Intel Corporation

Assembly and Reliability Assessment of Sea-of-Leads Compliant Interconnect Technology for WLP
Bing Dang, Georgia Institute of Technology

The Effect of PCB Thickness and Dual-sided Configuration on the Solder Joint Reliability of Area Array Packages
Rocky Shih, Sam Dai, Hewlett-Packard Company; Sue Teng, Mason Hu, Ken Hubbard, Cisco Systems Inc.

Integrated Passives – Ceramic
Chair: John Menaugh, DuPont Microcircuit Materials
8 am - 9:25 am

Continued growth in materials and methods for making ceramics embedded passives along with a high frequency embedded filter.

Passive Integration by Aerosol Deposition Method for Microwave Application
Yoshihiko Imanaka, Jun Akedo, Fujitsu Limited

New Materials and Method for Laser Trimmable NTC Thermistors
David J. Nabatian, KOARTAN Microelectronic Interconnect Materials; Gene A. Perschnick, EMC Technology Corporation

Multilayer Ceramic Band-Pass Filters for System-in-Package 5-GHz-WLAN Transceivers
Wojciech Debski, S. Walter, R. Matz, O. Dernovsek, S. Mecking, P. Mayr, P. Weger, Siemens AG

Emerging Technologies II
Chair: K. Jay Jayaraj, SiWave Inc.
10:20 am - 11:45 am

Papers in this session address reliability issues in probing low K devices, improved materials for first level interconnections and a robust laser bonding technique for system level interconnections.

Designing Low-k and Flip Chip Devices for Improved Reliability
Terence Collier, Nick Randall, CVInc.

Laser Ribbon Bonding: A Novel Interconnect Method
David Ruben, Medtronic Inc.; Ron Mundt, Mundt & Associates

Nanocrystalline Copper as Chip-to-Package High Density Interconnections
Shubhra Bansal, Rao R. Tummala, Georgia Institute of Technology; Ashok Saxena, University of Arkansas

Flip Chip (MEMS, Flat Panel, COG)
Chair: Tim Lenihan, RVSI, Semiconductor Equipment Group
10:20 am - 11:45 am

The Flip Chip (MEMS, Flat Panel, COG) Session will cover topics related to emerging Flip Chip (FC) applications in MEMS requiring low parasitic losses and improved high frequency characteristics in contact with the environment, FC on glass flat panel displays requiring low contact resistance and using low temperature solder, and a new UBM (Under Bump Metallurgy) for very fine pitch chip on glass (COG) using Au redistribution.

Flip Chip Joining of MEMS Components using SnPbAg and SnAg Solder Bumps
Kati Kokko, Sami Nurmi, Eero Ristolainen, Tampere University of Technology/Inst. of Electronics

Reactions and Shear Energies of 48Sn-52In Solder Bumps on Cu and Ni under Bump Metallurgies
Tae-Sung Oh, Jae-Hoon Choi, Young-Ho Kim, Hongik University

The Development of Redistribution Bump Process for Fine Pitch LDI Device
Chung Sun Lee, Yong-Hwan Kwon, Sa-Yoon Kang, Si-Jeong Kim, Ji-Hwan Hwang, Se-Yong Oh, Samsung Electronics

Flip Chip Underfill Stress
Chairs: Rajen Chanchani, Sandia National Laboratories & Andrew Strandjord, IC Interconnect
10:20 am - 11:45 am

Thermo-mechanical modeling and failure analysis caused by underfill stresses will be presented in this session.

Simulated Thermomechanical Loading Effects on Underfill/Passivation Interface Reliability for High Density Packaging
Bree Sharratt, Reinhold H. Dauskardt, Stanford University

Die Stress Characterization in Copper/Low-K Flip Chip Assemblies
Jeffrey C. Suhling, Kaysar Rahim, D. Scott Copeland, Richard C. Jaeger, R. Wayne Johnson, Pradeep Lall, Auburn University

Die/Underfill Interface Stress Analysis in Overmolded Flip Chip Packages
Yaomin Lin, Frank G. Shi, University of California - Irvine

Bend and Drop Testing
Chairs: Jamin Ling, ST Assembly and Testing Services (STATS - US) & Reza Ghaffarian, Jet Propulsion Laboratory
10:20 am - 11:45 am

Bend and drop are two important reliability test methods in electronic assemblies. The session focuses on the modeling of bend and drop tests in various applications and experimental validation of these models.

Analysis of Bend Test Technique for BGA Assemblies
Virendra Jadhav, Jennifer Latimer, David Alcoe, Endicott Interconnect Technologies Inc.

Cyclic Bending Strain Modeling and Its Application to the Life Prediction of SMD Solder Joints
Dongji Xie, Dongkai Shangguan, David Geiger, N. Todd Castello, Dan Roony, Flextronics USA

Reliability Modeling and Analysis of CSP Packages for Board and Product System Level Drop Tests
Liping Zhu, Walt Marcinkiewicz, Sony Ericsson Mobile Communication Inc.

Brittle Facture of Pb-free Solder Joint in Ni/Au finished FBGA MCP Mounted on OSP Board Subjected to Bending Impact Load
Ho Jeong Moon, Wang Ju Lee, Duk Yong Lee, Seung Woo Kim, Boseong Kim, Tae Gyeong Chung, Hee Kook Choi, Samung Electronics

Integrated Passives - Organic Substrate
Chair: R. Wayne Johnson, Auburn University
10:20 am - 11:45 am

Size reduction and reliability improvement in organic embedded passives.

Ultra-thin Substrates for use as Embedded Capacitors in PCBs and Organic Chip Packages
John Andresakis, Takuya Yamamoto, Pranabes Pramanik, Oak-Mitsui Technologies LLC; Nick Biunno, Sanmina-SCI Corporation

Yield and Reliability of Tantalum Pentoxide Integrable Decoupling Capacitors
Deepa Mannath, Anurag Yadav, Leonard W. Schaper, Richard K. Ulrich, Viswas Reddy Pola, University of Arkansas

Design and Fabrication of an Automotive Engine Controller Using Embedded Passive Technology for PWB
Jiming Zhou, John D. Myers, Delphi


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