|
Advance
Technical Program or browse the program:
THA1 The rapid pace of innovation in electronics manufacturing technology makes for a constant demand for newer applications. This session presents two applications of ink-jet printing in electronics fabrication and a new diagnostic method in flip chip assemblies. Low-Cost Solar Cell Fabrication by Drop-On-Demand Ink-jet Printing Digitally Printing Electronics with Piezo Ink Jet New Methods of the Nondestructive Quality Control and Reliability
Forecasting for Modern Flip Chip Assemblies and Electronic Devices THA2 This session addresses some important issues which are critical to the low cost packaging of ultra small form factor 10GB integrated transmitters, optical interconnection modules and high power LEDs. Ultra Small Form Factor 10GB Low Cost Integrated Transmitter Challenges of Pb-free Packaging of High-Power LEDs Alignment Arrangement for Low-Cost Embedded Optical Interconnection
Module THA3 Techniques for fine-pitch, flip-chip wafer level bumping will be presented in this session. This will include bumping with Pb-free materials. The relative merits of common bumping methods (stencil printing and electroplating) and their effects on reliability will be reviewed. In addition, with the drive towards lower cost, high yield flip-chip devices, a new method for wafer level encapsulation and bumping will also be presented. Lead-Free Flip Chip Wafer Bumping using Stencil Printing Technology Benchmark of Printed and Plated Bumping Technologies - A (Die
Level) Solder Bump Integrity Case Study New Techniques for Wafer-Level Packaging of Flip-Chip Devices THA4 Prediction of solder joint reliability is critical in electronic assemblies. Reliability of solder joints depends on many factors including packaging types and sizes, solder alloys, surface finishes, and more. This session focuses on the prediction and testing of board level solder joint reliability. Solder Joint Reliability of Large Flip Chip Ball Grid Array Package Isothermal-Fatigue Tests of Lead-Free Solder Joints on Lead-Free
Printed Circuit Board (PCB) Constitutive Equations and Life Prediction Models for SnPb and
SnAgCu Solder Joints THA5 Design of Microwave and RF systems and subassemblies continues to be a challenge for a wide range of applications. This session will focus on design and modeling techniques as they relate to RF and Microwave packaging. Factors Involved in Performance Optimisation of GHz Chip-Package
Co-Design Methodology for Efficient Modeling of BGA Packages at RF/Microwave
Frequencies Foundry Validation and Evaluation of a New LTCC Design Kit THA6 - Special Session - FREE TO ALL This session will focus on issues and logistics associated with doing business with China, including an overview of import/export issues, regulatory and customs negotiations, supply chain management, factory relocation, business expansion, resource definitions and allocations, and product quality assurance. Doing Business with China Global Sales and Marketing THA7 This session will present several novel fabrication techniques applied to wafer and die-level packaging, including stressed metal springs, nano laser marking, and piezo elements in a solid state cooler device. Wafer Level Packaging using Stressed Metal Technology Nano and Micro Laser Marking for Wafers and Chip Scale Packages Packaging Challenges in Building and Maintaining 5-10nm Gaps for
Cool Chips Active Solid-State Coolers THA8 This session looks at state of the art optoelectronics packaging techniques including laser welding used in external cavity tunable laser diode (ECTLD) with a fixed diffraction grating mirror and laser welding of fibers internal to the package and issues with post weld shift. Another advanced opto assembly technique presented is hermetically sealed transparent combo lids that transmit optical, infrared and ultraviolet spectrums. An External Cavity Tunable Laser Diode Module with Fixed Diffraction
Grating Mirror Toward Targeted Laser Welding Optimization: Influence of Laser
Pulse Shape on WIAD in Butterfly Laser Diode Module Packages VisiLid:Transparent Combo Lids THA9 Technical challenges in the adoption of lead-free flip chip and bumping approaches are discussed. New deposition and electroplating approaches, in addition to process and composition modifications are presented, paving the way to meet critical requirements for lead-free flip chip adoption. Study of Needle-Like Crystal in Lead Free Bump Tin-Silver-Copper Electrodeposition of Pb-Free Wafer Bumps Reliability and Electrical Property of Pb-free and Eutectic SnPb
Bumped Flip Chip THA10 Come and learn all aspects of 2nd level area array reliability issues only in one session! Electronic miniaturization demands robust area array packages with higher I/Os and finer pitches imposing stringent requirement for substrates and printed circuit board materials as well as 2nd level interconnects. Key product reliability issues are addressed in this session by dissecting each element of the system. The first paper provides both FEA modeling approach substantiated by experimental test results to assist users in selection of substrate materials and design to optimize solder joint reliability. The second paper uses both modeling and experimental results to understand the effect of printed circuit board warpage on 2nd level reliability. The last paper covers other system issues such as PWB thickness and double-sided assembly on 2nd level reliability. Substrate Structure and Material Impact on Solder Joint Reliability Assembly and Reliability Assessment of Sea-of-Leads Compliant
Interconnect Technology for WLP The Effect of PCB Thickness and Dual-sided Configuration on the
Solder Joint Reliability of Area Array Packages THA11 Continued growth in materials and methods for making ceramics embedded passives along with a high frequency embedded filter. Passive Integration by Aerosol Deposition Method for Microwave
Application New Materials and Method for Laser Trimmable NTC Thermistors Multilayer Ceramic Band-Pass Filters for System-in-Package 5-GHz-WLAN
Transceivers THA12 Papers in this session address reliability issues in probing low K devices, improved materials for first level interconnections and a robust laser bonding technique for system level interconnections. Designing Low-k and Flip Chip Devices for Improved Reliability Laser Ribbon Bonding: A Novel Interconnect Method Nanocrystalline Copper as Chip-to-Package High Density Interconnections THA13 The Flip Chip (MEMS, Flat Panel, COG) Session will cover topics related to emerging Flip Chip (FC) applications in MEMS requiring low parasitic losses and improved high frequency characteristics in contact with the environment, FC on glass flat panel displays requiring low contact resistance and using low temperature solder, and a new UBM (Under Bump Metallurgy) for very fine pitch chip on glass (COG) using Au redistribution. Flip Chip Joining of MEMS Components using SnPbAg and SnAg Solder
Bumps Reactions and Shear Energies of 48Sn-52In Solder Bumps on Cu and
Ni under Bump Metallurgies The Development of Redistribution Bump Process for Fine Pitch
LDI Device THA14 Thermo-mechanical modeling and failure analysis caused by underfill stresses will be presented in this session. Simulated Thermomechanical Loading Effects on Underfill/Passivation
Interface Reliability for High Density Packaging Die Stress Characterization in Copper/Low-K Flip Chip Assemblies Die/Underfill Interface Stress Analysis in Overmolded Flip Chip
Packages THA15 Bend and drop are two important reliability test methods in electronic assemblies. The session focuses on the modeling of bend and drop tests in various applications and experimental validation of these models. Analysis of Bend Test Technique for BGA Assemblies Cyclic Bending Strain Modeling and Its Application to the Life
Prediction of SMD Solder Joints Reliability Modeling and Analysis of CSP Packages for Board and
Product System Level Drop Tests Brittle Facture of Pb-free Solder Joint in Ni/Au finished FBGA
MCP Mounted on OSP Board Subjected to Bending Impact Load THA16 Size reduction and reliability improvement in organic embedded passives. Ultra-thin Substrates for use as Embedded Capacitors in PCBs and
Organic Chip Packages Yield and Reliability of Tantalum Pentoxide Integrable Decoupling
Capacitors Design and Fabrication of an Automotive Engine Controller Using
Embedded Passive Technology for PWB
| ||||||||
IMAPS
- International Microelectronics And Packaging Society
611 2nd Street, NE -- Washington, DC 20002 imaps @ imaps.org | 202.548.4001 |