Advance Technical Program
Tuesday, November 16, 2004



or browse the program:

By Day: By Session:
Tuesday TA1 | TA2 | TA3 | TA4 | TA5 | TA6
TP1 | TP2 | TP3 | TP4 | TP5 | TP6 | TP7 | TP8 | TP9 | TP10
Wednesday WA1 | WA2 | WA3 | WA4 | WA5 | WA6 | WA7 | WA8 | WA9 | WA10 | WA11
WP1 | WP2 | WP3 | WP4 | WP5 | WP6 | WP7 | WP8 | WP9 | WP10 | WP11 | WP12
Thursday THA1 | THA2 | THA3 | THA4 | THA5 | THA6 | THA7 | THA8 | THA9 | THA10 | THA11 | THA12 | THA13 | THA14 | THA15 | THA16

TA1
Wafer Level Packaging
Chair: Andrew Strandjord, IC Interconnect
8 am - 9:25 am

Cost reduction and performance improvement in wafer level packages.  The two most important issues in packaging.

Redistribution on Wafer: An Alternative, Cost-Efficient Approach
Herbert De Pauw, Nadine Carchon, Johan De Baets, André Van Calster, TFCG/IMEC

Innovative, Scalable and Reworkable Metal-Polymer Composite Nano Interconnects for High Performance and Ultra Fine-Pitch Wafer Level Packages
Ankur O. Aggarwal, P. Markondeya Raj, Rao R. Tummala, Georgia Institute of Technology

Study of the Integration of a New Elastomeric Material in a Silicone under the Bump Configuration
Mathieu Vanden-Bulcke, IMEC


TA2
Sensors-Thick and Thin Film
Chair: Janet Lumpp, University of Kentucky
8 am - 9:25 am
 

Homeland security and process monitoring needs continue to make sensing an important area. This session includes new approches for measuring flow, temperature and gas concentration.

Thick Film Flow Sensors for Liquids Based on the Calorimetric Principle
Walter Smetana, Roland Reicher, Heinz Homolka, Georg Dombazian, Vienna University of Technology

ZnO/Fe2O3 Thick Film Gas Sensors to Detect Butanol, Pentanol and Hexanol at Room Temperature
Khalil Arshak, I. Gaidan, University of Limerick

The Experimental Characterization of Thin Film Thermopiles
Muhammad Imran, A. Bhattacharyya, University of Arkansas at Little Rock


TA3
Developments in Wire Bonding
Chair: Lee Levine, Kulicke & Soffa Ind. Inc.
8 am - 9:25 am

New wire bonding applications continue to evolve. Fine pitch, stacked die and automotive applications will be described in this session.

Joint Strength Improvement of Au-Al IMC for Wire Bonded Package
Joe Hung, Y. P. Wang, Holman Chen, C.S. Hsiao, Siliconware Precision Industries Co., Ltd.

Analysis of the Characteristic of Bouncing Effect During the Wire Bonding Process
DongKil Shin, HeeKook Choi, TaeGyeong Chung, SeYong Oh, Samsung Electronics Co.

An Evaluation of Al Wire Bondable Surfaces for Automotive Lead Frame Applications
Philip W. Lees, Technical Materials, Inc.


TA4
Conductive Polymers & Adhesives
Chair: Herbert Neuhaus, Scimaxx Solutions
8 am - 9:25 am

Conductive polymers and adhesives are critical to electronics assembly. This session looks at flexible, low stress, and solder-like conductive adhesives.

Anisotropically Conductive Adhesive Film (ACF) System Durable to Bond Flexing
Ranjith Divigalpitiya, Richard Sabatier, Christophe Arnold, Glen Connell, 3M Canada Company

Low Stress, High Strength Isotropic Conductive Film Adhesive for Large Area Bonding of Thermally Mismatched Substrates
Andrew Collins, Chih-Min Cheng, Emerson & Cuming

Highly Conductive Die Attach Adhesive for Power Devices
Alan Grieve, M. Albert Capote, Arsenia Soriano, Aguila Technologies, Inc.


TA5
High Density Substrates
Chair: Andrew Strandjord, IC Interconnect
8 am - 9:25 am

Design issues around high density substrates, particularly in the area of micro-vias for both LTCC and organics substrates.

Microvias: Design, Performance, Reliability and Future Trends
Arthur Prejs, Mike Anderson, Anadigics, Inc.

Development and Evaluation of Carbon-Silicon Carbide Substrates for High-Density Packaging
Nitesh Kumbhat, Raghuram Pucha, P. Markondeya Raj, Venky Sundaram, Swapan Bhattacharya, Steve Atmur, Susan Hayes, Suresh Sitaraman, Rao Tummala, Georgia Institute of Technology

Micro Vias in LTCC Substrates
Fred Barlow, E. Elvey, G. Wang, A. Elshabini, University of Arkansas


TA6 - Special Session - FREE TO ALL
GBC Business Spotlight Session
Chair: Paul Galletta, Teledyne Electronic Technologies
8:30 am - 11 am

Diminishing Manufacturing Resources Workshop
Session Leader - Alan Hirschberg, Site DMS Program Manager, Northrop-Grumman Space Technology

                This one hour session will define and discuss issues and concerns regarding diminishing manufacturing resources as a result of outsourcing and COTS. The discussion leader will lead the audience through an interactive discussion as to potential paths towards long term stability and security in the supply chain for concerned companies.

ITAR
Session Leader - Heide Wallace, Director of Contracts, Teledyne Electronic Technologies

                This one-hour session will explain what information exporters need to comply with under the U.S. Export ITAR control requirements. The focus will fall on the process and requirements necessary to obtain an export license from the Department of State. Suspect situations or “Red Flags” in export to foreign countries will be identified and discussed.


TP1
Advanced Power Device Packaging
Chair: Douglas C. Hopkins, State University of New York at Buffalo
2 pm - 3:25 pm
 

Wafer-level packaging to high-temperature packages - Come listen to the latest advanced power packaging approaches.           

Environmental Stress Testing of Power Transistors Encapsulated in Plastic Packages
Alexander Teverovsky, QS Group, Inc.

Design and Performance Characteristics of a New Generation Wafer-level Package for Advanced Power MOSFET Applications
Mohammed Kasem, Q. Chen, E. Tjhia, D. Pattanayak, Vishay Siliconix   

High Temperature Packaging of Silicon Carbide (SiC) Power Devices for Multichip Power Module (MCPM) Applications
Habib A. Mustain, Alexander B. Lostetter, William D. Brown, University of Arkansas


TP2
MEMS Devices
Chair: David Galipeau, South Dakota State University
2 pm - 3:25 pm

This session covers new developments in micromachining including laser drilling, microcantilevers, and MEMS antennas.

Investigations of Laser Percussion Drilling of Small Holes on Thin Metal Sheets for MEMS Packaging Applications
Wei Han, Ryszard J. Pryputniewicz, Worcester Polytechnic Institute

Finite Element Modeling of Shape Memory Alloy-Layered Micro-Cantilevers
Paulomi Majumder, Abhijit Bhattacharyya, University of Arkansas at Little Rock

Micromachined Antennas using HRS (High Resistively Si) and LCP (Liquid Crystal Polymer) Technology for WLNA Applications
Sunghae Jung, Junghwan Hwang, Sungweon Kang, Electronics and Telecommunications Research Institute


TP3
Copper/Low K Wire Bonding
Chair: Lee Levine, Kulicke & Soffa Ind. Inc.
2 pm - 2:55 pm

Copper/Low K wire bonding is critical to the development of advanced devices at 90nm and beyond. This session looks at the critical issues of this process.

Simulation of Wirebond Stresses Under Bondpads in Copper/Low-k Technology
Kevin J. Hess, Susan H. Downey, Tom Lee, Lei L. Mercado, James W. Miller, Motorola Corp.

Pull Test Simulation and Optimization for Wires Bonded on Cu/Low-k Wafers
Chang-Lin Yeh, Chin-Li Kao, Yi-Shao Lai, Advanced Semiconductor Engineering, Inc.


TP4
Lead Free Solder Development
Chair: Roupen Keusseyan, DuPont Microcircuit Materials
2 pm - 3:25 pm

The timeline for lead-free conversion in Europe and elsewhere is fast approaching.  Next generation lead-free compositions and required modifications are presented for practical manufacturing capabilities to replace traditional solders.   The new approaches offer improved performance in terms of creep, bend and flex joint properties.

New Sn-Zn-Bi-Ag Solder and its Bonding Mechanism
Takuo Funaya, Junya Sakurai, Hiroshi Kubota, Motoji Suzuki, Koji Matsui, NEC Corporation

Reliability of Chip Size Package Solder Joints with Lower Melting Lead-free Solder
Atsushi Yamaguchi, Yuhei Yamashita, Akio Furusawa, Kazuto Nishida, Takashi Hojo, Yosuke Sogo, Ayako Miwa, Akio Hirose, Kojiro F. Kobayashi, Matsushita Electric Industrial Co., Ltd.

Investigation of Creep and Stress Relaxation by Solder Joints
Ivan Szendiuch, Milos Dusek, NPL Teddington, Michal Zelinka, Brno University of Technology


TP5
Development of SiP Technologies in Japan (Japanese Translated Session)
Chairs: Fumio Miyashiro, PI R&D Co., Ltd; Andy London, Heraeus Incorporated – CMD; Michael Stein, Electro-Science Labs, Inc.
2 pm - 3:25 pm

Development of System in a Package (SIP) has been in fashion in Japan.  Related technologies including embedding (building in) electronic parts, 3D Chip stacking, wafer and SIP level MEMS packaging are covered.

Development of Thin Capacitor Embedded Package
Kiyoshi Ohi, Shinko Electric Industry.

Concept & Development of “All-in-one SiP” in Japan
Takao Fujitsu, SiP Consortium

Key Technologies of “All-in-one SiP”
Hitoshi Kawaguchi, SiP Consortium


TP6
Thermal Interface Materials
Chair: Frank Wall, Lumileds Lighting LLC
4:20 pm - 5:40 pm

Methods and techniques for reducing the thermal path with both solders and TIM.

A Study of Thermal Interface Material (TIM) Technology Performance Specification (TPS) Validation with FCBGA Package Solution
Shaw Fong Wong, Zulkifly Abdullah, K.N. Seetharamu, Torresola Javier, Bharatham Logendran, Chee Koang Chen, Intel Technology

New Verification of TIM1 Performance and Examination of Interfacial Voiding in Room-Temperature Soldering
David Van Heerden, T. Rude, J. Newson, O.M. Knio, David W. Gailus, Reactive NanoTechnologies

Performance, Reliability, and Approaches using a Low Melt Alloy as a Thermal Interface Material
Chris Macris, Tom Sanderson, Chris Leyerle, Enerdyne Solutions


TP7
MEMS Materials
Chair: David Galipeau, South Dakota State University
4:20 pm - 5:40 pm

New developments in MEMS materials including thick film piezoelectrics, photo-epoxies used for microcavities, and fatigue analysis are reviewed in this session.

A Damage Mechanics Based Constitutive Model for Low Cycle Fatigue Analysis of MEMS systems
Juan Gomez, Cemal Basaran, State University of New York at Buffalo

Preparation of Piezoelectric Thick Films on different Substrates
Marija Kosec, Janez Holc, Marko Hrovat, Darko Belavic, Barbara Malic, Jozef Stefan Institute

A Wafer-Level-Process using Photo-Epoxy to create Air-Cavities for Bulk-Acoustic-Wave RF-Filters
R. Aigner, Martin Franosch, Klaus-Guenter Oppermann, Winfried Nessler, Andreas Meckes, Infineon Technologies


TP8
Cu Wire-Wire Bonding
Chair: George Harman, NIST
4:20 pm - 5:40 pm
 

Copper ball bonding has become a high-volume process. It’s now a major interconnection method in heavy wire, power devices. This session will cover issues in copper wire, wire bonding.

An Update on High Volume Copper Ball Bonding
Lee Levine, Michael Deley, Kulicke & Soffa Ind Inc.

Advanced Copper Bonding Wires for Chip Packaging
Z. Guo, L. Monterulo, K. Huth, Semiconductor Packaging Materials, Inc.

Heavy Al Ribbon Interconnect: An Alternate Solution for Hybrid Power Packaging
Bryan Y. Y. Ong, Shirley M.C. Chuah, STATS ChipPAC Ltd.; Christoph Luechinger, Garrett Wong, Orthodyne Electronics Corporation


TP9
Pb Free Assembly I
Chair: Ken Kuang, Kyocera America, Inc.
4:20 pm - 5:40 pm

Due to health and environmental concerns, lead- free solder is becoming more and more popular and being adopted surely and slowly. However, there are still many questions about its reliability and process quality not fully answered. This session covers the basics of lead-free solder, examines the impacts of component and pad metallizations, and solders compositions on solder joint reliability. The process challenges and yield associated with assembling 0201 components using lead-free solders are also discussed.

Lead-Free Solder Joint Reliability - State of the Art and Perspectives
Jianbiao Pan, California Polytechnic State University; Jyhwen Wang, Texas A&M University; David M. Shaddock, GE Global Research Center

Effect of Stencil and PCB Parameters on Lead Free 0201 Assembly Process Defects
S. Manian Ramkumar, Rahul Newasekar, Reza Ghaffarian, Rochester Institute of Technology

Optimizing SnAgCu Alloy Composition for Tombstoning and Voiding Performance
Ning-Cheng Lee, Benlih Huang, Indium Corporation of America


TP10
Development of SiP Technologies in Japan (Japanese Translated Session)
Chairs: Fumio Miyashiro, PI R&D Co., Ltd; Andy London, Heraeus Incorporated – CMD; Michael Stein, Electro-Science Labs, Inc.
4:20 pm - 5:40 pm
 

Development of System in a Package (SIP) has been in fashion in Japan.  Related technologies including embedding (building in) electronic parts, 3D Chip stacking, wafer and SIP level MEMS packaging are covered.

Development of 3D Chip Stacking Technology by Si Through-via
Kenji Takahashi, ASET

Embedded Wafer Level Package for SiP
Takeshi Wakabayashi, Casio

MEMS Packaging Technology for SiP
Munehisa Takeda, Mitsubishi Electric  

 

 

 

 

 

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