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Advance
Technical Program
TA1 Cost reduction and performance improvement in wafer level packages. The two most important issues in packaging. Redistribution
on Wafer: An Alternative, Cost-Efficient Approach Innovative,
Scalable and Reworkable Metal-Polymer Composite Nano Interconnects
for High Performance and Ultra Fine-Pitch Wafer Level Packages Study
of the Integration of a New Elastomeric Material in a Silicone
under the Bump Configuration TA2 Sensors-Thick and Thin Film Chair: Janet Lumpp, University of Kentucky 8 am - 9:25 am Homeland security and process monitoring needs continue to make sensing an important area. This session includes new approches for measuring flow, temperature and gas concentration. Thick
Film Flow Sensors for Liquids Based on the Calorimetric
Principle ZnO/Fe2O3
Thick Film Gas Sensors to Detect Butanol, Pentanol and
Hexanol at Room Temperature The
Experimental Characterization of Thin Film Thermopiles TA3 Developments in Wire Bonding Chair: Lee Levine, Kulicke & Soffa Ind. Inc. 8 am - 9:25 am New wire bonding applications continue to evolve. Fine pitch, stacked die and automotive applications will be described in this session. Joint
Strength Improvement of Au-Al IMC for Wire Bonded Package Analysis
of the Characteristic of Bouncing Effect During the Wire
Bonding Process An
Evaluation of Al Wire Bondable Surfaces for Automotive
Lead Frame Applications TA4 Conductive Polymers & Adhesives Chair: Herbert Neuhaus, Scimaxx Solutions 8 am - 9:25 am Conductive polymers and adhesives are critical to electronics assembly. This session looks at flexible, low stress, and solder-like conductive adhesives. Anisotropically
Conductive Adhesive Film (ACF) System Durable to Bond
Flexing Low
Stress, High Strength Isotropic Conductive Film Adhesive
for Large Area Bonding of Thermally Mismatched Substrates Highly
Conductive Die Attach Adhesive for Power Devices TA5 High Density Substrates Chair: Andrew Strandjord, IC Interconnect 8 am - 9:25 am Design issues around high density substrates, particularly in the area of micro-vias for both LTCC and organics substrates. Microvias:
Design, Performance, Reliability and Future Trends Development
and Evaluation of Carbon-Silicon Carbide Substrates for
High-Density Packaging Micro
Vias in LTCC Substrates TA6 - Special Session - FREE TO ALL GBC Business Spotlight Session Chair: Paul Galletta, Teledyne Electronic Technologies 8:30 am - 11 am Diminishing
Manufacturing Resources Workshop This one hour session will define and discuss issues and concerns regarding diminishing manufacturing resources as a result of outsourcing and COTS. The discussion leader will lead the audience through an interactive discussion as to potential paths towards long term stability and security in the supply chain for concerned companies. ITAR This one-hour session will explain what information exporters need to comply with under the U.S. Export ITAR control requirements. The focus will fall on the process and requirements necessary to obtain an export license from the Department of State. Suspect situations or “Red Flags” in export to foreign countries will be identified and discussed. TP1 Advanced Power Device Packaging Chair: Douglas C. Hopkins, State University of New York at Buffalo 2 pm - 3:25 pm Wafer-level packaging to high-temperature packages - Come listen to the latest advanced power packaging approaches. Environmental
Stress Testing of Power Transistors Encapsulated in Plastic
Packages Design
and Performance Characteristics of a New Generation Wafer-level
Package for Advanced Power MOSFET Applications High
Temperature Packaging of Silicon Carbide (SiC) Power
Devices for Multichip Power Module (MCPM) Applications TP2 This session covers new developments in micromachining including laser drilling, microcantilevers, and MEMS antennas. Investigations
of Laser Percussion Drilling of Small Holes on Thin Metal
Sheets for MEMS Packaging Applications Finite
Element Modeling of Shape Memory Alloy-Layered Micro-Cantilevers Micromachined
Antennas using HRS (High Resistively Si) and LCP (Liquid
Crystal Polymer) Technology for WLNA Applications TP3 Copper/Low K Wire Bonding Chair: Lee Levine, Kulicke & Soffa Ind. Inc. 2 pm - 2:55 pm Copper/Low K wire bonding is critical to the development of advanced devices at 90nm and beyond. This session looks at the critical issues of this process. Simulation
of Wirebond Stresses Under Bondpads in Copper/Low-k Technology Pull
Test Simulation and Optimization for Wires Bonded on
Cu/Low-k Wafers TP4 Lead Free Solder Development Chair: Roupen Keusseyan, DuPont Microcircuit Materials 2 pm - 3:25 pm The timeline for lead-free conversion in Europe and elsewhere is fast approaching. Next generation lead-free compositions and required modifications are presented for practical manufacturing capabilities to replace traditional solders. The new approaches offer improved performance in terms of creep, bend and flex joint properties. New
Sn-Zn-Bi-Ag Solder and its Bonding Mechanism Reliability
of Chip Size Package Solder Joints with Lower Melting
Lead-free Solder Investigation
of Creep and Stress Relaxation by Solder Joints TP5 Development of SiP Technologies in Japan (Japanese Translated Session) Chairs: Fumio Miyashiro, PI R&D Co., Ltd; Andy London, Heraeus Incorporated – CMD; Michael Stein, Electro-Science Labs, Inc. 2 pm - 3:25 pm Development of System in a Package (SIP) has been in fashion in Japan. Related technologies including embedding (building in) electronic parts, 3D Chip stacking, wafer and SIP level MEMS packaging are covered. Development
of Thin Capacitor Embedded Package Concept & Development
of “All-in-one SiP” in Japan Key
Technologies of “All-in-one SiP” TP6 Thermal Interface Materials Chair: Frank Wall, Lumileds Lighting LLC 4:20 pm - 5:40 pm Methods and techniques for reducing the thermal path with both solders and TIM. A
Study of Thermal Interface Material (TIM) Technology
Performance Specification (TPS) Validation with FCBGA
Package Solution New
Verification of TIM1 Performance and Examination of Interfacial
Voiding in Room-Temperature Soldering Performance,
Reliability, and Approaches using a Low Melt Alloy as
a Thermal Interface Material TP7 MEMS Materials Chair: David Galipeau, South Dakota State University 4:20 pm - 5:40 pm New developments in MEMS materials including thick film piezoelectrics, photo-epoxies used for microcavities, and fatigue analysis are reviewed in this session. A
Damage Mechanics Based Constitutive Model for Low Cycle
Fatigue Analysis of MEMS systems Preparation
of Piezoelectric Thick Films on different Substrates A
Wafer-Level-Process using Photo-Epoxy to create Air-Cavities
for Bulk-Acoustic-Wave RF-Filters TP8 Cu Wire-Wire Bonding Chair: George Harman, NIST 4:20 pm - 5:40 pm Copper ball bonding has become a high-volume process. It’s now a major interconnection method in heavy wire, power devices. This session will cover issues in copper wire, wire bonding. An
Update on High Volume Copper Ball Bonding Advanced
Copper Bonding Wires for Chip Packaging Heavy
Al Ribbon Interconnect: An Alternate Solution for Hybrid Power
Packaging TP9 Pb Free Assembly I Chair: Ken Kuang, Kyocera America, Inc. 4:20 pm - 5:40 pm Due to health and environmental concerns, lead- free solder is becoming more and more popular and being adopted surely and slowly. However, there are still many questions about its reliability and process quality not fully answered. This session covers the basics of lead-free solder, examines the impacts of component and pad metallizations, and solders compositions on solder joint reliability. The process challenges and yield associated with assembling 0201 components using lead-free solders are also discussed. Lead-Free
Solder Joint Reliability - State of the Art and Perspectives Effect
of Stencil and PCB Parameters on Lead Free 0201 Assembly Process
Defects Optimizing
SnAgCu Alloy Composition for Tombstoning and Voiding Performance TP10 Development of SiP Technologies in Japan (Japanese Translated Session) Chairs: Fumio Miyashiro, PI R&D Co., Ltd; Andy London, Heraeus Incorporated – CMD; Michael Stein, Electro-Science Labs, Inc. 4:20 pm - 5:40 pm Development of System in a Package (SIP) has been in fashion in Japan. Related technologies including embedding (building in) electronic parts, 3D Chip stacking, wafer and SIP level MEMS packaging are covered. Development
of 3D Chip Stacking Technology by Si Through-via Embedded
Wafer Level Package for SiP MEMS
Packaging Technology for SiP
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IMAPS
- International Microelectronics And Packaging Society
611 2nd Street, NE -- Washington, DC 20002 imaps @ imaps.org | 202.548.4001 |