Professional Development Courses (PDCs)
Monday, November 15, 2004

All PDCs run 9am - 5pm unless otherwise noted.

PDC Info | Sunday PDCs

PDC Reception
Sunday, November 14
5 pm - 6 pm
PDC Instructors and Attendees only

Wire Bonding in Microelectronics
Course Leader:
George G. Harman, National Institute of Standards and Technology

Course Description:
Wire bond manufacturing defects range typically from about 1000 to 100 ppm, with exceptions to >10,000 and <50 ppm. In order to achieve the lower numbers in production, one must understand all of the conditions that affect both bond yield and reliability (since they are interrelated). This course will discuss many large- and small-wire bonding problems, as well as subjects of specific interest to hybrid/MCM device bonding. In addition, a number of advanced topics, such as high yield, fine pitch, and flex bonding will be covered. New developments (e.g., high frequency ultrasonic bonding) are included along with a major discussion of wire bonding to multichip modules and other soft substrates. Wire bond testing and metallurgy (covering both aluminum and gold bonds); intermetallic compounds; cleaning for yield and reliability; failures resulting from electroplating; mechanical problems in wire bonding; new bond technologies and developments; how ultrasonic bonds are formed, and the metallurgy of gold and aluminum wire. It concludes with methods of implementing TAB and Flip Chip by using wire bonding techniques.

Who should attend?
Engineers in R&D, QA, QC, manufacturing, process development, and advanced technicians. It is assumed that participants have some familiarity with wire bonding and general device assembly technologies.

Special Course Material:
All attendees will receive a complimentary copy of Wire Bonding in Microelectronics, by George Harman, McGraw Hill, NY, 1997 (List price $65).

Mr. Harman is a Fellow of the National Institute of Standards and Technology (NIST), Department of Commerce. He received a BS in Physics from Virginia Polytechnic Institute & State University and a MS in Physics from the University of Maryland. Mr. Harman has published 50+ papers, two books on wire bonding, and holds four U.S. Patents. He was the 1995 President of ISHM and is a Fellow of IMAPS and the IEEE. He has received numerous awards for his work from IMAPS, IEEE, DVS and others. He has presented numerous talks, and has taught courses for the University of Arizona and IMAPS for over 15 years, as well as the IEEE, to name a few. He has presented many papers and given courses in the USA, Europe, and Asia.

Advanced Thermal Management Materials
Course Leader:
Carl Zweben, Advanced Thermal Management Materials Consultant

Course Description:
Material selection impacts thermal management, performance, alignment, reliability, cost, weight and manufacturing yield. Increasingly, traditional packaging materials are failing to meet the requirements of new microelectronic, optoelectronic and MEMS/MOEMS designs. For example, traditional low-coefficient-of-thermal-expansion (CTE) metallic materials have thermal conductivities that are no better than that of aluminum. In response to this need, numerous advanced composites and monolithic materials have been, and are continuing to be developed. There are now at least nine low-CTE materials with thermal conductivities in the range of 400 to 1700 W/m-K. A new thermal interface material has a reported thermal conductivity of 750 W/m-K. Several advanced materials have been used in high-volume commercial and military applications for several years. One class of new materials has high electrical resistivities, reducing electromagnetic emissions.

Advanced materials, such as Al/SiC metal matrix composites (first used in packaging by the course leader) and carbon-fiber-reinforced polymer matrix composites, are now being used in a growing number of high volume commercial and aerospace production applications at the rate of millions of piece parts annually. Components include heat spreaders, microprocessor lids, air-cooled and liquid-cooled cold plates, microwave modules, power semiconductor modules and optoelectronic packages.

Products using these materials include servers, cellular telephone handsets and base stations, laptop computers, telecommunication equipment, hybrid and electric vehicles, trains, wind turbine generators, data storage drives and aerospace/defense electronic systems.

This course covers traditional packaging materials and the large and increasing number of advanced materials, including: silicon carbide particle-reinforced aluminum (Al/SiC) and copper; carbon fiber-reinforced polymer matrix composites; aluminum and copper reinforced with discontinuous and continuous carbon fibers; diamond particle-reinforced aluminum, copper, cobalt and silicon carbide; beryllia particle-reinforced beryllium; graphite-flake-reinforced aluminum; silicon-aluminum; silver/“Invar;” carbon/carbon composites; “natural graphite;” thermal-, annealed- and highly oriented pyrolitic graphite; “ThermalGraph;” and others. This course provides an in-depth discussion of the materials, their properties, the processes by which they are made, applications and future directions.

Who should attend?
Engineers, scientists and managers involved in microelectronic, optoelectronic and MEMS/MOEMS packaging design, production and R&D; packaging material suppliers.

Dr. Zweben, an independent consultant, has directed development and application of advanced packaging materials for over 30 years. For many years, he was Advanced Technology Manager and Division Fellow at GE Astro Space, later acquired by Lockheed Martin, where he directed the Composites Center of Excellence. Other affiliations have included Du Pont, Jet Propulsion Laboratory and the Georgia Institute of Technology NSF Packaging Research Center. Dr. Zweben was the first, and one of only two winners of both the GE One-in-a-Thousand and Engineer-of-the-Year awards. He is a Fellow of ASME, ASM and SAMPE, an Associate Fellow of AIAA, and has been a Distinguished Lecturer for AIAA and ASME. He has published and lectured widely on advanced thermal management and packaging materials.

Technology of Screen Printing
Course Leaders:
Art Dobie, Microcircuit Engineering Corp. & Rudy Bacher, DuPont

Course Description:
The purpose of this course is to increase the understanding of the screen printing process thereby improving production yield and quality. The critical and integrated components for the screen, such as frames, screen mesh and emulsion are presented. Presented are some of the latest advancements in the screen, the composition and the printing process that enable screen printing to meet future circuit density requirements as well as definition for microwave circuits. The advantages of screen printing, an additive process, are described and compared to other subtractive deposition technologies.

The course is applications-oriented in terms of how to optimize the screen printing process; how to specify and use screens; rheology properties that affect the print; minimizing printing defects and trouble-shooting problems related to the screen and the printing process.

Who should attend?
This course is intended for production and process engineers, and others interested in learning how to optimize and increase the uses of the screen printing process.

Art Dobie is Manager of Screen Technology for Sefar America in Lumberton, NJ. He has been with Sefar over 23 years since receiving his BS in Graphic Communications (specializing in Screen Printing Technology) in 1980 from California University of Pennsylvania's School of Science and Technology.

Art has instructed the Technology of Screen Printing Professional Development Course of the International Microelectronics and Packaging Society (IMAPS) from its inception in 1991, and over the past twenty years, he has delivered many technical papers and presentations relating to screens and screen-printing technology to both microelectronic and screen-printing professionals at local, national and international level symposia.

Mr. Dobie is a Fellow of the Society of IMAPS, and has held numerous offices within the society, including president of the Keystone Chapter. Inducted on October 7, 1998, Art Dobie is an active member of the Academy of Screen Printing Technology (ASPT) of the SGIA, and was selected as a member of the ASPT's Technical Guide Book review committee.

Rudy Bacher has worked 37 years in Thick Film Technology for DuPont Research and Development as a Ceramic Engineer and currently as a Development Associate. He is a recipient of the ISHM Technical Achievement Award-1984; Corporate Marketing Excellence Award-1994; and IMAPS Instructor “Technology of Screen Printing” 1990-1998.

An Introduction to Microelectronics Packaging Technology
Course Leader:
Phillip G. Creter, Creter & Associates

Course Description:
This course will provide an introduction to microelectronics packaging technology for engineers, technicians and others involved in manufacturing, processing, development, quality, sales and marketing. Emphasis will be on visual aids including actual samples and a variety of photos and figures to provide the attendee with not only a solid base in how various microcircuits are made by various materials, processes and equipment but also what they look like. The attendee will learn classic hybrid definitions as well as current state of the art terminology of materials, processes and equipment, including: thick film technology, thin film technology, monolithic semiconductor technology; substrates (ceramic, conductors, dielectrics, co-fired, LTCC); components - passives, actives, chips vs. discrete, SMT components and flip chip; assembly including details of die attach, wire bonding and micro soldering, rework & repair, final assembly including details of visual inspection techniques, test, failure analysis, design, documentation standards, acronyms, glossary, list of symbols; clean rooms; and handling techniques.

Who should attend?
This course is designed for the attendee who has little initial familiarity with Microelectronics Packaging engineering terminology but would like to relate it to real life, everyday applications. Ideal for entry level technicians and engineers but also for people in quality assurance, sales, marketing, purchasing, safety, administration and program management. Emphasis will be on visual aids.

Phil Creter is a long-time member of IMAPS, having joined the New England Chapter of ISHM in 1974. He is a Fellow of the Society, and has been elected National Treasurer and President of the New England Chapter (twice). He received a BS in Chemistry from Suffolk University and has published 10 papers, holds a U.S. patent, has made numerous technical presentations (received Best Paper of Session award IMAPS 1998) and has chaired many technical sessions. He is currently a consultant (Creter & Associates) and has over 30 years of microelectronics packaging experience at Polymer Flip Chip Corporation, Mini-Systems, GTE Microelectronics Center and Itek Corporation. His past positions include General Manager of Microelectronics Center, Process Engineering Manager, Process Development Manager, Materials Engineering Manager and Manufacturing Engineer.

Introduction to Advanced Packaging
Course Leader:
R. Wayne Johnson, Auburn University

Course Description:
The increasing complexity and performance of semiconductor devices as well as the demands for smaller, light weight, high performance electronic products is driving develops in advanced packaging. To understand the implications of different packaging approaches, it is important to first understand the requirements and challenges posed by advanced semiconductors and product applications. This course begins with a review of semiconductor trends driving packaging requirements in terms of routing, electrical performance, thermal management and reliability including low-k dielectrics and lead free. With this as a starting point, advanced packaging is discussed, first divided into the topics of substrates and die connections and then as integrated packaging concepts. Ceramic, laminate, flex and thin film substrates are examined along with substrate embedded passives. Die connection by wire bonding and flip chip are commonly used today and both are examined. Trends in wire bonding are to ever finer pitch and wire bonding is finding increased applications in stacked die packages. Area array flip chip is increasingly used for high I/O count ASICs and microprocessors. The final topics presented are area array packages including stacked die, folded flex 2.5-D packages, chips first packages and 3-D packages.

Advanced packaging provides many opportunities for innovative new concepts to meet the challenges of future semiconductors and electronic products.

Who should attend?
This course is intended for chip designers needing a background in advanced packaging options, for those new to the packaging industry, and for material and equipment suppliers to the packaging industry.

Dr. Johnson is an Alumni Professor of Electrical Engineering at Auburn University and Director of the Laboratory for Electronics Assembly and Packaging (LEAP). At Auburn, he has established teaching and research laboratories for advanced packaging and electronics assembly. Research efforts are focused on materials, processing, and reliability for electronics assembly. He has worked in MCM design, MCM-L, -C and -D substrate technology as well as advanced SMT, wire bond and flip chip assembly techniques. He has published and presented numerous papers at workshops and conferences and in technical journals. He has also co-edited one IEEE book on MCM technology and written two book chapters in the areas of silicon MCM technology and MCM assembly. He received the 1997 Auburn Alumni Engineering Council Senior Faculty Research Award for his work in electronics packaging and assembly.

Dr. Johnson is the current Technical Vice President of IMAPS and was the 1991 President of the Society. He received the 1993 John A. Wagnon, Jr. Technical Achievement Award from ISHM, was named a Fellow of the Society in 1994 and received the Daniel C. Hughes Memorial Award in 1997. He is also a member of IEEE, SMTA, and IPC.

Dr. Johnson received the B.E. and M.Sc. degrees in 1979 and 1982 from Vanderbilt University, Nashville, TN, and the Ph.D. degree in 1987 from Auburn University, Auburn, AL, all in electrical engineering. He has worked in the microelectronics industry for DuPont, Eaton, and Amperex.

Low Temperature Co-fired Ceramics (LTCC)

Course Leaders:
Fred D. Barlow and Aicha Elshabini, University of Arkansas

Course Description:
This course is a one-day PDC focusing on the materials, processes, design, and applications of Low Temperature Co-fired Ceramics (LTCC). The course will begin with a brief history and background of the technology. A detailed discussion of the process flow and processes will cover each step used in the fabrication of LTCC substrates. A discussion of the material properties and design guidelines and considerations will also be covered in detail. Finally, a discussion of the technical advances and the technical applications of the technology will outline the relative strengths of LTCC for a number of target markets.

· History of LTCC and Background
· LTCC Process
· Material Properties
· Design Considerations
· Technical Advances
· Applications

Who should attend?
Engineers, managers, and technicians, who desire to expand their background or strengthen their understanding of the technology. The course will not assume any prerequisite background.

Aicha Elshabini is Professor of Electrical and Computer Engineering. She obtained a B.Sc. in Electrical Engineering at Cairo University, 1973, in both Electronics and Communications areas, a Masters in Electrical Engineering at University of Toledo, 1975, in Microelectronics, and a Ph.D. Degree in Electrical Engineering at the University of Colorado, 1978 in Semiconductor Devices and Microelectronics. Currently, she is serving the position of Professor and Department Head for the Electrical Engineering Department at University of Arkansas (since July 1, 1999), and Interim Department Head for Computer Science & Computer Engineering Department (since July 1, 2000). She has been serving as the faculty advisor for IMAPS student society at both institutions since 1980 to present time. Elshabini is a Fellow member of IEEE/CPMT Society (1993) Citation for ‘Contribution to Hybrid Microelectronics Education and to Hybrid Microelectronics to Microwave Applications,’ a Fellow member of IMAPS Society (1993), the International Microelectronics And Packaging Society, Citation for ‘Continuous Contribution to Microelectronics and Microelectronics Industries for numerous years.’ Dr. Elshabini was awarded the 1996 John A. Wagnon Jr., Technical Achievement Award from IMAPS. She has served as the Editor of the IMAPS International Journal of Microcircuits & Electronic Packaging for 10 years.

Fred Barlow earned a Bachelors of Science in Physics and Applied Physics from Emory University in 1990, a Masters of Science in Electrical Engineering from Virginia Tech in 1994, and a Ph.D. in Electrical Engineering from Virginia Tech in 1999. He is currently working as Assistant Professor in the Electrical Engineering Department at University of Arkansas. Dr. Barlow has published widely on electronic packaging and electronic materials evaluation and is Co-Editor of The Handbook of Thin Film Technology (McGraw Hill, 1998). In addition, he has written several book chapters including two chapters on thin films and one on components and devices. He has achieved the Outstanding Contribution Award with IMAPS in recognition of his efforts in developing and implementing the CD-ROM project for IMAPS publications, IMAPS home page on the Internet, and for his technical contributions. He currently serves on the IMAPS national technical committee for power packaging. His research interests include electronic packaging for power electronic and microwave applications as well as RF and microwave design.

Hermeticity Testing and Issues with RGA

Course Leader:
Thomas J Green, Microelectronics Packaging Consultant

Course Description:
Hermeticity of electronics packages and hermeticity test techniques continue to be of critical importance to the microelectronics packaging community. Specifically, in the area of MEMS/MOEMS packaging, OLEDs, wafer scale packaging, optoelectronic devices and packaging for Military and Space. In addition, there are a host of medical implants, bio medical devices and emerging nanotechology applications that all require hermetic packages and valid techniques to measure the leak rate. This course begins with an overview of hermetic sealing processes, e.g., seam welding (also know as brazing), laser welding; solder sealing and techniques/methods to seal components at the wafer level.

The class will then examine the accepted leak test techniques as prescribed in Mil Standard 883 Test Method 1014. This misunderstood test method is often a source of frustration. The basic science behind helium fine leak testing (both the fixed and flexible methods) will be presented to the class along with the advantages and potential pitfalls of helium fine leak testing. Difficulties and limitations in fine leak testing of small volume packages is a major industry concern, especially among the Space community. Issues with bomb times and pressures, measured leak rate vs air leak rates, “one way leakers,” virtual leakers will be addressed, along with gross leak testing; bubble, weight gain and other techniques such as dye penatrant. In each case the focus will be on practical issues facing the industry.

The latest techniques for measuring both gross and fine leak testing are Optical Leak Test (OLT). In this method a laser interferometer measures out of plane deflection on a lid surface in response to a changing pressure and relates them to an equivalent helium leak rate. For some packages, such as opto devices with fiber arrays, OLEDs and wafer level testing OLT is the only viable technique.

The ultimate goal is to seal the electronics/MEMS in a dry, inert atmosphere to allow reliable functioning of the device over its intended lifetime. A proper pre seal bake out is required for a dry package. The gas ambient inside the package is measured using Residual Gas Analysis. What is RGA (Residual Gas Analysis)? How does this relate to hermeticity testing? Are the current spec limits valid for next generation MEMS/MOEMS and Nanotechnology? What is the basis for the existing spec? Besides moisture, what other outgassing products are of concern? The basic science behind RGA testing will be presented and industry case studies will help illustrate the answers to these question and more.

Special Course Material:
All attendees will receive a complimentary copy of Hermeticity of Electronic Packages, by Hal Greenhouse, Noyes Publications 2000 (List price $139).

Who should attend?
This PDC is intended as an introductory to intermediate level course for process engineers, designers, quality engineers, and managers responsible for sealing, leak testing and RGA results.

Mr. Green is a consultant and adjunct professor at the National Training Center for Microelectronics. At NTCm he designs curriculum and teaches industry short courses relating to advanced microelectronics manufacturing processes. He has over twenty years experience in the microelectronics industry at Lockheed Martin Astro Space and USAF Rome Laboratories. At Lockheed he was a Staff engineer responsible for the materials and manufacturing processes used in building custom high reliability space qualified microcircuits (Hybrids, MCMs and RF modules) for military and commercial communication satellites. Tom has demonstrated expertise in seam sealing and leak testing processes. He has conducted experiments and presented technical papers at NIST and IMAPS on leak testing techniques and optimization of seam welding processes through statistical DOE methods. At Rome Labs he worked as a senior reliability engineer and analyzed component failures from AF avionic equipment along with providing technical support for a variety of Mil specs and standards (e.g., MIL-PRF-38534 and MIL-STD-883). Tom is an active member of IMAPS and is currently the chairman of the Optoelectronics National Technical Committee. He has a B.S. in Materials Engineering from Lehigh University and a Masters from the University of Utah.

PDC Info
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