Professional Development Courses (PDCs)
(All PDCs run 9am - 5pm)

Sunday PDCs | PDC General Info

Register On-line

*All PDCs will be held in the Pennsylvania Convention Center. Room locations will be made available closer to the show date.

Wire Bonding in Microelectronics
Course Leader:
George G. Harman, National Institute of Standards and Technology

Course Description:
Wire bond manufacturing defects range typically from about 1000 to 100 ppm, with exceptions to >10,000 and <50 ppm. In order to achieve the lower numbers in production, one must understand all of the conditions that affect both bond yield and reliability (since they are interrelated). This course will discuss many large- and small-wire bonding problems, as well as subjects of specific interest to hybrid/MCM device bonding. In addition, a number of advanced topics, such as high yield, fine pitch (towards 20 micron pitch), and bonding to flex will be covered. Newer developments (e.g., high frequency ultrasonic bonding) are included along with a major discussion of wire bonding to multichip modules and other soft substrates. Wire bond testing and metallurgy (covering both aluminum and gold bonds); intermetallic compounds; cleaning for yield and reliability; failures resulting from electroplating; mechanical problems in wire bonding; new bond technologies and developments; how ultrasonic bonds are formed, and the metallurgy of gold and aluminum wire. It concludes with methods of implementing TAB and Flip Chip by using wire bonding techniques.

Who should attend?
Engineers in R&D, QA, QC, manufacturing, process development, and advanced technicians. It is assumed that participants have some familiarity with wire bonding and general device assembly technologies.

Special Course Materials:
All attendees will receive a complimentary copy of Wire Bonding in Microelectronics, by George Harman, McGraw Hill, NY, 1997 (List price $65), as well as course notes and explanations.

Mr. Harman is a Fellow Emeritus of the National Institute of Standards and Technology (NIST), and a consultant. He received a BS in Physics from Virginia Polytechnic Institute & State University and a MS in Physics from the University of Maryland. Mr. Harman has published over 60 papers, two books on wire bonding, and holds four U.S. Patents. He was the 1995 President of ISHM and is a Fellow of IMAPS and the IEEE. He has received numerous awards for his work from IMAPS, IEEE, DVS and others. He has presented numerous talks, and has taught courses for the University of Arizona and IMAPS for over 15 years, as well as the IEEE, to name a few. He has presented many papers and given courses in the USA, Europe, and Asia.

Advanced Thermal Management Materials
Course Leader:
Dr. Carl Zweben, Advanced Thermal Management Materials Consultant

Course Description:
In response to critical needs, there have been revolutionary advances in thermal management materials in the last few years. There are now over 15 low-CTE, low-density materials with thermal conductivities ranging between 400 and 1700 W/m-K, and many others with somewhat lower conductivities. Some are low cost. Others have the potential to be low cost in high-volume. Production applications include servers, laptops, PCBs, PCB cold plates/heat spreaders, cellular telephone base stations, hybrid electric vehicles, power modules, phased array antennas, thermal interface materials (TIMs), optoelectronic telecommunication packages, laser diode and LED packages, and plasma displays.

This course covers the large and increasing number of advanced thermal management materials, providing an in-depth discussion of properties, manufacturing processes, applications, cost, lessons learned, typical development programs, and future directions. Traditional materials are discussed for reference. Participants are invited to bring their thermal management problems for discussion.

Who should attend?
Engineers, scientists and managers involved in microelectronic, optoelectronic and MEMS/MOEMS packaging design, production and R&D; packaging material suppliers.

Dr. Zweben, now an independent consultant, directed development and application of advanced thermal management and packaging materials for over 30 years. He was formerly Advanced Technology Manager and Division Fellow at GE Astro Space, where he directed the Composites Center of Excellence, and was the first to use Al/SiC. Other affiliations have included Du Pont, Jet Propulsion Laboratory and the Georgia Institute of Technology NSF Packaging Research Center. Dr. Zweben was the first, and one of only two winners of both the GE One-in-a-Thousand and Engineer-of-the-Year awards. He is a Fellow of ASME, ASM and SAMPE, an Associate Fellow of AIAA, and has been a Distinguished Lecturer for AIAA and ASME. He has published and lectured widely.

Technology of Screen Printing
Course Leaders:
Art Dobie, Sefar Printing Solutions, Inc. & Rudy Bacher, Consultant

Course Description:
The purpose of this course is to increase the understanding of the screen printing process thereby improving production yield and quality. The critical and integrated components for the screen, such as frames, screen mesh and emulsion are presented. Presented are some of the latest advancements in the screen, the composition and the printing process that enable screen printing to meet future circuit density requirements as well as definition for microwave circuits. The advantages of screen printing, an additive process, are described and compared to other subtractive deposition technologies.

The course is applications-oriented in terms of how to optimize the screen printing process; how to specify and use screens; rheology properties that affect the print; minimizing printing defects and trouble-shooting problems related to the screen and the printing process.

Who should attend?
This course is intended for production and process engineers, and others interested in learning how to optimize and increase the uses of the screen printing process.

Art Dobie is Manager of Screen Technology for SEFAR Printing Solutions headquartered in Lumberton, NJ. He has been with SEFAR over 24 years since receiving his BS in Graphic Communications (specializing in Screen Printing Technology) in 1980 from California University of Pennsylvania’s School of Science & Technology. Art has instructed the Technology of Screen Printing Professional Development Course for IMAPS (International Microelectronics And Packaging Society) since its inception in 1991. Over the past twenty-four years, he has delivered many technical papers and presentations relating to screens and screen-printing technology to both microelectronic and screen printing professionals at local, national and international levels. Art is a Fellow of the Society of IMAPS, and has held numerous offices within the society, including president and vice-president of the Keystone Chapter. He is also Exhibits Co-Chair for IMAPS 2005, after having served in the same capacity for ISHM ‘97. On October 7, 1998, Art Dobie was inducted into the Academy of Screen Printing Technology (ASPT) of the SGIA, and was also selected to the ASPT’s Technical Review Committee. The ASPT represents the highest level of technological expertise in the screen printing industry. Recognized authorities in their field, Academy members are chosen on the basis of their demonstrated ability and willingness to assist in the betterment of the industry.

Rudy Bacher has worked 43 years in Thick Film Technology for Dupont Research and Development as a Senior Development Associate. Retired in 2004 and currently is consultant for Dynamesh, the US division of NBC, Japan. He was a recipient of the ISHM Technical Achievement Award in 1984; Dupont Corporate Marketing Excellence Award-1994 and Accomplishment Awards for thick film compositions for high yield fine line printing. Received 8 patents and has been an IMAPS Instructor “Technology of Screen Printing” 1990 – 2005.

Introduction to Microelectronics Packaging Technology
Course Leader:
Phillip G. Creter, Creter & Associates

Course Description:
This course will provide an introduction to microelectronics packaging technology for engineers, technicians and others involved in manufacturing, processing, development, quality, sales and marketing. No prior knowledge of Microelectronics is required. Emphasis will be on visual aids including actual samples and a variety of photos and figures to provide the attendee with not only a solid base in how various microcircuits are made by various materials, processes and equipment but also what they look like. The attendee will learn classic hybrid definitions as well as current state of the art terminology of materials, processes and equipment, including: thick film technology, thin film technology and monolithic semiconductor technology; substrates (ceramic, conductors, dielectrics, co-fired, LTCC); components (passives, actives, chips vs. discrete, SMT components and flip chip); assembly including details of die attach, wire bonding and micro soldering, rework & repair; final assembly including details of visual inspection techniques, test, and failure analysis. Also covered is design, documentation standards, acronyms, list of symbols, clean rooms and handling techniques. Video clips highlight various microcircuit assembly processes. Included in the 200-page course handout is an updated glossary and list of references the attendee will find invaluable.

Who should attend?
This course is designed for the attendee who has little initial familiarity with Microelectronics Packaging engineering terminology but would like to relate it to real life, everyday applications. Ideal for entry level technicians and engineers but also for people in quality assurance, sales, marketing, purchasing, safety, administration and program management; also ideal for non-engineering support people. Emphasis will be on visual aids.

Phil Creter is a long-time member of IMAPS, having joined the New England Chapter of ISHM in 1974. He is a Fellow of the Society, and has been elected National Treasurer and President of the New England Chapter (twice). He received a BS in Chemistry from Suffolk University and has published numerous papers, holds a U.S. patent, has made many technical presentations (received Best Paper of Session award IMAPS 1998) and has chaired several technical sessions. He is currently a consultant (Creter & Associates) and has over 30 years of microelectronics packaging experience at Polymer Flip Chip Corporation, Mini-Systems, GTE and Itek Corporation. His past positions include GTE Microelectronics Center Manager, Process Engineering Manager, Process Development Manager, Materials Engineering Manager and Manufacturing Engineer. He currently teaches professional development courses at microelectronics events and is a certified instructor for the Department of Homeland Security.

Introduction to Advanced Packaging
Course Leader:
R. Wayne Johnson, Ph.D., Auburn University

Course Description:
The increasing complexity and performance of semiconductor devices as well as the demands for smaller, light weight, high performance electronic products is driving developments in advanced packaging. To understand the implications of different packaging approaches, it is important to first understand the requirements and challenges posed by advanced semiconductors and product applications. This course begins with a review of semiconductor trends driving packaging requirements in terms of routing, electrical performance, thermal management and reliability including low-k dielectrics and lead free. With this as a starting point, advanced packaging is discussed, first divided into the topics of substrates and die connections and then as integrated packaging concepts. Ceramic, laminate, flex and thin film substrates are examined along with substrate embedded passives. Die connection by wire bonding and flip chip are commonly used today and both are examined. Trends in wire bonding are to ever finer pitch and wire bonding is finding increased applications in stacked die packages. Area array flip chip is increasingly used for high I/O count ASICs and microprocessors. The final topics presented are area array packages including stacked die, folded flex 2.5-D packages, chips first packages and 3-D packages.

Advanced packaging provides many opportunities for innovative new concepts to meet the challenges of future semiconductors and electronic products.

Who should attend?
This course is intended for chip designers needing a background in advanced packaging options, for those new to the packaging industry, and for material and equipment suppliers to the packaging industry.

Dr. Johnson is a Ginn Professor of Electrical Engineering at Auburn University and Director of the Laboratory for Electronics Assembly and Packaging (LEAP). At Auburn, he has established teaching and research laboratories for advanced packaging and electronics assembly. His research efforts are focused on electronics manufacturing, advanced packaging and extreme environment electronics. He has published and presented numerous papers at workshops and conferences and in technical journals as well as book chapters on MCM technology and electronics assembly. Dr. Johnson was the Technical Vice President of IMAPS (2000-2004) and was the 1991 President of the Society. He received the 1993 John A. Wagnon, Jr. Technical Achievement Award from ISHM, was named a Fellow of the Society in 1994 and received the Daniel C. Hughes Memorial Award in 1997. He is also a member of SMTA, and IPC and a Fellow of IEEE. Dr. Johnson received the B.E. and M.Sc. degrees in 1979 and 1982 from Vanderbilt University, Nashville, TN, and the Ph.D. degree in 1987 from Auburn University, Auburn, AL, all in electrical engineering. He has worked in the microelectronics industry for DuPont, Eaton, and Amperex.

Low Temperature Co-fired Ceramics (LTCC)
Course Leaders:
Fred D. Barlow, Aicha Elshabini, Gangqiang Wang, University of Arkansas

Course Description:
This course focuses on the materials, processes, design, and applications of Low Temperature Co-fired Ceramics (LTCC). The course will begin with a brief history and background of the technology. A detailed discussion of the process flow and processes will cover each step used in the fabrication of LTCC substrates. A discussion of the material properties and design guidelines and considerations will also be covered in detail. Finally, a discussion of the technical advances and the technical applications of the technology will outline the relative strengths of LTCC for a number of target markets.

• History of LTCC and Background
• LTCC Process
• Material Properties
• Design Considerations
• Technical Advances
• Applications

Who should attend?
Engineers, managers, and technicians, who desire to expand their background or strengthen their understanding of the technology. The course will not assume any prerequisite background.

Aicha Elshabini is Professor of Electrical and Computer Engineering. She obtained a B.Sc. in Electrical Engineering at Cairo University, 1973, in both Electronics and Communications areas, a Masters in Electrical Engineering at University of Toledo, 1975, in Microelectronics, and a Ph.D. Degree in Electrical Engineering at the University of Colorado, 1978 in Semiconductor Devices and Microelectronics. Currently, she is serving the position of Professor and Department Head for the Electrical Engineering Department at University of Arkansas (since July 1, 1999), and Interim Department Head for Computer Science & Computer Engineering Department (since July 1, 2000). She has been serving as the faculty advisor for the IMAPS student program at both institutions from 1980 to present time. Elshabini is a Fellow of IEEE/CPMT Society (1993) Citation for ‘Contribution to Hybrid Microelectronics Education and to Hybrid Microelectronics to Microwave Applications,’ a Fellow of IMAPS Society (1993), The International Microelectronics And Packaging Society, Citation for ‘Continuous Contribution to Microelectronics and Microelectronics Industries for numerous years.’ Dr. Elshabini was awarded the 1996 John A. Wagnon Jr., Technical Achievement Award from IMAPS. She has served as the Editor of the IMAPS International Journal of Microcircuits & Electronic Packaging for 10 years.

Fred Barlow earned a Bachelors of Science in Physics and Applied Physics from Emory University in 1990, a Masters of Science in Electrical Engineering from Virginia Tech in 1994, and a Ph.D. in Electrical Engineering from Virginia Tech in 1999. He is currently working as Assistant Professor in the Electrical Engineering Department at University of Arkansas. Dr. Barlow has published widely on electronic packaging and electronic materials evaluation and is Co-Editor of “The Handbook of Thin Film Technology” (McGraw Hill, 1998). In addition, he has written several book chapters including two chapters on thin films and one on components and devices. He has achieved the Outstanding Contribution Award with IMAPS in recognition of his efforts in developing and implementing the CD-ROM project for IMAPS publications, IMAPS home page on the Internet, and for his technical contributions. He currently serves on the IMAPS national technical committee for power packaging. His research interests include electronic packaging for power electronic and microwave applications as well as RF and microwave design.

Gangqiang (Victor) Wang obtained his B.S. degree in Engineering from Chongqing University in China in 1988, his M.S. degree in Metallurgy and Materials from Chongqing University in China in 1991, and his Ph.D. in Materials Science and Engineering from Tsinghua University in China in 1996. During his career, Victor received numerous awards; outstanding graduate scholarship five times from Tsinghua University, outstanding achievement and management three times from Tsinghua University, best graduate paper award in the Symposium of Chinese Material Research Society, and an award for science and technology advancement from the State Education Commission of China. Dr. Victor Wang has been serving as a Research Assistant Professor in the Electrical Engineering Department at University of Arkansas since January 2001. His areas of expertise include integration of passive components in low temperature cofired ceramics (LTCC), design, simulation, fabrication, and measurements of LTCC based RF and microwave devices, and advanced LTCC processing for high density interconnect and microsystem integration.

Hermeticity Testing and Issues with RGA
Course Leader:
Thomas J. Green, Microelectronics Packaging Consultant

Course Description:
Hermeticity of electronics packages and hermeticity test techniques continue to be of critical importance to the microelectronics packaging community. Specifically, in the area of MEMS/MOEMS packaging, OLEDs, wafer scale packaging, optoelectronic devices and packaging for Military and Space. In addition, there are a host of medical implants, bio medical devices and emerging nanotechnology applications that all require hermetic packages and valid techniques to measure the leak rate. This course begins with an overview of hermetic sealing processes, e.g., seam welding (also known as brazing), laser welding; solder sealing and techniques/methods to seal MEMS components at the wafer level.

The class will then examine the accepted leak test techniques as prescribed in Mil Standard 883 Test Method 1014. This misunderstood test method is often a source of frustration. The basic science behind helium fine leak testing (both the fixed and flexible methods) will be presented to the class along with the advantages and potential pitfalls of helium fine leak testing. Difficulties and limitations in fine leak testing of small volume packages is a major industry concern, especially among the Space community. Issues with bomb times and pressures, measured leak rate vs air leak rates, “one way leakers,” virtual leakers will be addressed, along with gross leak testing; bubble, weight gain and other techniques such as dye penatrant. In each case the focus will be on practical issues facing the industry.

The latest technique for measuring both gross and fine leak testing is Optical Leak Test (OLT). In this method a laser interferometer measures out of plane deflection on a lid surface in response to a changing pressure and relates them to an equivalent helium leak rate. For some packages, such as opto devices with fiber arrays, OLEDs and wafer level testing OLT is the only viable technique.

The ultimate goal is to seal the electronics/MEMS in a dry, inert atmosphere to allow reliable functioning of the device over its intended lifetime. A proper pre seal bake out is required for a dry package. The gas ambient inside the package is measured using Residual Gas Analysis. What is RGA (Residual Gas Analysis)? How does this relate to hermeticity testing? Are the current spec limits valid for next generation MEMS/MOEMS and Nanotechnology? What is the basis for the existing spec? Besides moisture what other outgassing products are of concern? The basic science behind RGA testing will be presented and industry case studies and will help illustrate the answers to these questions and more.

Special Course Material:
All attendees will receive a complimentary copy of the “Hermeticity of Electronic Packages” by Hal Greenhouse, Noyes Publications 2000 (List price $159).

Who should attend?

This PDC is intended as an introductory to intermediate level course for process engineers, designers, quality engineers, and managers responsible for sealing, leak testing and RGA results.

Mr. Green is a consultant and adjunct professor at the National Training Center for Microelectronics. At NTCm he designs curriculum and teaches industry short courses relating to advanced microelectronics manufacturing processes. He has over twenty years experience in the microelectronics industry at Lockheed Martin Astro Space and USAF Rome Laboratories. At Lockheed he was a Staff engineer responsible for the materials and manufacturing processes used in building custom high reliability space qualified microcircuits (Hybrids, MCMs and RF modules) for military and commercial communication satellites. Tom has demonstrated expertise in seam sealing and leak testing processes. He has conducted experiments and presented technical papers at NIST and IMAPS on leak testing techniques and optimization of seam welding processes through statistical DOE methods. At Rome Labs he worked as a senior reliability engineer and analyzed component failures from AF avionic equipment along with providing technical support for a variety of Mil specs and standards (e.g., MIL-PRF-38534 and MIL-STD-883). Tom is an active member of IMAPS and is currently chairman of the Optoelectronics National Technical Committee. He has a B.S. in Materials Engineering for Lehigh University and a Masters from the University of Utah.

Adhesion Fundamentals in Microelectronic Packaging
Course Leader:
Professor Raymond A. Pearson, Lehigh University

Course Description:
Polymers are widely used in electronic packaging. The lack of adhesion can adversely affect reliability as well as package performance. The intention of this course is to review the fundamentals of adhesion and apply them to interfaces found in Plastic-Quad Flat Packs (PQFP), chip-scale packages (CSP), and Flip-Chip (FC) assemblies. Adhesion issues in molding compounds, die attach adhesives, and underfill resins will be covered. By the end of the course, you should know how to choose proper tools to predict and measure adhesion.

Course Outline:
1. Discuss Course Objectives
2. Review Microelectronic Packages (Brief)
3. Discuss the Role of Chemical Forces in Adhesion
4. Examine Extrinsic Deformation Mechanisms in Polymers
5. Review Common Tests to Assess Adhesion
6. Model Interfacial Fracture Toughness
7. Apply Interfacial Fracture Toughness Concepts to Gage Reliability

Who should attend?
Engineers, scientists and managers involved in the design, process and manufacturing of IC electronic components and hybrid packaging, electronic material suppliers involved in materials manufacturing and research & development.

Dr. Raymond A. Pearson joined the Materials Science and Engineering Department at Lehigh University in August of 1990 after obtaining his doctorate in Materials Science and Engineering from University of Michigan. Prior to graduate school, Ray had worked for seven years with General Electric Company: from 1980-1984 as an associate staff member at GE’s Corporate Research and Development Center in Schenectady, New York and from 1984-1987 as a materials specialist at GEPE’s Product Technology Center in Bergen op Zoom, The Netherlands. His research interests include all aspects of processing, deformation, yield, and fracture of polymers. He has worked extensively in the area of fracture mechanisms and adhesion, and with organizations such as the Semiconductor Research Corporation and SEMATECH. He serves on the Editorial Board of the International Journal of Microelectronic Packaging: Materials and Technologies.

PDC Reception
Sunday, September 25th
5:00 pm - 6:00 pm
PDC Instructors and Attendees only.

Sunday PDCs | PDC General Info





Sponsored in part by:

Golf Tournament Sponsorsed in part by:

IMAPS - International Microelectronics And Packaging Society
and Sidney J. Stein Educational Foundation
611 2nd Street, NE -- Washington, DC 20002
imaps @ | 202.548.4001 | 202.548.6115 (fax)