Technical
Program
Wednesday, September
28, 2005
*All Technical Sessions will be held in the Pennsylvania Convention
Center. Room locations will be made available closer to the
show date.
WA1 | WA2 | WA3 | WA4 | WA5 | WA6 | WA7 | WA8 | WA9 |
WA10
WP1 | WP2 | WP3 | WP4 | WP5 | WP6 | WP7 | WP8 | WP9
Tuesday
Sessions | Thursday Sessions
Register
On-line
WA1
Emerging Technologies
Chairs: Ron Jensen, Honeywell Solid State Electronics Center;
K. (Jay) Jayaraj, SiWave Inc.
8:00 am – 9:15 am
This session focuses on emerging nanotechnologies and their applications
in electronic packaging.
Hybrid Technique for Mass Synthesis of Field Effect Transistors using
Gallium Nitride Nanowires
Son Nguyen, Joan Z. Delalic, Temple University; Jeffrey M.
Catchmark, Penn State
Approaches for Hybrid Biological and Synthetic System Integration
Vivek Verma, William O. Hancock, Jeffery M. Catchmark, The
Pennsylvania State University
Manufacturing Methods Employing Molecular Ruler Lithography
Shyamala Subramanian, Gregory S. McCarty, Jeffrey M. Catchmark,
Pennsylvania State University
WA2
Attachment Technologies - Solder and Conductive Pastes
Chairs: Greg Caswell, VirTex Assembly Services, Inc.; Timothy
Lenihan, TGL Consulting
8:00 am – 9:15 am
Improvements in flip chip materials are essential to successful process
growth. This session focuses on improvements in underfills and solder
for the flip chip process.
Room Temperature Soldering of Connectors to PCB using Reactive Multilayer
Foils
Jai S. Subramanian, Jonathan Levin, David Van Heerden, Omar
Knio, Michael Powers, Reactive Nanotechnologies
Interconnect Technologies for RFID Assembly
Bo Xia, Jayesh Shah, Chih-Min Cheng, Wanda O’Hara, Vito Buffa,
Emerson & Cuming
Lead Free BGA Package Design Guide for Reliability
Cheng Siew Tay, Intel Products (M) Sdn Bhd.
WA3
Manufacturing I: Packaging Processes & Quality Assessments
Chair: John Graves, The Micro-Tech Index; Randy Hume, Visteon
8:00 am – 9:15 am
From performing the assembly on thin substrates through the sealing
of hermetic packages, improvements in the processes for these operations
are key to the electronics packaging industry. The ability to verify
that these processes meet the design requirements without defect is
key to making a quality product. This session focuses on several processes
and quality assessment methods for manufacturing electronic assemblies.
Thermosonic Bonding of High Pin Count Flip Chips on Flexible Substrates
Gerard Kums, J. van Delft, H. de Vries, Philips Applied Technologies
Wire Looping Optimization in Fine Pitch Dual Row In-line Pad Devices
Tu Anh Tran, Kenneth Lightle, Dennis Ravenscraft, Alvin Youngblood,
Freescale Semiconductor
Hermetic Sealing of Microelectronics Packages using a Room Temperature
Soldering Process
Jai S. Subramanian, Jonathan Levin, David Van Heerden, Omar
Knio, Michael Powers, Reactive Nanotechnologies
WA4
Photonics/Optoelectronics Packaging
Chairs: Charlie Banda, Laboratory for Physical Sciences; Bud
Osthaus, Merrimac Industries
8:00 am – 8:50 am
Developments in optoelectronics and photonics assembly processes continue
to meet stringent packaging requirements that often surpass those of
conventional microelectronics assembly. Novel materials, processing,
assembly and alignment techniques are presented in this session that
address these packaging challenges.
Characterization
of “In Package MEMS Aligner” for
Optoelectronics
Jason T. Iceman, Raymond A. Pearson, Richard P. Vinci, Lehigh
University
Evaluating the Dimensional Stability of Optoelectronic Adhesives using
Test Vehicles
Raymond Pearson, Thomas Daugherty, Lehigh University; Bob Sullivan,
High Density Packaging Users Group
WA5
Advanced Technology & Production Trend on Lead-Free Soldering in
Japan (Japanese to English Translation)
Chairs: Fumio Miyashiro, PI R&D Co., Ltd.; Andy London, Heraeus
Incorporated – CMD
8:00 am – 9:15 am
In Japan, this year is the last year to complete lead-free soldering
in production line at almost all electronics equipment and home appliance
companies. In this session the history and procedure of introduction
of lead-free soldering in Japan will be presented by Prof. Suganuma
as a 50 minute keynote presentation; and representative solder alloy
cases will be presented by each company in detail.
Lead-Free Soldering Progress and Technical Four Issues - Whiskers,
Bath Erosion, Pb Contamination and Lowering Temperature
Katsuaki Suganuma ISIR, Osaka University
Sn-Ag-Cu
Ikuo Mori, Toshiba Corporation
WA6
Fine Pitch Interconnect Technologies
Chairs: Wayne Johnson, Auburn University; Bob Chylak, Kulicke & Soffa
Industries Inc.
9:45 am – 11:25 am
The growth of Au-Al intermetallic in fine pitch wire bonds is a critical,
long-term reliability issue. This session focuses on the assembly and
reliability of fine-pitch wire bonds.
Enhancing Fine Pitch, High I/O Devices with Copper Ball Bonding
Lee R. Levine, Patrick Devlin, Kulicke & Soffa Industries Inc.
TEM Microstructural
Analysis of Intermetallic Phases Formed During Wire Bonding and Annealing
in the Au-Al System
Ziv Atzmon, Wayne D. Kaplan, Adi Karpel, Giyora Gur, Kulicke & Soffa Bonding
Tools
Micro-Post Assembly Process
Nabil Homsy, First Level Inc.
Total Lead-Free Flip Chip Ball Grid Array
Kouichi Hirosawa, Keisuke Sato, NEC Electronics
WA7
Flip Chip Reliability (Underfill, Cleaning, & Rework)
Chairs: Beth Keser, Freescale Semiconductor; John Wood, Emerson & Cuming
9:45 am – 11:25 am
As flip chip packaging continues to evolve, underfill and cleaning
continue to be a problem. The papers presented in this session address
these issues.
Effect of Compatibility between the Lead-Free Fluxes and Cyanate Ester
Underfill on the Lead-Free Flip Chip Assembly and Reliability
Raghunandan Chaware, George He, Ablestik Laboratories (National
Starch and Chemicals); Leon Stiborek, Jeremias Libres, Manots Marquez,
Charles Odegard, Marvin Cowens, Texas Instruments Corporation
Development of New Repairable Underfill Technology for High-Density
Packaging Application
Masahiro Kubo, Ichiro Hazeyama, Akira Ohuchi, Tomoo Murakami,
Koji Matsui, NEC Corporation
Development of Wafer Level Underfill Process
W. H. Lee, Y. P. Wang, C. S. Hsiao, S. Katsurayama, Y. Sakamoto,
H. Yamada, Siliconware Precision Industries Co., Ltd. (SPIL)
Reliability Issues of No-Clean Flux Technology for Printed Circuit
Boards
Sheng Zhan, Michael H. Azarian, Michael Pecht, University of
Maryland
WA8
Manufacturing II: Thin Substrates & Embedded Components
Chairs: Ken Kuang, Torrey Hills Technologies, LLC; Keith Easler,
Kyocera America Inc.
9:45 am – 11:25 am
As the density required for high functionality per unit volume increases,
methods to produce thin substrates and to embed passive elements within
the substrates provide a means to achieve this goal. This session focuses
on both of these areas, improvements in the manufacture of thin substrates,
and the technology of embedding passive devices in the substrate.
Manufacturability of Very Thin Zirconia Tapes in an ISO 9001 Environment
Alvin H. Feingold, M. A. Stein, R.L. Wahlers, M. Heinz, E.
Twiname, Z. Topka, Electro-Science Labs, Inc.
50µm
Wafers with Improved Total Thickness Variation by Means of a Low Cost
Modified Reusable Carrier
Wafer
Parthiban Arunasalam, State University of New York at Binghamton;
Matthew H. Gordon, Leonard W. Schaper, Susan L. Burkett, Ziaur Rahman,
Silke Spiesshoefer, Gowtham Vangara, University of Arkansas
SiP Assembly
Challenges – Where
Semiconductor Packaging and Circuit Board Assembly Converge
Jacques Coderre, Universal Instruments Corporation
A Dielectric Resonator Buried in a Layered Polymer Package
Eric Hoppenjans, Wing Han She, William J. Chappell, Purdue
University
WA9
LTCC Technology
Chairs: Ron J. Barnett, GeoMat Insights; John Menaugh, DuPont
Microcircuit Materials
9:45 am – 11:25 am
Ceramic based technology has been a solid choice over the years for
circuit functions demanding high performance and high density. LTCC
is no longer a novel technology practiced by a few suppliers. It is
now a reliable technology to manufacture high volume, high density structures.
This session highlights innovative processing and technology advancements.
Requirements for Thick Film Conductor Pastes for Fuel Level Senders
Stefan Flick, Roland Kersting, David Malanga, W. C. Heraeus
GmbH Circuit Materials Division
A Direct Methanol Fuel Cell using Cermet Electrodes in Low Temperature
Cofire Ceramic (LTCC)
W. Kinzy Jones, Zheng Feng, Naveen Savaram, Vic Tittle, Florida
International University
Distributed Filter Characterization in Low Loss LTCC using a Co-Fired
Photoimageable Conductor
Timothy P. Mobley, Patricia Ollivier, Michael A. Smith, DuPont
Electronic Technologies
Novel LTCC Technology with Embedded High Value Capacitor
Takafumi Kamei, Toshihiko Maeda, Tetsuya Toujou, Kouta Ikeda,
Ken Furukuwa, Katsuhiko Onitsuka, Tsukasa Yanagida, Kyocera Corporation
WA10
Advanced Technology & Production Trend on Lead-Free Soldering in
Japan (Japanese to English Translation)
Chairs: Fumio Miyashiro, PI R&D Co., Ltd.; Andy London, Heraeus
Incorporated – CMD
9:45 am – 11:00 am
In Japan, this year is the last year to complete lead-free soldering
in production line at almost all electronics equipment and home appliance
companies. In this session the history and procedure of introduction
of lead-free soldering in Japan will be presented by Prof. Suganuma
as a 50 minute keynote presentation; and representative solder alloy
cases will be presented by each company in detail.
Practical use of Sn-Ag-Bi-In Lead-Free Solder and Its Advanced Technology
Akio Furusawa, Matsushita Electric Industrial Co., Ltd.
Sn-Zn-Al
Keiichi Yamamoto, Fujitsu Limited
Cu-Sn
Osamu Ikeda, Hitachi, Ltd.
WP1
Interactive Forum (Poster Session)
Chairs: Lee Levine, Kulicke & Soffa Industries Inc.; Don Havas,
Applied Technology and Science
12:00 pm – 3:15 pm
One-on-One Interactive Forum. This is your chance for detailed interaction
with authors whose work is too good to miss.
New Thick-Film Ballasts for Mercury-Free Sterilising UVC Lamp
Janusz J. Gondek, Private Institute of Electronic Engineering;
Slawomir Kordowiak, Cracow University of Technology; J. Kocol, Technical
School of Telecommunication
Needle-less Picking of Ultra Thin Dice
Wolfgang Herbst, Andreas Marte, Alphasem AG
Development of the Micro CPL for High Thermal Density
Seok Hwan Moon, Gunn Hwang, ETRI
Marking of Wafers and Chip Scale Packages using Ultra Fast Lasers
Bo Gu, GSI Lumonics Inc.
How Ultra-Thin Power-Ground Dielectrics in First and Second Level Packaging
Applications can be used to meet Power Distribution, EMC, Size and Weight
Requirements
Joel S. Peiffer, William Balliette, 3M Company
Uniformity Control of Solder Bump Heights in Stencil Printing Process
for Flip Chip Packages
Jin-Woo Lee, Chang-Soo Jang, Joong-Do Kim, Han-Gu Kim, Samsung
Techwin Co., Ltd.
Solder Short Failure Mechanism in System-In-Packages
Shafi Saiyed, Bob Murcko, K. Srihari, State University of New
York at Binghamton; Dipak Sengupta, Analog Devices Inc.
The Penn State Nanofabrication Facility
Jeffrey M. Catchmark, Shyamala Subramanian, The Pennsylvania
State University
Pre-Applied Underfill Approaches for Pb-Free CSP Assemblies
Timothy Adams, Paul Morganelli, Vinod Mohan, Matt Laffey, Jayesh
Shaw, Emerson & Cuming
Pumped Liquid Cooling System for Desktop Computers
Nelson Gernert, Kevin Wert, Gregg Baldassarre, Thermacore,
Inc.; Michael Wilson, Jonathan Wattelet, Modine Manufacturing Company
WP2
Fine Pitch Interconnect Technologies
Chairs: Wayne Johnson, Auburn University; Bob Chylak, Kulicke & Soffa
Industries Inc.
1:30 pm – 2:45 pm
The growth of Au-Al intermetallic in fine pitch wire bonds is a critical,
long-term reliability issue. This session focuses on the assembly and
reliability of fine-pitch wire bonds.
Low Temperature Fine Pitch Bonding on the Flexible Substrate with NCA
Applied
Zhigang Chen, Young-Ho Kim, Hanyang University
Evaluation of Electroless Ni-Au Finishes for Wirebonding on PWBs
Allen C. Keeney, John Lehtonen, David Lee, George Coles, Katherine
Mach, Shaun Francomacaro, Johns Hopkins University/APL
Novel Method of Separating Probe and Wire Bond Regions without Increasing
Die Size and Reducing Weak Fab-BEOL Adhesion Interfaces
Chu-Chung Lee, TuAnh Tran, Bill Williams, Jody Ross, Freescale
Semiconductor Inc.
WP3
Flip Chip Reliability (Underfill, Cleaning, & Rework)
Chairs: Beth Keser, Freescale Semiconductor; John Wood, Emerson & Cuming
1:30 pm – 2:45 pm
As flip chip packaging continues to evolve, underfill and cleaning
continue to be a problem. The papers presented in this session address
these issues.
Effects of High Resistance Bumps caused by Al2O3 Film Remainders and
Process Characteristics of Flip Chip Package
Rick Yu, Tom Tai, C. H. Hsu, Jowel Taguibao, Mars Tsai, Homing
Tong, Advanced Semiconductor Engineering, Inc. (ASE)
Innovations in Wafer Bump Cleaning
Mike Bixenman, Eric Miller, Kyzen Corporation
Effects of Re-Finishing of Leads by Solder Dipping on Electronic Parts
Shirsho Sengupta, Diganta Das, Sanka Ganesan, Michael Pecht,
William Rollins, University of Maryland
WP4
Manufacturing II: Thin Substrates & Embedded Components
Chairs: Ken Kuang, Torrey Hills Technologies, LLC; Keith Easler,
Kyocera America Inc.
1:30 pm – 2:45 pm
As the density required for high functionality per unit volume increases,
methods to produce thin substrates and to embed passive elements within
the substrates provide a means to achieve this goal. This session focuses
on both of these areas, improvements in the manufacture of thin substrates,
and the technology of embedding passive devices in the substrate.
Design, Modeling and Measurement of Embedded Decoupling Capacitors
for Power Delivery in the Mid-Frequency Range
Prathap Muthana, Madhavan Swaminathan, Rao Tummala, Venkatesh
Sundaram, Lixi Wan, S.K Bhattacharya, P.M. Raj, Georgia Institute of
Technology
Embedded Capacitors using High-K Inorganic/Organic Composite Material
Noboru Asahi, Yoshitake Hara, Toshihisa Nonaka, Toray Industries,
Inc.
Development of an Enhanced Wafer Level Packaging Technology
Yogi Ranade, Stan Mihelcic, LSI Logic
WP5
LTCC Technology
Chairs: Ron J. Barnett, GeoMat Insights; John Menaugh, DuPont
Microcircuit Materials
1:30 pm – 2:45 pm
Ceramic based technology has been a solid choice over the years for
circuit functions demanding high performance and high density. LTCC
is no longer a novel technology practiced by a few suppliers. It is
now a reliable technology to manufacture high volume, high density structures.
This Session highlights innovative processing and technology advancements.
Improved Integration Density with Fine Line Conductors on Self-Constrained
Sintered LTCC
Annette Kipka, Quentin Reynolds, Andreas Henning, Stefan Malkmus,
Frieder Gora, Christina Modes, W.C. Heraeus GmbH
Unidirectional Cascade Sintering in LTCC Substrate
Yong-Bin Sun, Ju-Hwan Ahn, Jeong-In Choi, Jae-Yun Kim, Eui-Jyong
Choi, Kyonggi University
Co-fireable Overglaze for Zero X-Y Shrink LTCC Tapes
Weiming Zhang, Jim Wood, Peter Bokalo, Heraeus Incorporated-Circuit
Materials Division
WP6
Wirebonding (Gold)
Chairs: Lee Levine, Kulicke & Soffa Industries Inc.; Bruce Romenesko,
The Johns Hopkins University/APL
3:15 pm – 4:30 pm
Ultra fine pitch wire bonding (<50um
pitch) requires smaller ball bonds with smaller welded interfaces.
Development and reliability of
small ball bonds is the focus of this session.
The Effects of Wire Bond Parameters on Fine-Pitch Reliability
Matt Osborne, Lee Levine, Sr., Horst Clauberg, Kulicke & Soffa Industries
Inc.
Fine Pitch Wire Bonding for Automotive Requirements
Tu Anh Tran, Chu-Chung (Stephen) Lee, Nick Vo, Yuan Yuan, Freescale
Semiconductor
Thermal Bond Reliability of High Reliability Gold Alloy Wire for Automotive
ICs
Tomohiro Uno, Kohei Tatsumi, Keiichi Kimura, Nippon Steel Corporation
WP7
Power Packaging (Si and SiC)
Chairs: Doug Hopkins, University at Buffalo; Herb Dwyer, SATCON
Electronics
3:15 pm – 4:30 pm
Packing power into a small area has provided many challenges. Listen
how planar interconnect techniques can offer higher performance and
functionality for Si devices. Take the gloves off for very high power
density and drive SiC devices up to 300C. Listen to the latest in high
temperature packaging and interconnection metallurgy.
High Power Density Power Conversion using Polymer-Based Planar Power
Packaging
Raymond A. Fillion, Eladio Delgado, Rich Beaupre, Paul McConnelee,
GE Global Research Center
Integrated Packaging for a High Frequency Voltage Regulator Application
Zhenxian Liang, Yu Meng, Ming Xu, J. D. van Wyk, F. C. Lee,
Virginia Tech, CPES
Packaging of a High-Temperature Silicon Carbide (SiC) Mulitchip Power
Module (MCPM)
Jared M. Hornberger, Sharmila Mounce, Roberto Schupbach, Steven
Franks, Brice McPherson, Edgar Cilio, Alexander Lostetter, Arkansas
Power Electronics International, Inc.
WP8
Reliability II (Test Methods)
Chairs: Changhan Yun, Analog Devices Inc.; Harry K. Charles,
Jr., The Johns Hopkins University/APL
3:15 pm – 4:55 pm
This session on Reliability addresses failure mechanisms in both devices
and packages. There are presentations on the studies of the failure
mechanisms themselves, testing for failure and lifetime modeling. This
session focuses on the mechanisms and test methods.
Prediction of Board-Level Drop Reliability of Chip-Scale Packages with
Experimental Verifications
Chang-Lin Yeh, Chin-Li Kao, Yi-Shao Lai, Ping-Feng Yang, Advanced
Semiconductor Engineering, Inc.
Automated Three-Dimensional Digital Image Correlation Metrology of
FC-BGA First Level Interconnect In-Plane Deformation and Strain
Liam Kehoe, Patrick V. Kelly, Vincent Guénebaut, Patrick Lynch,
Optical Metrology Innovation
Influence of Extreme Temperature, Moisture and Vibration on Reliability
of Electronics
Parsaoran Hutapea, Teri-Lynn Allonardo, Branko Bogicevic, Temple
University
Characterization of Room Temperature Soldered Joints using Scanning
Acoustic Microscopy
Vidyu Challa, Sonix; Jai Subramanian, Jesse Newson, Reactive
NanoTechnologies
WP9
Substrate Advances in Packaging
Chairs: Warren Dyckman, IBM, Tim Mobley, Dupont Electronic
Technologies
3:15 pm – 4:30 pm
New and innovative substrate packaging technologies are continuously
being developed to keep up with market needs for increased performance,
reliability, miniaturization, and lower cost. This session looks at
some of the latest advances in microvia technology, fine line interconnects,
chip first strategies, elastomeric interconnect, high temperature ceramics,
and multilayer interconnect strategies. The relationship of these areas
is examined relative to system integration, reliability testing, and
performance.
Reliability of HITCE Ceramic Ball Grid Array Package
Rocky Shih, Sam Dai, Nelson Ramos, Hewlett Packard Company;
Lavanya Gopalakrishnan, Mason Hu, Ken Hubbard, Sue Teng, Cisco Systems
Inc.; Na Lee-Kim, Steve Bezuk, Ryuichi Imura, Kyocera America, Inc.
High I/O BGA Packaging using Chips First Build-Up
Raymond A. Fillion, GE Global Research Center
Micro Line Conductor Structuring using Electro-Hydrodynamic Printing
of Silver Nano Suspension
Dae-Young Lee, Eun-Soo Hwang, Yong-Jun Kim, Jungho Hwang, Yonsei
University
WA1 | WA2 | WA3 | WA4 | WA5 | WA6 | WA7 | WA8 | WA9 | WA10
WP1 | WP2 | WP3 | WP4 | WP5 | WP6 | WP7 | WP8 | WP9
Tuesday
Sessions | Thursday
Sessions
Register On-line
