IMAPS 2006 - PDC Descriptions

Professional Development Courses (PDCs)
All PDCs run 9:00 am - 5:00 pm, unless otherwise noted

PDC Lunch
Lunch on the day of your course only.

PDC Reception
Sunday, October 8th
5:00 pm - 6:00 pm
PDC Instructors and Attendees only.

Sunday, October 8

S1
Plating Processes for High Rel Microelectronic Devices
Course Leader: Fred Mueller, Consultant, ASEF Instructor

Course Description:
• Provide a thorough overview of the use of nickel, gold, and other precious metals that are electroplated for a variety of applications in the field of electronics;
• Present methods for conservation (and reuse) of precious metals, as well as pollution prevention and waste treatment methods;
• Understand the use of laboratory controls including the Hull Cell and other plating cells to test solutions;
• Highlight the engineering differences in plating processes.

Who Should Attend?
This course is intended as an introductory to intermediate level course for process engineers, quality engineers, and managers responsible for electronic finishing.

Mr. Mueller is a consultant and serves as a national certified instructor for the American Electroplaters and Surface Finishing Society (AESF). He has over twenty-five years experience in the plating industry in printed circuits and plating for electronics. He is currently the National Quality Manager at General Magnaplate, Linden, NJ. As a Chemist, Fred has conducted experiments and presented technical papers at SurFin on various topics in electroplating. He is very active in AESF, currently serving as First Vice President on the National Board. He is Chairman of the Quality in Surface Finishing Committee and the Electro-forming Committee of the AESF.

S2
RF/Microwave Hybrids: Principles, Materials and Processes
Course Leader: Richard Brown, Richard Brown Associates

Course Description:
Though widely used in the fields of telemetry, remote monitoring and remote process control, radio frequency (RF) and microwave (MW) circuits are primarily used today in the rapidly expanding wireless and automotive applications. To meet the demand for more features, smaller size and lower cost, the design of all electronic equipment keeps moving toward higher levels of integration. Another important driving force has been the explosive introduction of Surface Mount Technologies (SMT) in products such as the ubiquitous wireless phone. The ability to handle smaller size components and to place them with greater accuracy has shifted the manner in which many microwave circuits are currently being manufactured.

Coupled with the continuing development of monolithic integrated circuits, MMICs, are new materials and process refinement of hybrids. Clad material and LTCC technology are becoming more widespread. High dielectric materials, both in tape and fired substrate form, are rapidly emerging as a means of shrinking embedded and passive components. As a result, system and product designers are faced with the choice between hybrids and MMICs; i.e., complete system on a chip vs. hybrids with discrete devices, or more often, somewhere in-between.
High frequency circuits are perhaps unique in that impedance matching between components is critical for proper performance. As a result the proper choice of material and/or process is vital to achieve efficient, viable circuits. The challenge manufacturers face is to provide a product meeting strict electrical requirements from a wide spectrum of materials, each with its own set of manufacturing variables. Depending on the application, some combinations will be more appropriate than others. In some cases trade-offs may be necessary because of cost, capital requirements, space limitations, equipment limitations or even history with a given material or process. Depending on the final design requirements, the materials and processes the designer elects to use is of critical importance.

This course will begin with a short, non-mathematical review of high frequency basics. Next a comparison of MMICs and hybrids is presented. The transmission line as the basic circuit component of RF and microwave hybrids will be reviewed. Hybrid “waveguide” structures will be compared as they relate to transmission line properties. The basic materials (conductors, dielectrics and substrates) and their properties will be introduced. Their effect on impedance, circuit properties and performance will be discussed. Processing technologies suitable for RF/microwave hybrids will be reviewed. Selected packaging protocols, such as vias and bonding wires, will be discussed in light of their influence on RF/microwave performance. At the completion of this course, attendees will have a better understanding of many of the critical materials and processing factors affecting high frequency circuit performance.

Who Should Attend?
This introductory course will benefit those associated with the RF and microwave arena. The topics discussed in this course are important to help understand some of the issues that the material scientists face. In particular this course will benefit those with responsibility for design and manufacturing of RF/microwave hybrids. Supervisors, engineers and technicians involved in product development, sales, design and manufacture are encouraged to attend.

Special Course Materials:
All attendees will receive a complimentary copy of “RF/Microwave Hybrids: Basics, Materials and Processes,” by Richard Brown, Springer Publishers, 2002 (List Price $185).

Richard Brown is a technical and engineering consultant in hybrids, with more than 30 years experience, encompassing thin and thick film, electroplating and substrate technologies. He began his career at Bell Telephone Laboratories. After joining RCA Solid State in 1968, he transferred in 1979 to the RCA Microwave Technology Center in Princeton. In 1991, Mr. Brown joined an Alcoa Electronic Packaging technology team as program manager to implement thin film on high temperature co-fired ceramic for MCMs.

He has published extensively, authoring a chapter on Thin Film for Microwave Hybrids in “Handbook of Thin Film Technology,” McGraw-Hill, NY, 1998, A. Elshabini-Riad, Ed. In 1995, ISHM awarded him the prestigious John A. Wagnon, Jr. Technical Achievement Award. His text, “Materials and Processes for Microwave Hybrids” was published in 1991 by ISHM, Reston, VA., and most recently, RF/Microwave Hybrids; Basics, Materials and Processes, Kluwer Academic Press, 2002.

S3
Practical Electronics Reliability – An Overview
Course Leader: Andrew D. Kostic, Ph.D.

Course Description:
The student will learn basic principles of electronic reliability testing and measurement.

The class begins with an introduction and explanation of terms and concepts. After basic definitions have been established, the student will learn basic information about failure distributions, component reliability, system reliability, Environmental Stress Screening (ESS) and their applications.

The presentation uses actual examples of issues encountered to help guide the student and provide a reference for when they return to their own company.

Students will receive a softcopy of the presentation along with simple Microsoft Excel reliability software tools that are demonstrated during the class. Students are encouraged to bring along laptop computers to use during class exercises.

Who Should Attend?
This course is a “must” for Reliability engineers, Quality engineers, Manufacturing engineers, Sales & Marketing personnel, Reliability technicians, and anyone who wants to gain a basic understanding of electronic reliability.

Dr. Kostic has been intimately involved in the fields of electronics product quality and reliability for over 30 years. He has extensive experience with both semiconductor and system manufacturing. Andy is an Engineering Fellow in the Product Integrity department of Northrop Grumman Electronic Systems. He has held senior technical leadership positions in the Unisys Component Engineering Procurement Organization, IBM Global Procurement Quality Engineering, and IBM Microelectronics Corporate Quality. He has taught quality and reliability improvement classes all over the world since 1988 which have been highly praised by his students as being effective and practical. Dr. Kostic has been a successful consultant in the electronics industry. His advice has enabled companies to improve their field reliability dramatically with small investments. Dr. Kostic has an extensive background in reliability that includes:

• Reliability modeling and prediction
• Supplier evaluation
• Electrical characterization
• Incoming inspection
• FRACAS
• Failure analysis
• Environmental Stress Screening
• Supplier qualification and management
• Component qualification
• Lead-free electronics

Dr. Kostic holds the B. Sc. and M. Sc. degrees in Physics and a Ph. D. in Engineering. He has over twenty-five publications in the field of quality and reliability and is the Northrop Grumman representative to JEDEC Solid State Products Quality and Reliability Committee.

S4
Technology of Screen Printing
Course Leaders: Art Dobie, SEFAR Printing Solutions, Inc. & Rudy Bacher, Consultant

Course Description:
Screen printing continues to have innovative solutions to the increasing demands for higher circuit densities. This course is intended to increase the understanding of the screen printing process thereby improving production yield and print quality. Presented are some of the latest advancements in composition, screens, and printing technology that enable screen printing to meet future circuit density requirements as well as the definition required for microwave circuitry. The advantages of screen printing, an additive deposition process, are described, and the cost and environmental advantages of “advanced screen printing” compared to other subtractive deposition technologies will be discussed.

The course is applications-oriented in terms of how to optimize the screen printing process; how to properly specify screen parameters and use screens correctly; rheology properties that affect the print results; minimizing printing defects and trouble-shooting problems related to the screen and the printing process.

Who should attend?
This course is intended for production and process engineers, and others interested in learning how to optimize and increase the uses of the screen printing process.

Art Dobie is Manager of Screen Technology for SEFAR Printing Solutions headquartered in Lumberton, NJ. He has been with SEFAR over 24 years since receiving his BS in Graphic Communications (specializing in Screen Printing Technology) in 1980 from California University of Pennsylvania’s School of Science & Technology.

Art has instructed the Technology of Screen Printing Professional Development Course for IMAPS (International Microelectronics And Packaging Society) since its inception in 1991. Over the past twenty-four years, he has delivered many technical papers and presentations relating to screens and screen-printing technology to both microelectronic and screen printing professionals at local, national and international levels.

Art is a Fellow of the Society of IMAPS, and has held numerous offices within the society, including president and vice-president of the Keystone Chapter. He was also Exhibits Co-Chair for IMAPS 2005, after having served in the same capacity for ISHM ‘97.

On October 7, 1998, Art Dobie was inducted into the Academy of Screen Printing Technology (ASPT) of the SGIA, and was also selected to the ASPT’s Technical Review Committee. The ASPT represents the highest level of technological expertise in the screen printing industry. Recognized authorities in their field, Academy members are chosen on the basis of their demonstrated ability and willingness to assist in the betterment of the industry.

Rudy Bacher has worked 43 years in Thick Film Technology for DuPont Research and Development as a Senior Development Associate. Retired in 2004, he currently is a consultant for Dynamesh, the US division of NBC, Japan. He was a recipient of the ISHM Technical Achievement Award in 1984; DuPont Corporate Marketing Excellence Award-1994 and Accomplishment Awards for thick film compositions for high yield fine line printing. Received 8 patents and has been an IMAPS Instructor, “Technology of Screen Printing,” 1990 - 2005.

S5
Application of Nanomanufacturing for Microelectronics and Related Microsystems Packaging
Course Leader: Ajay P. Malshe, Ph.D., University of Arkansas

Course Description:
Nanomanufacturing is a science and engineering of the fabrication and assembly of nano elements into nanostructures, devices, and systems, and integration into larger scale structures (ex. microelectronics and microsystems) such that both heterogeneity and scalability is possible. Nanomanufacturing science and engineering especially addresses synthesis of nano materials (particles, molecules, quantum dots, etc.), tools and systems for reproducible nano manipulation and post-synthesis processing (self and/or directional), integration and packaging, addressing component reliability and system durability, and addressing “application specific” scientific and engineering designing-to-processing issues.

This globally taught course will address silicon, carbon, BaTiO3 like ceramics and other nanoelements fabrication processes, unique properties of nanoelements, their self as well as directed assemblies and integration in microelectronics and microsystems for advanced functionality. The course will elaborate the theme of this PDC through leading examples such as nanoparticle filled epoxies for durable assembly, nanoparticle filled integrated passive capacitors, organic molecular assembly for devices, integration of carbon nanotube (CNT) based devices and their interconnection to traditional electronic devices and heterogeneous systems.

This course will be very vital for business leaders to understand how this new frontier of manufacturing can immediately benefit them and their organizations to be leaders in the global market. Various application areas include, wireless communication, optical devices, homeland security, harsh electronics, etc.

Who Should Attend?
The course is specifically meant for industry and academic leaders and investors in science and engineering with interest in nano and nano-integrated micro systems. Highly recommended for R&D scientists, engineers and managers involved in sensors, actuators, instrumentation and systems related to micro and nano systems technology. Graduate students with special interest in the above areas will also find it useful.

Ajay P. Malshe is a Professor of Mechanical Engineering and adjunct-faculty of Electrical Engineering at the University of Arkansas. He is Director of the Materials and Manufacturing Research Laboratories. He is a Fellow of The Institute of Physics (IOP). He is a Materials Scientist and Engineer. Malshe has multidisciplinary research programs in Nanomanufacturing, MEMS and microelectronic packaging and integration, and surface engineering for advanced machining. He has authored over one hundred and twenty five refereed publications, three book chapters, and holds six patents. He has initiated the development of nano-mechanical machining system-on-a-chip, nano-particle composite coatings, wafer level chip scale packaging of MEMS and related microsystems, femtosecond laser for chemically clean machining. He has graduated over twenty-five students, trained numerous post-doctoral fellows, and provided research experience to several undergraduate and high school students. He has received fifteen awards for research, education and service achievements (1996-2006) and is listed in Lexinton’s Who’s Who. He has an extensive record of global collaborations with academic institutions and companies, and has co-founded and been CTO of two companies in the nano and micro technology sectors in the state of Arkansas.

S6
Introduction to Microelectronics Packaging Technology
Course Leader: Phillip Creter, Creter & Associates

Course Description:
This continuously updated course will provide an introduction to microelectronics packaging technology to entry-level engineers and technicians and others involved in manufacturing, processing, development, quality, sales and marketing. No prior knowledge of microelectronics is required. Emphasis will be on visual aids including actual samples passed among students; a variety of photos and figures provide the attendee with not only a solid base in how various microcircuits are made by various materials, processes and equipment, but also what they physically look like.

The attendee will learn basic definitions as well as advanced terminology of materials, processes and equipment, including: thick film technology, thin film technology and monolithic semiconductor nano technology; substrates (ceramic, conductors, dielectrics, co-fired, LTCC); components (passives, actives, chips vs. discrete SMT components and flip chip); assembly including details of die attach, wire bonding and micro soldering, rework & repair; final assembly including details of visual inspection techniques, test, failure analysis and important elements of reliability. Variations of QFP, QFN, BGA, WLP, FC, CSP and 3D stacked die will be reviewed. The tutorial will also cover documentation standards. Also covered is design, acronyms, clean rooms and handling techniques. Video clips will highlight various traditional assembly processes and new developments in wafer thinning, jet underfilling, laser dicing, and high speed assembly.

Included in the 200-page course handout is an updated glossary and list of references the attendee will find invaluable.

Who Should Attend?
This course is designed to provide an overall perspective to entry level engineers as well as provide an update in technology developments to more experienced engineers new to the field of packaging; also ideal for non-technical people in quality assurance, sales, marketing, purchasing, safety, administration and program management. The course relies upon a comprehensive set of class notes with an emphasis on visual aids including many photos, figures, video clips and actual physical samples of various microcircuits. No prior knowledge of microelectronics is required since this course is designed primarily for the student who has little initial familiarity with Microelectronics Packaging engineering terminology but would like to relate it to real life, everyday applications. The course uses simple terms for ease of understanding yet includes aspects of advanced packaging for senior engineers new to the field and needing a running start in packaging technology.

Phil Creter has over 30 years of microelectronics packaging experience and is a long-time member of IMAPS, having joined the New England Chapter of ISHM in 1974. He is a Fellow of the Society, and has been elected National Treasurer and President of the New England Chapter (twice). He received a BS in Chemistry from Suffolk University and has published numerous papers, holds a U.S. patent, has made many technical presentations (received Best Paper of Session award IMAPS 1998) and has chaired several technical sessions for symposia. He is currently a consultant (Creter & Associates) with 30 years of microelectronics packaging experience at Polymer Flip Chip Corporation, Mini-Systems, GTE and Itek Corporation. His past positions include GTE Microelectronics Center Manager, Process Engineering Manager, Process Development Manager, Materials Engineering Manager and Manufacturing Engineer.

Phil currently teaches professional development courses at microelectronics events and is a certified active instructor for the Department of Homeland Security.

1/2 Day Course: 9:00 am - Noon
S7
Lead-Free Reliability & Manufacturing
Course Leader: Dr. Jennie Hwang, H-Technologies Group, Inc.

Course Description:
The course is designed to integrate the manufacturing know-how and the resulting solder joint reliability, based on three books: “Environment-Friendly Electronics: Lead Free Technology;” “Lead-free Implementation: A Manufacturing Guide;” and “Modern Solder Technology for Competitive Electronics Manufacturing.” The objective is to provide a proper level of understanding of Pb-Free solder interconnection reliability in material basics, production process, and real-world performance, as well as the interrelation between them. The main factors affecting the reliability from manufacturing perspectives will be presented. The effects of gold, intermetallics and the estimation of gold threshold concentration in relation to reliability will be discussed. Tin whisker will also be discussed. Information is applicable to all types of interconnections including fine pitch QFP, BGA, flip chip, CSP, and passive components.

Topics
• Industry trends vs. solder joint reliability
• Solder joint vs. bulk solder
• Factors affecting reliability
  --Alloy selection
  --Substrate compatibility
  --Gold effects and threshold estimate
  --Intermetallics sources and effects
  --Effects of component coating
  --Effects of PCB surface finish
  --Effects of solder mask
  --Effects of reflow process
  --Microstructure & interface
  --Service conditions
• Options of Pb-Free solder paste alloys, solder spheres, component coating, PCB surface finish
• Examples of temp. cycling of Pb-Free solder joints
  --temp cycling conditions
  --temp cycling condition differentiating the properties of solder joint integrity
• Tin whisker phenomena, factors, mitigation techniques
• Basic failure processes
• Fundamental alloy behavior vs. temperature including Pb-free technology
• Reliability factors of BGA/CSP array solder joints
• Reliability factors of QFP solder joints
• Concluding points

Who should attend?
This course provides a working knowledge to all who are involved with or interested in environment-friendly Pb-Free electronic packaging and assembling through a broad-based understanding of materials, processes, production implementation and factors affecting reliability.

Special Course Material:
All attendees will receive a complimentary copy of “Lead-Free Implementation: A Manufacturing Guide,” by Jennie Hwang, McGraw-Hill, NY, 2004 (List price $100).

Dr. Hwang brings her 26-year SMT manufacturing experience combined with her 16-year lead-free R&D and production implementation to this course. She has been a major contributor to the Surface Mount Technology since its inception. She has provided hands-on solutions to many challenging production problems and is also an advisor to major OEMs, EMSs and government including DoD F-22 project. She received Ph.D., M.S., M.A. B.S degrees in Materials Science & Engineering, Physical Chemistry, Liquid Crystal Science, Chemistry, respectively. Among her many honors and awards are citations by the U.S. Congress for her outstanding achievements; election to the National Academy of Engineering; induction into the WIT International Hall of Fame; recipient of YWCA Women of Achievement Award; and being named “R&D-Stars-to-Watch” by Industry Week. She is also the recipient of Distinguished Alumni Awards from her alma maters. Being a popular lecturer/keynote speaker worldwide and the holder of a number of patents, Dr. Hwang is the author of over 300 publications, including the sole authorship of six textbooks. She is also a prolific author on the topic of trade, business, education and social issues. Dr. Hwang has served on the board of NYSE Fortune 500 companies, and various civic and university boards, including Ferro Corporation, Case Western Reserve University, Second National Bank, US Commerce Department’s Export Council. Having held senior executive positions with Lockheed Martin, SCM Corp., Sherwin William Co., IEM Corp., currently she is a principal of H-Technologies Group Inc., providing technology and business solutions to the electronics industry. She is also an invited distinguished adjunct professor with the Engineering School of Case Western Reserve University.

1/2 Day Course: 1:00 pm - 5:00 pm
S8
Six Sigma Applications in Microelectronics Packaging
Course Leader: Thomas J. Green, Microelectronics Packaging Consultant; TJ Green Associates LLC

Course Description:
Six Sigma is a philosophy of doing business that focuses on defect prevention and process improvements rather than simple detection after the fact. Methodologies such as process mapping, pareto charts, statistical process control (SPC) and design of experiments (DOE) along with the associated cost reductions and yield improvements form the cornerstone of the Six Sigma approach. This half day tutorial will focus on how these techniques can be effectively applied in packaging and assembly of microelectronic components. Actual case studies from the manufacturing floor will be used to illustrate how Six Sigma can be employed to improve process yields, speed throughput and reduce costs. Thick film, stencil printing, thin film, die bond, wirebond, plating and package seal are all prime processes for the application of statistical techniques and Six Sigma methodologies. A background and training in statistics is not enough. It’s the combination of statistical methods, plus a basic understanding of the materials and process that can produce breakthrough results. This course attempts to educate and enlighten the student by illustrating this important relationship.

After a cursory review of the relevant six sigma principles the instructor will walk through several packaging related Design of Experiments (DOEs) emphasizing the rationale for factor settings, matrix selection, graphical analysis and process optimization. Other six sigma techniques will also be illustrated using relevant industry data sets. The course will examine some of the pitfalls and difficulties applying Six Sigma along with the successes.

Who Should Attend?
The course is important for process and quality engineers, technical managers, and technicians interested in learning how to apply Six Sigma statistical techniques in the microelectronics manufacturing industry. The attendee is assumed to have some basic understanding of statistical methods and graphical analysis and is interested in some practical applications and industry case studies.

Mr. Green is a respected industry consultant and Adjunct Professor at the National Training Center for Microelectronics. As a consultant he has considerable experience in die bond, wirebond and package seal and has conducted and analyzed numerous statistically designed experiments (DOEs), which increased first past yield, reduced costs and improved product quality. At NTCm he designs curriculum and teaches industry short courses relating to advanced microelectronics manufacturing processes. He has over twenty years experience in the microelectronics industry at Lockheed Martin Astro Space and USAF Rome Laboratories. At Lockheed he was a Staff engineer responsible for the materials and manufacturing processes used in building custom high reliability space qualified microcircuits (Hybrids, MCMs and RF modules) for military and commercial communication satellites. He has presented technical papers at NIST and IMAPS on leak testing techniques and optimization of seam welding processes through statistical DOE methods. At Rome Labs he worked as a senior reliability engineer and analyzed component failures from AF avionic equipment along with providing technical support for a variety of Mil specs and standards (e.g. MIL-PRF-38534 and MIL-STD-883). Tom is an active member of IMAPS and a Society Fellow. He has a B.S. in Materials Engineering from Lehigh University and a Masters from the University of Utah.

PDC Lunch
Lunch on the day of your course only.

PDC Reception
Sunday, October 8th
5:00 pm - 6:00 pm
PDC Instructors and Attendees only.

Monday, October 9

M1
Wire Bonding in Microelectronics
Course Leader: George G. Harman, National Institute of Standards and Technology

Course Description:
Wire bond manufacturing defects range typically from about 1000 to 100 ppm, with exceptions to >10,000 and <50 ppm. In order to achieve the lower numbers in production, one must understand all of the conditions that affect both bond yield and reliability (since they are interrelated). This course will discuss many large- and small-wire bonding problems, as well as subjects of specific interest to hybrid/MCM device bonding. In addition, a number of advanced topics, such as high yield, fine pitch (towards 20 micron pitch), and bonding to flex will be covered. Newer developments (e.g., high frequency ultrasonic bonding) are included along with a major discussion of wire bonding to multichip modules and other soft substrates. Wire bond testing and metallurgy (covering both aluminum and gold bonds); intermetallic compounds; cleaning for yield and reliability; failures resulting from electroplating; mechanical problems in wire bonding; new bond technologies and developments; how ultrasonic bonds are formed, and the metallurgy of gold and aluminum wire. It concludes with methods of implementing TAB and Flip Chip by using wire bonding techniques.

Who should attend?
Engineers in R&D, QA, QC, manufacturing, process development, and advanced technicians. It is assumed that participants have some familiarity with wire bonding and general device assembly technologies.

Special Course Materials:
All attendees will receive a complimentary copy of “Wire Bonding in Microelectronics,” by George Harman, McGraw Hill, NY, 1997 (List price $65).

Mr. Harman is a Fellow Emeritus of the National Institute of Standards and Technology (NIST), and a consultant. He received a BS in Physics from Virginia Polytechnic Institute & State University and a MS in Physics from the University of Maryland. Mr. Harman has published over 60 papers, two books on wire bonding, and holds four U.S. Patents. He was the 1995 President of ISHM and is a Fellow of IMAPS and the IEEE. He has received numerous awards for his work from IMAPS, IEEE, DVS and others. He has presented numerous talks, and has taught courses for the University of Arizona and IMAPS for over 15 years, as well as the IEEE, to name a few. He has presented many papers and given courses in the USA, Europe, and Asia.

M2
Advanced Thermal Management and Packaging Materials
Course Leader: Dr. Carl Zweben, Advanced Thermal Materials Consultant

Course Description:
Advanced thermal materials can help solve two of the most critical packaging problems: thermal management and delamination/fracture of Copper/Low-k (Cu/Low-k) ICs. The key causes of the latter are thermal stresses arising from differences in coefficient of thermal expansion (CTE) of the IC and substrate. Use of lead-free solders, which have higher processing temperatures, increases thermal stresses, intensifying the problem. In response to these critical needs, there have been revolutionary advances in thermal management and packaging materials in the last few years. There are now over 15 low-CTE, low-density materials with thermal conductivities ranging between that of copper (400 W/m-K) and 1700 W/m-K, and many others with lower conductivities. Some are low cost. Others have the potential to be low cost in high-volume. Carbon fiber-reinforced epoxy constraining layers can tailor substrate and PCB CTE to match that of silicon, potentially eliminating the need for underfill. They also can increase thermal conductivity significantly, allowing heat removal from the bottom, as well as the top of a chip. Advanced materials also will be increasingly important for 3D packages as heat loads increase. Low-CTE solders under development will provide additional advantages.

Current production systems include servers, laptops, cellular telephone base stations, hybrid electric vehicles, traction motor controls, aerospace power systems, phased array antennas, and a variety of optoelectronic products, such as telecommunication equipment and plasma displays. Components include substrates, PCBs, PCB cold plates/heat spreaders, heat sinks, thermal interface materials (TIMs), microelectronic packages, RF packages, power modules, thermoelectric cooler modules, and laser diode and LED packages. For example, IBM has used diamond particle-reinforced silicon carbide server heat spreaders that have a thermal conductivity of over 600 W/m-K.

Advanced material payoffs include:

• increased reliability
• reduced thermal stresses and warpage
• potential elimination of underfill
• simplified thermal design
• reduction/elimination of fans, heat pipes, liquid cooling and refrigeration
• reduced weight and size
• reduce cooling power requirements
• increased battery life
• increased stiffness and strength
• enablement of hard solders by minimizing CTE mismatches
• increased manufacturing yield
• reduced system cost

This course covers the large and increasing number of advanced thermal management and packaging materials, providing an in-depth discussion of properties, manufacturing processes, applications, cost, lessons learned, typical development programs, and future directions, including carbon nanotubes. Traditional materials are discussed for reference. Participants are invited to bring their thermal management problems for discussion.

Who Should Attend?
Engineers, scientists and managers involved in microelectronic, optoelectronic and MEMS/MOEMS packaging design, production and R&D; packaging material suppliers.

Dr. Zweben, now an independent consultant, directed development and application of advanced thermal management and packaging materials for over 30 years. He was formerly Advanced Technology Manager and Division Fellow at GE Astro Space, where he directed the Composites Center of Excellence, and was the first to use Al/SiC. Other affiliations have included Du Pont, Jet Propulsion Laboratory and the Georgia Institute of Technology NSF Packaging Research Center. Dr. Zweben was the first, and one of only two winners of both the GE One-in-a-Thousand and Engineer-of-the-Year awards.

He is a Life Fellow of ASME, a Fellow of ASM and SAMPE, an Associate Fellow of AIAA, and has been a Distinguished Lecturer for AIAA and ASME. He has published and lectured widely on advanced thermal management and packaging materials.

M3
Low Temperature Co-fired Ceramics (LTCC)
Course Leaders: Aicha Elshabini, University of Idaho & Fred D. Barlow, University of Arkansas

Course Description:
This course focuses on the materials, processes, design, and applications of Low Temperature Co-fired Ceramics (LTCC). The course will begin with a brief history and background of the technology. A detailed discussion of the process flow and processes will cover each step used in the fabrication of LTCC substrates. A discussion of the material properties and design guidelines and considerations will also be covered in detail. Finally, a discussion of the technical advances and the technical applications of the technology will outline the relative strengths of LTCC for a number of target markets.

Topics:
• History of LTCC and Background
• LTCC Process
• Material Properties
• Design Considerations
• Technical Advances
• Applications

Who should attend?
Engineers, managers, and technicians, who desire to expand their background or strengthen their understanding of the technology. The course will not assume any prerequisite background.

Aicha Elshabini is Professor of Electrical and Computer Engineering and the Dean of Engineering at University of Idaho. She obtained a B.Sc. in Electrical Engineering at Cairo University, 1973, in both Electronics and Communications areas, a Masters in Electrical Engineering at University of Toledo, 1975, in Microelectronics, and a Ph.D. Degree in Electrical Engineering at the University of Colorado, 1978 in Semiconductor Devices and Microelectronics. She has served as a faculty member at Virginia Tech in the period 1979-1999. She has served in the position of Professor and Department Head for the Electrical Engineering Department at University of Arkansas (1999-2006), and Interim Department Head for Computer Science & Computer Engineering Department (2000-2003). She has been serving as the faculty advisor for the IMAPS student program at both Virginia Tech and University of Arkansas institutions from 1980 to 2006. Elshabini is a Fellow of IEEE/CPMT Society (1993) Citation for ‘Contribution to Hybrid Microelectronics Education and to Hybrid Microelectronics to Microwave Applications,’ a Fellow of IMAPS Society (1993), The International Microelectronics And Packaging Society, Citation for ‘Continuous Contribution to Microelectronics and Microelectronics Industries for numerous years.’ Dr. Elshabini was awarded the 1996 John A. Wagnon Jr., Technical Achievement Award from IMAPS. She has served as the Founding Editor of the IMAPS International Journal of Microcircuits & Electronic Packaging for 10 years.

Fred Barlow earned a Bachelors of Science in Physics and Applied Physics from Emory University, a Masters of Science in Electrical Engineering from Virginia Tech, and a Ph.D. in Electrical Engineering from Virginia Tech. Dr. Barlow has published widely on electronic packaging and electronic materials evaluation and is Co-Editor of “The Handbook of Thin Film Technology” (McGraw Hill, 1998). In addition, he has written several book chapters including two chapters on thin films and one on components and devices. He has achieved the Outstanding Contribution Award with IMAPS in recognition of his efforts in developing and implementing the CD-ROM project for IMAPS publications, IMAPS home page on the Internet, and for his technical contributions. His research interests include electronic packaging for power electronic and microwave applications as well as RF and microwave design.

M4
Hermeticity Testing, RGA and “Near Hermetic” Packaging Concepts
Course Leader: Thomas J. Green, Microelectronics Packaging Consultant; TJ Green Associates LLC

Course Description:
Hermeticity of electronics packages and hermeticity test techniques continue to be of critical importance to the microelectronics packaging community. Specifically, in the area of MEMS/MOEMS packaging, OLEDs, wafer scale packaging, optoelectronic devices and packaging for Military and Space. In addition, there are a host of medical implants, bio medical devices and emerging nanotechnology applications that all require hermetic packages and valid techniques to measure the leak rate. In contrast to a hermetic cavity style package “near hermetic” packages are being developed that rely on polymeric materials, such as LCP, to make a package that provides just enough moisture protection to survive in the intended end user environment.

This course begins with an overview of hermetic sealing processes. The class will then examine the accepted leak test techniques as prescribed in Mil Standard 883 Test Method 1014. This misunderstood test method is often a source of frustration. The basic science behind helium fine leak testing (both the fixed and flexible methods) will be presented. Difficulties and limitations in fine leak testing of small volume packages is a major industry concern; especially among the Space community. Issues with bomb times and pressures, measured leak rate vs air leak rates, “one way leakers,” virtual leakers will be addressed, along with gross leak testing; bubble, weight gain etc. In each case the focus will be on practical issues facing the industry.

The latest technique for measuring both gross and fine leak testing is Optical Leak Test (OLT). In this method a laser interferometer measures out of plane deflection on a lid surface in response to a changing pressure and relates these measurements to an equivalent helium leak rate. For some packages (e.g. MEMS and OPTO devices) OLT is the only available viable technique.

The ultimate goal is to seal the sensitive microelectronic component in a dry, inert atmosphere to allow reliable functioning of the device over its intended lifetime. The gas ambient inside the package is measured using Residual Gas Analysis. What is RGA (Residual Gas Analysis)? How does it relate to hermeticity testing? Is the current 5,000 PPM level valid for next generation MEMS/MOEMS and Nanotechnology. Besides moisture what other gases are of concern?

Packages made from polymeric materials as opposed to traditional hermetic seals (i.e. metal, ceramic etc) require a different approach from a testing standpoint. The problem is now one of moisture diffusion through the barrier and package interfaces. A brief review of the techniques and methods to evaluate a “non-hermetic” approach is presented.

Special Course Material:
All attendees will receive a complimentary copy of “Hermeticity of Electronic Packages,” by Hal Greenhouse, Noyes Publications, 2000 (List price $167); and a “Practical Guide to TM 1014” authored by the Instructor.

Who Should Attend?
This PDC is intended as an introductory to intermediate level course for process engineers, designers, quality engineers, and managers responsible for sealing, leak testing and RGA results and for those responsible for evaluating new cavity style packages.

Mr. Green is a consultant and adjunct professor at the National Training Center for Microelectronics. As a consultant he has considerable experience in die bond, wirebond and package seal. At NTCm he designs curriculum and teaches industry short courses relating to advanced microelectronics manufacturing processes. He has over twenty years experience in the microelectronics industry at Lockheed Martin Astro Space and USAF Rome Laboratories. At Lockheed he was a Staff engineer responsible for the materials and manufacturing processes used in building custom high reliability space qualified microcircuits (Hybrids, MCMs and RF modules) for military and commercial communication satellites. He has conducted experiments and presented technical papers at NIST and IMAPS on leak testing techniques and optimization of seam welding processes through statistical DOE methods. At Rome Labs he worked as a senior reliability engineer and analyzed component failures from AF avionic equipment along with providing technical support for a variety of Mil specs and standards (e.g. MIL-PRF-38534 and MIL-STD-883). Tom is an active member of IMAPS. He has a B.S. in Materials Engineering from Lehigh University and a Masters from the University of Utah.

M5
Adhesion Fundamentals in Microelectronic Packaging
Course Leader: Raymond A. Pearson, Lehigh University

Course Description:
Polymers are widely used in electronic packaging. The lack of adhesion can adversely affect reliability as well as package performance. The intention of this course is to review the fundamentals of adhesion and apply them to interfaces found in Plastic-Quad Flat Packs (PQFP), chip-scale packages (CSP), Flip-Chip (FC) assemblies, and optoelectronic packages. Adhesion issues in molding compounds, die attach adhesives, optoelectronic adhesives, and underfill resins will be covered. By the end of the course, you should know how to choose the proper tools to predict and measure adhesion.

COURSE OUTLINE:
1) Discuss Course Objectives
2) Review Microelectronic and Optoelectronic Packages (Brief)
3) Discuss the Role of Chemical Forces in Adhesion
4) Examine Extrinsic Deformation Mechanisms in Polymers
5) Review Common Tests to Assess Adhesion
6) Evaluate procedures used to form adhesive bonds
7) Apply Interfacial Fracture Toughness Concepts to Gage Reliability

Who should attend?
Engineers, scientists and managers involved in the design, process and manufacturing of IC electronic components and hybrid packaging, electronic material suppliers involved in materials manufacturing and research & development.

Special Course Material:
All attendees will receive a complimentary copy of “Adhesives Technology for Electronic Applications: Materials, Processing, Reliability,” by James J. Licari and Dale W. Swanson, William Andrew Publishing, 2005 (List price $165).

Dr. Raymond A. Pearson joined the Materials Science and Engineering Department at Lehigh University in August of 1990 after obtaining his doctorate in Materials Science and Engineering from University of Michigan. Prior to graduate school, Ray had worked for seven years with General Electric Company: from 1980-1984 as an associate staff member at GE’s Corporate Research and Development Center in Schenectady, New York and from 1984-1987 as a materials specialist at GEPE’s Product Technology Center in Bergen op Zoom, the Netherlands. His research interests include all aspects of processing, deformation, yield, and fracture of polymers. He has worked extensively in the area of fracture mechanisms and adhesion. He has worked closely with organizations such as the Semiconductor Research Corporation and SEMATECH.

M6
Introduction to Integrated Circuit Packaging, Assembly, and Interconnections
Course Leader: William J. Greig, Greig Associates

Course Description:
This course provides an overview of electronics/microelectronics manufacturing and addresses the impact of both the Integrated Circuit and End Product requirements for “smaller, better, cheaper.” It covers IC packaging, chip assembly, and HDI packages and substrates. It focuses on packaging trends, in particular area array, the BGA, the CSP, and the Flip Chip and its counterpart the Wafer Level CSP. It includes discussions on the advantages of alternative packaging options including multichip packaging (MCP), and Chip On Board (COB). Additionally emerging 3-D packaging initiatives rapidly entering mainstream are examined at both the chip and package levels, i.e., both die and package stacking.

High Density Interconnect (HDI) package/substrate manufacturing process technologies are reviewed including Thin Film, Thick Film and Co-fired Ceramic that support Level 1.0 SCP and MCP, and Level 2.0 PWBs. Significant developments in the PWB process technology are presented including Build Up Technology (BUT) that offers increased wiring density, fine lines and spaces, and microvias.

Throughout the course the technical issues will be emphasized and reliability concerns addressed where appropriate.

Who Should Attend?
The course is effectively a primer covering primarily the microelectronic packaging arena. It is intended for a variety of individuals, technical and non-technical, whether directly or indirectly involved with electronic product manufacturing. It will serve as a review of current and emerging technologies for the experienced engineer and technician or as an introduction for anyone new to the industry. It should be of special interest to materials and equipment suppliers and those in support activities such as, procurement, quality assurance, marketing and sales, by providing an adequate technology base to assist in evaluating, planning or implementing.

Special Course Material:
All attendees will receive a complimentary copy of “Hybrid Microcircuit Technology Handbook,” by James J. Licari and Leonard R. Enlow, Noyes Publications, 1998 (List Price $155).

Bill Greig is currently an independent consultant specializing in microelectronic packaging and assembly. His previous work experiences include RCA Semiconductor, General Electric Co., Lockheed Electronics, and contract consultant to NASA. His areas of expertise covers semiconductor wafer processing and assembly, hybrid circuit manufacture, and printed wiring board fabrication. He has been granted 6 patents and has published or presented numerous papers at various technical symposia. He has presented courses at various national symposia and participated in CEE programs at U. of Wisconsin, Lehigh University and Rutgers University. He is a member of SMTA and IMAPS in which he is a Fellow, and Past President of the Garden State Chapter.

1/2 Day Course: 9 am - Noon
M7
Biomedical Materials, Devices and Packaging
Course Leader: Z. Joan Delalic, PhD, Temple University

Course Description:
The basic objective of this workshop is to provide material to professional engineers and scientists who will be working in design and packaging of medical devices and in the manufacturing of these devices. This course material will provide informative information in material science, design packaging and manufacturing of biomedical devices.

Today’s medical professional environment requires perfection from equipment and other medical devices. The function, method of use and design of medical devices must always be correct. The design process, packaging and material selection are key success factors in ensuring that the product is correctly manufactured and perform at standards required by biomedical applications.

Biomedical engineering is divided into multiple components including large equipment for diagnostic purposes, smaller portable equipment for home/hospital use, sensors and MEMS/NEMS to measure and/or enhance specific body function. Recent developments in high power microscopy are allowing the development of implantable micro/nano devices. Twenty-first century engineering will evolve into the development of new materials, new methods of packaging, defining the biocompatible packaging, and experimenting with new materials to produce biocompatible devices. Specifically, these devices are going to be in the area of implantable biomeasuring devices, drug delivery devices, micro/nano under the skin monitoring devices, etc.

The materials used for packaging biomedical devices, specifically implantable ones, must address issues in the selection of proper bio-materials from biocompatibility to bio-stability to structure/function relationships. The focus is on the use of specific biomaterials based on their physiochemical and mechanical characterizations. Major types of biomaterials for packaging implantable devices will be discussed. Implantable devices such as different mechanical pumps for drug delivery at a constant rate over a prolonged period as well as different types of biosensors will also be discussed.

A large number of studies are being conducted in numerous laboratories to develop nanoscale bio-structures. These structures can mimic or affect a biological process or interact with a biological entity. The structures include numerous micro/nano scale sensors that work using physical properties of bulk materials via complex mechanical and electronic apparatus. In engineering they are defined as MEMS/NEMS.

A common problem with implantable devices is allergic reaction in the biological medium. To avoid the bi-response, these sensors, MEMS/NEMS, are using bio-compatible materials as well as packaging these devices in the appropriate shape and size.

The ultimate goal for this PDC is to introduce a novel approach in designing, packaging, and defining bio-compatible materials for bio-devices used as implantable, monitoring, and replacement of bio-parts devices, MEMS/NEMS, etc.

Who Should Attend?
This PDC course is intended as an introductory to intermediate level course for packaging engineers, designers, materials engineers, and engineering managers.

Dr. Z. Joan Delalic is a Professor in the Department of Electrical/Computer Engineering, Temple University. She has a BS and MS in Electrical Engineering and a PhD in Bioelectronics. She is currently involved in Biomedical and Nanotechnology research. Her involvement in biomedical research involves different types of implantable sensors for measuring various biological functions. Her nanotechnology research involves the development of the implantable structures for drug delivery to tumors.

1/2 Day Course: 1:00 pm - 5:00 pm
M8
Guide to Component Chip Attach - Including Flip Chip
Course Leader: Phillip Creter, Creter & Associates

Course Description:
This course will provide an industry proven training guide to successful component chip attach including Flip Chip for use by engineers or senior technicians in a prototype and/or manufacturing environment. It is also designed for entry level personnel with little or no experience. The attendee will learn various definitions, details of techniques, materials, processes and equipment used in traditional component chip attachment of passives (capacitors, inductors, transformers, resistors), actives (diodes, transistors, ICs, ASICs, Memory) and rework methods. Topics covered include: SMT solder reflow, wire bonding, pick/place, dispensing, stamping, printing, TAB, epoxy vs. eutectic, hot gas rework, and process control.

Special attention will be given to Flip Chip (Direct Chip Attach) which will review various Flip Chip packaging applications. The attendee will learn definitions (UBM, WLP, C4, ICA, ACA, ACF, UF & stud bump), techniques, processes, materials, substrates (PCB, LTCC, HTCC, Thick Film, Thin Film, Flex, Polymer Film) and equipment used in flip chip die attachment and underfill using both solder and polymers. Included: design guidelines, solder and polymer wafer bumping, pick/place, solder reflow, polymer cure, underfill dispensing, and process control methodology.

Reliability analysis techniques for various types of component attach are discussed using optical, die shear, scanning electron microscopy and scanning acoustic microscopy. Operator issues include: setups, proper documentation, use of industry-proven lot travelers, inspection criteria, rework techniques and safety. A 100 page class handout and use of video clips enhance the learning experience. Actual microcircuit samples are passed around to attendees as visual aids.

Who Should Attend?
This course is designed for the attendee who has little initial familiarity with microelectronics packaging assembly processes at the chip component and flip chip level. Ideal for entry-level technicians and engineers but also for people in quality assurance, sales, marketing, purchasing, safety, administration and program management. Emphasis will be on visual aids.

Phil currently teaches professional development courses at microelectronics events and is a certified active instructor for the Department of Homeland Security.