IMAPS 2006 - 39th International Symposium on Microelectronics - Bringing Together the Entire Microelectronics Supply Chain!
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Technical Program

Tuesday: Morning Sessions (TA1 - TA6) | Afternoon Sessions (TP1 - TP6)
Wednesday: Morning Sessions (WA1 - WA6) | Afternoon Sessions (WP1 - WP6)
Thursday: Morning Sessions (THA1 - THA6)
Interactive Poster Sessions


Tuesday, October 10, 2006 | Morning Sessions: 8:00 AM - 10:50 AM

Industry
"Focused Track"
Systems/Design
Track
Materials Track
Reliability Track
Interconnect Track
Advanced Technologies Track
TA1
Advanced Packaging in RF and Wireless Applications I

Chairs: Ron Barnett, GeoMat Insights LLC; Aicha Elshabini, University of Idaho

View More Info on the RF/Wireless "Focused Sessions" or see session info below

Cutting edge RF, Microwave, and Millimeter packaging is the subject of this focused session, where you will see papers on MMwave Ball-Grid-Arrays, a novel method of eliminating bypass capacitors, a 3D plastic-based system-system-in-a-package, and several new innovative low cost Microwave packaging systems.

Microwave Performance of Ball Grid Array Packages
Rick Sturdivant, Microwave Packaging Technology, Inc.

A Novel Wideband Embedded Decoupling Structure for Power Supply Distribution in RF and Microwave Circuits that Eliminates Bypass Capacitors by Controlling Resonances
Thomas A. Jerse, The Citadel; Ron Barnett, GeoMat Insights LLC

Advanced Thick Film Technology Enabling Three-Dimensional Microwave Microcircuits
Lewis Dove, Agilent Technologies, Inc.

Wall-Grid Array Laminate Multi-Chip Module
Paul Cassanego, Brian Hutchison, Robin Zinsmaster, Donald Estreich, Matt Schwiebert, Bob Fullmer, Jim P. Stephens, Connie Van Schaick, Dave Dascher, Agilent Technologies

High Performance Thick Film Ball Grid Array Package
Donald E. Schott, Agilent Technologies

Compact and High Density Hermetic Modules for Microwave and Millimeter Wave Applications
Anh-Vu Pham, University of California, Davis

TA2
Electrical Design and Modeling I

Chairs: Jim Knighten, Terradata, a division of NCR; W. Kinzy Jones, Jr., Motorola

Leading-edge developments in high-speed signaling, PCB design, signal integrity, EMI/EMC, and other topics related to electrical design and modeling for components and systems.

VLSI Packaging Features for EMI Containment
Sergiu Radu, Sun Microsystems, Inc.

Advanced Via Structure in BGA Substrate Design for High-Speed Application
Robert Sung, Kevin Chiang, Yu-Po Wang, C.S. Hsiao, Siliconware Precision Industries

Challenges in Signal Integrity for Ultra-High Speed Multi-Gigabit – 10-40 Gb/s - PCB Designs for and Dispersion Control
Joseph T. (Ted) Dibene II, Kevin B. Quest, Intel Corporation; James L. Knighten, Terradata, a division of NCR

ESD Design Strategy for All-In-One Printers
Theodore M. Zeeff, Hewlett Packard

CNFETs: A Performance Comparison with Current Technology
Sima Borah, Z. J. Delalic, Temple University

Influence of Radiation Losses in Microstrip Ring Resonators used for Materials Characterisation
Richard Hopkins, University of Surrey

 

TA3
Underfill and Adhesives

Chairs: Herb Neuhaus, TechLead Corporation; Ray Pearson, Lehigh University

New underfill and adhesive applications and formulations represent the leading edge of materials development for electronics packaging. This session includes the most exciting new developments in the field.

Low Temperature Curing of Epoxies with Microwaves
Robert L. Hubbard, I. Ahmad, Lambda Technologies, Inc.; B. Toleno, Henkel Technologies

Effects of Environmental Exposures on Underfill Material Behavior
Guoyun Tian, Chang Lin, Jeffrey Suhling, Predeep Lall, R. Wayne Johnson, Auburn University

Underfill Interaction with a Pb-Free CSP Assembly Process and Impact on Reliability
Paul Morganelli, Vinod Mohan, Brian Wheelock, Antonio Prats, Tim Adams, Emerson & Cuming Specialty Polymers

Performance of a Novel Anisotropic Conductive Adhesive under Thermal and Temperature/Humidity Aging Conditions
S. Manian Ramkumar, Krishnaswami Srihari, Rochester Institute of Technology

Characterization of Carbon Nanotube Filled Conductive Adhesive
Jing Li, Janet Lumpp, University of Kentucky

High-Temperature Spin-on Adhesives for Temporary Wafer Bonding
Sunil K. Pillalamarri, Rama Puligadda. Brewer Science, Inc.; Markus Wimplinger, Stefan Pargfrieder, EV Group

TA4
Pb-Free Solder I

Chairs: Don Gudeczauskas, Uyemura International Corporation; Theodore Tessier, FlipChip International LLC

Pb-Free Assembly has many new challenges which must be overcome to maintain a robust assembly process. Reliability is also a concern as the Pb-Free solders show much different characteristics than the typical eutectic solutions. In many cases the assembly process can play a large role in the reliability of the final system as the solder characteristics can be changed with reflow profile and environment. The surface finish to use with Pb-Free solders must also be chosen carefully. The papers in this session will explore the topics of a Pb-Free assembly process and materials and their impact on reliability.

Reliability and Microstructural Assessment of Hybrid CBGA Assemblies
Mark K. Hoffmeyer, IBM Corporation; Mukta Farooq, IBM Microelectronics

Effect of Thermal Aging on Electrical Resistance of SnAgCu/Cu Joints
Marco Elisio Marques, Eduardo F. Monlevade, Nokia Technology Institute; Weiqun Peng, Nokia Research Center

Lead-Free Die-Attachment with High-Temperature Capability by Low-Temperature Nanosilver Paste Sintering
John Guofeng Bai, Guo-Quan Lu, Jesus N. Calata, Kevin D. Creehan, Virginia Polytechnic Institute and State University

Board Level Reliability of High Density Flip Chip BGA with Large Die and Large Package
Raghunandan Chaware, Leilei Zhang, Lan Hoang, Peter Ubaldo, Xilinx

Some Factors Affecting Voiding in Pb-Free Solder Joints
Gavin J. Jackson, Hector Steen, Henkel Technologies

TA5
Packaging Technologies

Chairs: Soren Norlyng, Micronsult; Jie Xue, Cisco Systems

This session features the challenges and the latest developments in materials, assembly process, and packaging reliability for products ranging from microwave to high-end networking applications.

Super Thin Flip Chip Assemblies on Flex Substrates - Adhesive Bonding and Soldering Technology - Reliability Investigations and Applications
Julian Haberland, Barbara Pahl, Fraunhofer IZM

A New Low Stress Flip Chip Bonding Method using Ultra-Precision Cutting of Metal/Adhesive Layers
Taiji Sakai, Seiki Sakuyama, Masataka Mizukoshi, Fujitsu Laboratories Ltd.

Challenges in Substrate Design, Assembly, and Reliability of SiP Package for a High End Networking Application
Judy Priest, Jie Xue, Li Li, Cisco Systems, Inc.

Precision Trimmable Passive Components
George Korony, Robert Heistand, AVX Corporation

Comparison of LTCC Material Systems through Dielectric and Transmission Characterization for Microwave/Millimeter Wave Applications
Michael Miller, David Zimmerman, Deepukumar Nair, Matthew Walsh, Bruce Butler, Delphi

Reliability Assessment of Hermetic Wafer Level Package for RF MEMS Device Application
Byung Gil Jeong, Samsung Advanced Institute of Technology

TA6
Emerging Technologies

Chairs: Kumaraswamy “Jay” Jayaraj, Simpel Corporation; Brian Farrell, Foster Miller Inc.

Papers in this session focus on emerging packaging technologies being developed in Industry and academia.

Au Stud Bumping for Wafer Probe Testing
Jamin Ling, Bob Werner, Luis Morales, Kulicke & Soffa Industries Inc.

Low Temperature Reduction of Copper Oxides using Electron Attachment
Christine Dong, Richard E. Patrick, Eugene J. Karwacki, Air Products and Chemicals, Inc.

Chemical and Electro-Chemical Processes for 3D Chip Integration with Through-Silicon-Via Electrodes
Bioh Kim, Charles Sharbono, Rajesh Baskaran, Brian Gardner, Semitool, Inc.

Flexible Interconnects for Deformable Ultra-Thin Substrates
T. Zoumpoulidis, M. Bartek, R. Dekker, L.Wang, A. Polyakov, J. Tian, S. Sosin, Technical University of Delft

Design and Characterization of Aligned Carbon Nanotube Based Gas Sensors
Ning Ma, Suresh Rajaputra, Praveen Sivakumar, Janet Lumpp, Vijay Singh, University of Kentucky

Innovative QFN Designs for System-in-Package Solutions
Andrew Holland, RF Modules & Optical Design Limited

 


Tuesday, October 10, 2006 | Afternoon Sessions: 1:45 PM - 5:30 PM
Industry
"Focused Track"
Systems/Design
Track
Materials Track
Reliability Track
Interconnect Track
Advanced Technologies Track

TP1
Advanced Packaging in RF and Wireless Applications II

Chairs: Ron Barnett, GeoMat Insights LLC; John Gipprich, Northrop Grumman Electronic

View the RF/Wireless "Focused Sessions" or see session info below

Innovative RF, Microwave, and Millimeter wave packaging is presented in this session, where you will see papers on multi-disciplined module/system-in-a-package design, including mmWave plastic, Low-loss High Temperature Co-fired Ceramic (HTCC), mmWave Low Temperature Co-fired Ceramic (HTCC), RF MEMS on high resistivity Silicon, and inexpensive high performance packaging

System-Level Design requirements for Wireless RF Module Design
Keith Felton, Cadence Design Systems Inc.

Photoimageable Thick-Film Circuits up to 100 GHz
Manju Henry, Charles E. Free, University of Surrey

Millimeter-Wave Performance of Alumina High Temperature Cofired Ceramics IC Packages
Rick Sturdivant, Microwave Packaging Technology, Inc.

Packaged Microwave Components for Multimedia Satellite Communication
Reinhard Kulke, Olaf Kersten, Josef Winkler, Carsten Günner, Matthias Rittweger, IMST GmbH

Hybrid Wafer-Level Packaging for RF-MEMS Applications
Marian Bartek, S. Sosin, J. Tian, J. Iannacci, Delft University of Technology, ECTM/DIMES

mm-Wave Packaging: A Low-Cost Solution Based on a Leadless Plastic Package
Mario Engl, Klaus Pressel, Jochen Dangelmaier, Horst Theuss, Werner Simbuerger, Herbert Knapp, Robert Weigel, Infineon Technologies AG

Reducing LTCC losses at High Millimetre-Wave Frequencies
M. Henry, C. Free, University of Surrey; Quentin Reynolds, Stefan Malkmus, Jim Wood, Heraeus Circuit Materials Division

TP2
Electrical Design and Modeling II

Chairs: Jim Knighten, Terradata, a division of NCR; W. Kinzy Jones, Jr., Motorola

Leading-edge developments in high-speed signaling, PCB design, signal integrity, EMI/EMC, and other topics related to electrical design and modeling for components and systems.

Accuracy and Application of Physics Based Circuit Models for Vias
Christian Schuster, Young Kwark, Mark Ritter, IBM T. J. Watson Research Center; Giuseppe Selli, James Drewniak, University of Missouri-Rolla

Designing Pin Grid Array Ceramic Packages for High Performance in High Density I/O Application
Jerry Aguirre, Paul Garland, Aki Nomura, Kyocera America, Inc.; Larry Retherford, George Lambert, John Daniels, Lincoln Laboratory MIT

Low Inductance Land-Grid Array Decoupling Capacitors
Andrew Ritter, Joseph M. Hock, AVX Advanced Product and Technolgy Center

Internal Radiated Emissions Generating External Conducted Emissions: An Overview
Bruce Harlacher, Fischer Custom Communications, Inc.

A Comprehensive Simulation Approach for Gigabit Speed PCB Design
Lawrence Williams, Denis Soldo, Ansoft Corporation

Power Delivery Effectiveness of Individual Power Planes in a Multiple Power Plane Pair Configuration Printed Circuit Board
Giuseppe Selli, Liang Xue, James L. Drewniak, Bruce Archambeault, Jun Fan, Samuel R. Connor, University of Missouri –Rolla; James L. Knighten, Terradata, a division of NCR


TP3
Cu/Low-K Packaging

Chairs: Surasit Chungpaiboonpatana, Mindspeed (Conexant) Inc.; Beth Keser, Freescale Semiconductor

Cu/Low-K wirebond and flip-chip packagings are critical to the development of advanced devices at 90nm and beyond. This session focuses at the critical challenges of this process through fundamental and experimental studies presented by industry leading IDM, OSAT, and research organizations.

Critical Process of Wire Bond Low-K IC Packaging
Louie Huang, S. S. Chen, Bryan Lin, Advanced Semiconductor Engineering, Inc.

Wafer Singulation Technology Development for Low k/Cu Technology
Chu-Chung (Stephen) Lee, TuAnh Tran, Sonder Wang, J. H. Wang, T. B. Lau, Freescale Semiconductor, Inc.

Shadow Moiré Thermal Stress Behaviors as a Predictive Method for Low k Wire Bonded Thermally Enhanced Package Reliability Performance
Sheila Chopin, Matt Ruston, Freescale Semiconductor Inc.

Assembly Process Development for 44um Wire Pitch Device with 90nm CMOS Technology and Bond over Active Pad Structure
Nhat (Nick) Vo, Tu Anh Tran, Chuchung (Stephen) Lee, Sonder Wang, C.C. Yong, Freescale Semiconductor, Inc.

Underfill Material for Pb-Free Cu/Low-K Flip Chip Package
Chih-Ming Chung, Jarsh Lin, Advanced Semiconductor Engineering, Inc.


TP4
Pb-Free Solder II

Chairs: Jon Aday, Amkor Technology, Inc.; Elvira Preecha, Qualcomm

Pb-Free Assembly has many new challenges which must be overcome to maintain a robust assembly process. Reliability is also a concern as the Pb-Free solders show much different characteristics than the typical eutectic solutions. In many cases the assembly process can play a large role in the reliability of the final system as the solder characteristics can be changed with reflow profile and environment. The surface finish to use with Pb-Free solders must also be chosen carefully. The papers in this session will explore the topics of a Pb-Free assembly process and materials and their impact on reliability.

Thermal and Mechanical Characterization of Lead Free Packages with Organic Carriers for High End Servers Applications
Arv Sinha, IBM Corp.

Study of the Ni-P/Pd/Au (ENEPIG) Deposit as a Final Finish for Packaging
Donald Gudeczauskas, Shigeo Hashimoto, Masayuki Kiso, Yukinori Oda, Uyemura International Corporation

Drop Test and Failure Mechanism of Sn-3.8Ag-0.7Cu and Sn-37Pb Solders in BGA Package
Jin-Wook Jang, Ananda P. De Silva, James E. Drye, Steven L. Post, Norman L. Owens, Jong-Kai Lin, Darrel R. Frear, Freescale Semiconductor, Inc.

Leadfree Automotive Electronics: Status Quo and First Experiences in Production and Field Behaviour
Petrik Lange, Andreas Herenz, Jochen Diekmann, Wolfgang Labod, Tilmann Seubert, Hella KGaA

Investigation of the Lead-Free Solder Joint Shear Performance
James Webster, Jianbiao “John” Pan, California Polytechnic State University; Brian J. Toleno, Henkel Technologies

Investigating the Lead Free Manufacturing Process
Rita Mohanty, Joe Belmonte, Speedline Technology

Effect of Reflow Profile (RSP Vs RTP) on Sn/3.8Ag/0.7Cu Solder Joint Strength
Ibrahim Ahmad, Universiti Kebangsaan Malaysia

TP5
Wirebonding I

Chairs: Roupen Keusseyan, DuPont Microcircuit Materials; Jianbiao John Pan, California Polytechnic State

The wire bonding of new, finer pitch packages, loop shapes and materials are continuously evolving. This session focuses on fine pitch issues.

New Wire Bonding Loops for Stacked Die Packages
Lee R. Levine, Bob Chylak, Stephen Babinetz, O.D. Kwon, Kulicke & Soffa Industries Inc.

Surface Characterization of Gold Bonding Wire for High Density Interconnect Application
Matthew Gallaugher, R. Sodhi, Z.Wang, Y.C. Koo, University of Toronto; J. Persic, Microbonds Inc.

Improvement of High-Temperature Reliability of Ball Bond using Platinum-Modified Gold Alloy Wires
Kazunari Maki, Yuji Nakata, Masayoshi Nagao, Akifumi Mishima, Mitsubishi Materials Corporation

Plasma Treatment for Enhancing Wire Bonding to Cu Surface
Serguei Stoukatch, Philippe Soussan, Eric Beyne, IMEC vzw.

Process Portability Quantification Method
Gur Giyora, Sonnenreich Beni, Kulicke & Soffa Industries, Inc. - Bonding Tools

Wirelocking for Fine Pitch Wirebond
Michael V. Ascerno, Freescale Semiconductor Inc.

PowerRibbon™ - An Alternative Interconnect Technology for Small Power Packages
Chrsitoph Luechinger, Kris Oftebro, Siegbert Haumann, Orthodyne Electronics

TP6
Packaging Materials and Processes using Nano Technologies for Next Stage Electronics (Japanese to English Translation)

Chairs: Fumio Miyashiro, PI R&D Co., Ltd.; Michael Alan Stein, Electro-Science Labs, Inc.

This session will discuss next stage in fine pitch circuit technologies by advanced nano-materials and nano-processes. This session will be presented in Japanese with English translation available.

Dielectric Layers Formed by Aerosol Deposition and its Application to Embedded Passive Ceramic Components
Jun Akedo, S. M. Nama, National Institute of Advanced Industrial Science and Technology; Y. Imanaka, Fujitsu Limited; T. Tsurumi, Tokyo Institute of Technology

Development and Application of Block Co-Polyimides Photo-Imageable Polyimide Ink
Toshiyuki Goshima, Shintaro Nakajima, Win Maw Soe, PI R&D Co., Ltd.

Direct Metal Patterning for Printable Electronics by Inkjet Technology
Shin-ichi Nishi, Konicaminolta Technologies Inc.

LTCC Multilevel Interconnection Substrate with Ink-jet Printing and Thick Film Printing for High Density Packaging
Yuki Kawamura, Koji Sigezawa, Tetsuro Tanaka, Koji Koiwai, KOA Corporation; Koichi Mizugaki, Kazuaki Sakurada, Toshiyuki Kobayashi, Kenji Wada, SEIKO EPSON Corporation

Liquid Wiring Technology by Ink-jet Printing Using NanoPaste®
Hiroshi Saito, Harima Chemicals, Inc.

Micro Bump Formation by using a Super Fine Inkjet System
Kazuhiro Murata, National Institute of Advanced Industrial Science and Technology

Application of Inkjet Printing Technology to Electro Packaging
Hideo Imai, SEIKO EPSON Corporation


Wednesday, October 11, 2006 | Morning Sessions: 8:00 AM - 11:30 AM

Industry
"Focused Track"
Systems/Design
Track
Materials Track
Reliability Track
Interconnect Track
Advanced Technologies Track

WA1
Advanced Packaging in Military Applications

Chairs: Greg Caswell, VirTex Assembly Services, Inc.; Christo Bojkov, MAXIM-DallasSemi

View the Military "Focused Sessions" or see session info below


This session will address issues and applications that are affecting the implementation of next generation military electronics, from 3D and novel packaging approaches, to fiberoptics and reliability.

A Systems-In-Package Approach for Military and Aerospace Applications using FlipChip and 3-D Packaging
Keith Sturcken, BAE SYSTEMS

3D Technologies for Advanced Hybrid/MCM Designs
Tom Dlouhy, Gordon Jensen, CAD Design Software

High Temperature Generic Electronic Module (GEM) for Aerospace Actuators
Bhal R. Tulpule, Richard Millar, Steve Raccio, Carole Teolis, Embedded Systems LLC

A Novel IC Packaging Approach
Anna Fontanelli, Mentor Graphics Corporation

Hot Solder Dip and Minimizing Thermal Gradients
Russell T. Winslow, Ganesh R. Iyer, Minerva M. Cruz, Six Sigma; Guna S. Selvaduray, San Jose State University

Effect of High Temperature Storage in Vacuum, Air, and Humid Conditions on Degradation of Gold/Aluminum Wire Bonds in PEMs
Alexander Teverovsky, QSS Group, Inc.

Leveraging the Militarization of COTS Adhesives for Significant Cost Savings of Terrestrial Fiber Optic Cables
Gregory T. Daly, Lockheed Martin MS2

WA2
System Packaging

Chairs: Ray Alexander, Terradata, a division of NCR; Don Hayashigawa, NxGen Electronics, Inc.

Running the system gauntlet from those measured in square centimeters producing a fraction of a BTU to systems measured in thousands of square feet producing well in excess of one million BTUs.

A Functional Mobile Phone in a SD Card-Sized Module: A Case Study in Electronics Miniaturization
Ilyas Mohammed, Shanquan Bao, Tessera, Inc.

Mechanical and Electrical Characteristics of Flexible Silicon Die for Chip Embedded Packaging
Kyuho Shin, Changyoul Moon, Yong-Jun Kim, Samsung Advanced Institute of Technology

RF/Microwave Modeling of SiP Modules – A Novel Approach
Ivan N. Ndip, Herbert Reichl, Stephan Guttowski, Fraunhofer IZM

New IC Packaging Structures for System in Package Applications
Joseph Fjelstad, Kevin Grundy, Gary Yasumura, SiliconePipe, Inc.

A 3D Computer Module Study
Don Hayashigawa, NxGen Electronics, Inc.

Practical 3D System-in-Package Solution for Mixed IC Technology Applications
Vern Solberg, Tessera, Inc.

External Environmental Considerations that Impact Packaging Design
Joseph Fleming, David Wang, NCR Corporation

WA3
Embedded and Integrated Passives

Chairs: Robert Heistand, II, AVX Corporation; Timothy Lenihan, TGL Consulting

Integration of passives is occuring on chip, on substrate, and in the PWB; all of these techniques are currently used in commercial applications. Results from continuing developments in this field for materials, fabrication techniques, and systems will be presented in the areas of capacitors and inductors.

Nanotechnology in Electronics Packaging
Abhijit Biswas, Pramod C. Karulkar, UAF Office of Electronic Miniaturization

Embedded Thin Film Capacitor for PCB Application
YulKyo Chung, Jungwon Lee, SeungHyun Sohn, HyunJu Jin, SungTaek Lim, Samsung Electro-Mechanics

3D Wafer Level Package with Large Inductors, Capacitors and Impedance Matching
Andrzej Peczalski, James Detry, Paul Bauhahn, Honeywell

The Impact of SiP Performance and Form-Factor Requirements on IPD Technology
Robert C. Frye, RF Design Consulting, LLC; Yaojian Lin, Guruprasad Badakere, Brett Dunlap, Eric Gongora, STATS ChipPAC, Ltd.

Frontend Components for 40 GHz FWA Applications in Multilayer LTCC
Reinhard Kulke, Olaf Kersten, Gregor Möllenbeck, Matthias Rittweger, IMST GmbH; Bong-Su Kim, Kwang-Seon Kim, Woojin Byun, Myung-Sun Song, ETRI

High Frequency Characteristics of LTCC Multilayer Substrates with Ink-Jet Printed Silver Conductors
Koji Shigesawa, Yuki Kawamura, Tetsuro Tanaka, Koji Koiwai, KOA Corporation; Koichi Mizugaki, Kazuaki Sakurada, Toshiyuki Kobayashi, Kenji Wada, SEIKO EPSON Corporation


WA4
Flip-Chip Reliability

Chairs: Charles Banda, Laboratory for Physical Sciences; Christo Bojkov, MAXIM-DallasSemi

As flip chip packaging continues to advance, the reliability of these advancements needs to be understood. In this session, several new flip chip interconnects, processes, and/or packages and their reliability will be presented.

Lead Free Wafer Bumping Techniques with Solder Paste
Richard R. Lathrop, Heraeus Incorporated-Circuit Materials Division

Electroless Nickel-Gold Flip Chip and CSP Reliability
Andrew J.G. Strandjord, M.Tsai, M. Johnson, H. Lu, D. Lawhead, R. Yassie, FlipChip International, LLC

Assembly Yield Study on Flip Chip PBGA using Electroless Ni UBM/Pb-Free Solder
J. D. Kim, W.-S. Choi, J.-W. Lee, S.-B. Lee, Samsung Techwin Co., Ltd.

A Flip Chip Attach Method for Dense, Moderate Pin Count, High Speed (80+ Gbps) Interconnects
Wendy L. Wilkins, M. J. Lorsung, J. E. Bublitz, B. A. Randall, J. L. Fasig, B. K. Gilbert, E. S. Daniel, Mayo Clinic

Interaction between Component Level and Board Level Reliability and the Effect on Low k Dielectric Reliability
Mudasir Ahmad, Sue Teng, Jie Xue, Cisco Systems, Inc.

High Reliability FCBGA Packaging
Ho-Yi Tsai, Siliconware Precision Industries Co., Ltd.

Multiple Flip-Chip Assembly for Hybrid Compact Optoelectronic Modules using Electroplated AuSn Solder Bumps
Kun-Mo Chu, J.-S. Lee, H. Oppermann, G. Engelmann, J. Wolf, H. Reichl, D. Y. Jeon, Korea Advanced Institute of Science and Technology (KAIST)


WA5
Wirebonding II

Chairs: Lee Levine, KNS Industries, Inc.; Thomas Green, National Training Center for Microelectronics

Wire bonding technology continues to change. Stacked die applications, coated wire, adaptive controls, heavy wire applications with higher frequency ultrasonic transducer systems are all focused.

Overview of X-Wire™ Insulated Wire Bonding Technology
Robert Lyn, John I. Persic, Young-Kyu Song, Microbonds Inc.

The Development of 100+ GHz High-Frequency MicroCoax Wire Bonds
Sean S. Cahill, Eric A. Sanjuan, BridgeWave Communications, Inc.; Lee Levine, Kulicke & Soffa Industries

Studbump Interconnects for High-power LED Assembly
Shatil Haque, Young-Keat Beh, Nooralshikin Hussain, Mooi Guan Ng, Seck Hoe Wong, Kok Hong Tan, Bob Steward, Paul Martin, Gilles Abrahamse, Lumileds Lighting LLC

Wire Bonding Solutions for Overhang Stack Die Configuration Packages: Finite Element Analysis and Wire Bond Process Optimization
John Foley, Tom Colosimo, Ivy Wei Qin, Kulicke & Soffa Industries Inc.

Geometry and Bond Improvements for Wire Ball Bonding and Ball Bumping
Daniel D. Evans, Jr., Palomar Technologies, Inc.

80kHz as an Alternate Frequency for Large Aluminum Wire Bonding
Michael McKeown, Alex Voronel, Orthodyne Electronics

Thermal Cycling Reliability of Heavy-Gauge Aluminum Wires Ultrasonically Bonded at Elevated Temperature
Wei-Sun Loh, Martin Corfield, C. Mark Johnson, The University of Sheffield

WA6
LED/SiC Packaging

Chairs: Douglas Hopkins, University of Buffalo; Herb Dwyer, Herb Dwyer Associates

High temperature and high current densities are always challenges cutting across many applications. This session shows advancements in LED and SiC packaging with tremendous commonality...what is and what is coming. Both processes and new materials are introduced.

Recent Development of DBC (Direct Copper Bonded) Substrates: High Temperature Solder Stop and Pure Copper, High Aspect-Ratio Vias
Jurgen Schulz-Harder, Karl Exel, Andreas Meyer, Curamik® Electronics GmbH

Packaging of an Extreme Environment DC Motor Drive for the NASA Venus Lander
Brice R. McPherson, J. Garrett, E. Cilio, J. Hornberger, S. Mounce, R. M. Schupbach, A. B. Lostetter, Arkansas Power Electronics International

Packaging of a High-Temperature Silicon Carbide (SiC) Three-Phase 4kW Motor Drive
Jared M. Hornberger, B. McPherson, R. M. Schupbach, A. B. Lostetter, A. Mantooth, Arkansas Power Electronics International, Inc.

Glass Encapsulated LEDs with High Reliability and Out-coupling Efficiency
Nobuhiro Nakamura, Shuji Matsumoto, Naoki Sugimoto, Asahi Glass Co., Ltd.

Aluminum-Based High-Temperature (>200°C) Packaging for SiC Power Converters
Douglas C. Hopkins, Cemal Basaran, University at Buffalo; David W. Kellerman, Material Solutions, LLC; Juan Gomez, Universidad EAFIT Applied



Wednesday, October 11, 2006 | Afternoon Sessions: 1:30 PM - 5:30 PM
Advanced Technologies Track
Systems/Design
Track
Materials Track
Reliability Track
Interconnect Track
Advanced Technologies Track

WP1
Sensor and MEMS Packaging

Chairs: Ajay Malshe, University of Arkansas; David Galipeau, South Dakota State University

The objective of this session is “application-specific” packaging for MEMS and Sensors.

Test Chip for Measurement of the Mechanical Stress caused by Packaging Applications
Soeren Hirsch, Bertram Schmidt, University Magdeburg

Controlling Vacuum Levels in Discrete MEMS Packages
David Muhs, Paul Barnes, SST International

M3: Modular Microassembly System for MEMS Packaging
Rakesh Murthy, Dan Popa, Manoj Mittal, Jeongsik Sin, Harry Stephanou, University of Texas at Arlington

Package Design for a Miniaturized Capacitive Based Chemical Sensor
Caroline A. Kondoleon, Thomas F. Marinis, Charles Stark Draper Laboratory

BCB Wafer Bonding Technologies for Wafer-Level Packaging with an Integrated MEMS Resonator
S. Brault, X. Leroux, M. El-Amrani, E. Dufour-Gergam, F. Parrain, S. Lani, A. Bosseboeuf, Institut d’Electronique Fondamentale; F. Verjus, P. Schwindenhammer, Philips France

Cu-Sn Solder Sealing for Hermetic Optical MEMS Devices Package
Won Kyoung Choi, Qian Wang, Woonbae Kim, Chang Youl Moon, Samsung Advanced Institute of Technology

Development and Characterization of Wafer-Level Hermetic Package for RF MEMS Applications
Suk-Jin Ham, Byung-Gil Jeong, Ji-Hyuk Lim, Kyu-Dong Jung, Moon-Chul Lee, Jun-Sik Hwang, Jong-Oh Kwon, Kae-Dong Baek, Woon-Bae Kim, Chang-Youl Moon, Samsung Advanced Institute of Technology

 

WP2
Thermal Management, Mechanical Design and Modeling

Chairs: Herman Chu, Cisco Systems; David Saums, DS&A LLC

This session is to promote discussion of leading-edge developments in thermal management and mechanical design components, materials, and systems solutions for microelectronic devices and systems.

Shear and Creep Resistance of Thermally Conductive Adhesive Tapes
Y. Joon Lee, Parker Hannifin, Chomerics Division

Dealing with the 3D Complexity of Power-Efficient Designs
Ralph Remsburg, Amulaire Thermal Technolgy

Three-Dimensional Electro-Thermal Modeling of Thin Film Micro-Refrigerators for Site-Specific Cooling of VLSI ICs
Je-Hyoung Park, Yan Zhang, Sung-Mo (Steve) Kang, Ali Shakouri, University of California, Santa Cruz; Kazuhiko Fukutani, Canon & University of California, Santa Cruz

Effect of PWB Design Factors and Glass Transition Temperature on PTH Reliability
Jingsong Xie, Yu-Jie Huo, Beijing University of Aeronautics and Astronautics (BUAA); Yuan Zhang, Huawei Technologies Corporation; Michael Freda, Sun Microsystems, Inc.

Modeling the Effect of Die Paddle Design and Polyimide Coating on the Thermo-Mechanical Reliability of Microelectronic Packages
Farnaz Parhami, An-Yu Kuo, Cypress Semiconductor

Heat Sink Thermal Enhancements
Andreas C. Pfahnl, Elyssa Kaplan, Amphenol TCS

Numerical Analysis of Residual Warpage of FBGA Package during EMC Curing Process
Yong Tae Park, Tae Min Kang, Hynix Semiconductor Inc.

WP3
Ceramic and Conductive Materials

Chairs: John Menaugh, DuPont Electronics; Larry Zawicki, Honeywell – KCP

Reliable thick film and LTCC technology continues to evolve and adapt to changing market requirements. This session features papers discussing technology and environmental enhancements. The LTCC presentations exemplify innovative process advances in a technology that has had huge world-wide growth during the past 2 decades.

Next Generation Multilayer Dielectrics for High Reliability Multilayer Hybrid Circuits
Stefan Flick, Annette Kipka, W.C. Heraeus GmbH; David Malanga, Heraeus Inc. - TFD

Interactions between Thick Film Resistors and Aluminum Nitride Substrates
Christel Kretzschmar, Günther Reppe, Fraunhofer Institut für Keramische Technologien und Systeme

Investigation of the Via Fill Process for High Density Multilayer LTCC Substrates
Fred D. Barlow, Brian Rowden, Gangqiang Wang, Aicha Elshabini, University of Arkansas; Larry Zawicki, Gregg Barner, Brent Duncan, Dan Krueger, Cristie Lopez, Honeywell Federal Manufacturing & Technologies

Dimensional Control of DuPont™ 943 LTCC Green Tape™ for High Frequency Applications
Michael A. Smith, Howard T. Sawhill, Carl Wang, DuPont Microcircuit Materials

On the Influence of Layer-to-Layer Misalignment on the Microwave Performance of LTCC Antenna Modules
Peter Uhlig, Sybille Holzwarth, Oliver Litschke, Alexandra Serwa, Dinh Trung Tran, IMST GmbH

High Performance Gold Coated Nickel Powders for Packaging Applications in Electronics
Brian W. Callen, Eric Kozculab, Sulzer Metco (Canada) Inc.

Performance of RoHS Compliant Thick Film Gold Conductor
Samson Shahbazi, Peter Bokalo, David Malanga, Meg Tredinnick, Jim Wood, Heraeus Inc. – TFD

WP4
Package Reliability I

Chairs: F. Patrick McCluskey, University of Maryland; Christo Bojkov, MAXIM-DallasSemi

This session will discuss Assembly, Test and Reliability evaluation for new devices and materials.

Fatigue Assessment of Solder Joints on Board Assembly Affected by PWB Warpage
Wei Tan, I. Charles Ume, Georgia Institute of Technology

Effect of Dwell Times on the Thermal Cycling Reliability of Pb-free Wafer- Level Chip Scale Packages – Experiments and Modeling
S. Chaparala, J.M. Pitarresi, State University of New York at Binghamton; M. Meilunas, Universal Instruments Corporation

Numerical Investigations of Failure Potentials of Substrate Through Holes
Yi-Shao Lai, Tong Hong Wang, Chin-Li Kao, Advanced Semiconductor Engineering, Inc.

Electrothermal Coupling Analysis and Experimental Verification for Wirebond Devices under Operation Test Conditions
Yi-Shao Lai, Chin-Li Kao, Chang-Chi Lee, Advanced Semiconductor Engineering, Inc.

Anisotropic Conductive Films for Flex-Flex Bonding
Abhishek Singh, Ajay P. Malshe, University of Arkansas; K. Uka, David M. Barnett, Q-Flex, Inc.

Space Application and Microwave Glob-Top: A Reality
Claude Drevon, Philippe Monfraix, Laurent Garcia, Jean-Louis Cazaux, Alcatel Alenia Space

Management of Information and Data used for Failure Assessment of Printed Circuit Board Assembly
Medy Ramot, RAFAEL; Diganta Das, Michael G. Pecht, University of Maryland - CALCE

 

WP5
Flip-Chip Interconnection

Chairs: Beth Keser, Freescale Semiconductor; Hong Yang, Applied Micro Circuits Corporation

Flip chip devices can be connected to a substrate or board through a variety of interconnection materials. In this session, advances in flip chip interconnection will be reviewed with an emphasis on interconnection formation.

C4NP - First Manufacturing & Reliability Data for High-End FlipChip Solder Bumping based on IBM’s C4NP Process
Klaus Ruhmer, Eric Laine, Peter Gruber, Dietrich Toennies, Emmett Hughlett, SUSS MicroTec, Inc.

A Novel DoD Metal-Jet System for Solder Bumping Formation
Taik-Min Lee, Tae Goo Kang, Jeong-Soon Yang, Jeong-Dai Jo, Kwang-Young Kim, Byung-Oh Choi, Dong-Soo Kim, Korea Institute of Machinery & Materials

Reliability of New Gold-Solder Interconnection System
Jae-Yun Kim, Yong-Bin Sun, Ho-Jung Chang, Kyonggi University

Latest Technological Advancements in Stencil Printing Processes for Ultra-Fine-Pitch Flip Chip Bumping up to 60µm Pitch
Dionysios Manessis, R. Patzelt, A. Ostmann, R. Ascenbrenner, H. Reichl, R. Kay, E. de Gourcuff, Technical University Berlin/Fraunhofer IZM Berlin

An Evaluation of Wafer Bumping Stencils Based on Solder Transfer Ratios and Predicted Bump Heights
Scott Popelar, Robert A. Niemet, IC Interconnect

Development of Sn-Cu Bumping by Alloying Cu/Sn Metal Stacks
Kazuhito Higuchi, Masaharu Seto, Masayuki Uchida, Takashi Togasaki, Hirokazu Ezawa, Toshiba Corporation

Production Feasibility of Electrodeposition of Tin-Silver-Copper for Wafer Bump Applications
Rozalia Beica, Eric Chiu, Nathaniel Brese, Angelo Chirafisi, Rohm and Haas Electronic Materials, L.L.C.

 

WP6
Nano Materials and Technologies

Chairs: Chris Matayabas, Intel Corporation; Daewoong Dave Suh, Intel Corporation

This session is focused on application of nano materials and technologies to microelectronic packaging. In this session, opportunities and challenges in application of nanotechnology for the enhancement of packaging are reviewed and key material innovations in this area are presented.

Low Temperature Printing Wiring with Ag Salt Pastes
Katsuaki Suganuma, M. Hatamura, K.-S. Kim, M. Kawazome, S. Horie, A. Hirasawa, H. Tanaami, Osaka University

Nanocomposites and Nanoparticle Fluids for Microelectronic Packaging Applications
Emmanuel P. Giannelis, Cornell University

Controlling Orientation and Defects in Block Copolymer Thin Films Through Directed Self-Assembly
Alamgir Karim, Ronald Jones, Brian Berry, Eric Amis, Sushil Satija, Charles Laub, NIST - Polymers Division

Opportunities and Challenges for the Application of Nanotechnology to Microelectronic Packaging Solution
Vijay Wakharkar, Chris Matayabas, Intel Corporation

Nanoscale Materials and Structures for Advanced Electronics
Ray Tsui, Motorola Labs.

Stability Issues and Internal Stresses in Nanoimprint Structures
Alamgir Karim, Hyun Wook Ro, Yifu Ding, Hae-Jeong Lee, Ronald L. Jones, Eric K. Lin, Christopher L. Soles, Wen-li Wu, NIST Polymers Division; Daniel R. Hines, University of Maryland

Packaged N-Typed Field Effect Transistors Using GaN Nanowires
Son Nguyen, Joan Zdenka Delalic,Temple University; Jeffrey M. Catchmark, Penn State Nanofabrication Facility

 


Thursday, October 12, 2006 | Morning Sessions: 8:00 AM - 12:20 PM

Industry
"Focused Track"
Systems/Design
Track
Materials Track
Reliability Track
Interconnect Track
Advanced Technologies Track
THA1
Advanced Packaging in Biomedical Applications

Chairs: Joan Delalic, Temple University; Sharad Bhatt, Shanta Systems

View the Biomedical "Focused Sessions" or see session info below

The biomedical session is novel to the IMAPS 2006 event. It introduces a new approach to packaging and application of biomedical sensors and micro/nano electronic devices

Aberration Retrieval from the Point Spread Function in Ophthalmic Wavefront Sensors
Edward Polkowski, MIEYE LLC

Development of Portable Zeolite Based Gas Sensor
David M. Kargbo, Z. Joan Delalic, Zameer Hasan, Son Nguyen, Temple University

All-Electrical PZT/SiO2 Piezoelectric Microcantilever Mass Sensors with Femtogram/Hz Sensitivity
Wan Y. Shih, Zuyan Shen, Wei-Heng Shih, Drexel University

Portable Device for Detection of Toxic Chemicals Using Yeast-Based Biosensor
Son Nguyen, Sowrabha Vijayanna, Joan Z. Delalic, Danny Dhanasekaran, Temple University

Miniature Thin Film Precision Resistors, Capacitors and Inductors for Medical Applications
Robert Heistand II, George Korony, AVX Corporation

New Leak Test Method Increases Reliability of Hermetic Packages
John C. Pernicka, Pernicka Corporation

Reliability of Stacked Package
Shin Kim, Seo Young Yang, Young Min Lee, Dong Gil Shin, Samsung Electronics

THA2
Interconnect Technologies and High Density Boards

Chairs: Bruce Romenesko, John Hopkins University/APL; Munawar Ahmad, Molex, Inc.

This session will discuss the latest technology trends related to high density substrates and advanced interconnect.

Reducing the Size of High Speed Copper Interconnects
Herb Van Deusen, Henry N. Yates, W.L. Gore & Associates, Inc.

Development of High Speed Copper Interconnects for PCI Express Applications
Christopher
DiMinico, Leoni High Speed Cables

Electrical and Thermomechanical Evaluation of Advanced 2nd-Level-Interconnects for LTCC Modules
Torben Baras, Maria Corrales Hernandez, Arne F. Jacob, Hamburg-Harburg University of Technology

Electrical Design Methodology for the over 20 Metal Layer PALAP FCBGA Substrate for the High-Speed Low-Power/Ground Noise Application and its Electrical Performance
Ryuichi Oikawa, Katsunobu Suzuki, NEC Electronics Corporation

Improved Direct Write Technology for High Frequency Interconnects on Flexible Substrates Improved Direct Write Technology for High Frequency Interconnects on Flexible Substrates
Valery Marinov, Yuriy Atanasov, North Dakota State University

High Temperature Electrical Shorts in Printed Wiring Boards
Aaron C. Der Marderosian, Sr., Raytheon Company

THA3
RoHS Compliance and Outsourcing

Chairs: Peter Elenius, E and G Technology Partners LLC; Kim Davies, Sanmina-SCI, Cable Systems

With RoHS taking effect July 1, the compliance requirements need to be understood and implemented by all parties in the electronics supply chain. This session covers RoHS compliance from the OEM through outsourcing by presenting what companies are doing to comply and what your company needs to do to be in compliance.

ECOMOTO - An OEM’s Journey to a Sustainable World
William Olson, Siegfried Pongratz, Jim Liu, Motorola Inc.

The RoHS Experience at NCR
Paul Rostek, Joe Fleming, NCR Corporation

IC Packages Certification for Green Compliance
Jeffrey C. B. Lee, IST-Integrated Service Technology

Achieving Compliance with the EU RoHS Directive - An Update
Chris J. Robertson, Paul Goodman, Stephen Pitman, ERA Technology Ltd.

Working with Chinese Suppliers: Case Studies and Ethics Issues
Ken Kuang, Torrey Hills Technologies, LLC; Geoffery Gao, Kevin Duan, GTSI Corp.

THA4
Package Reliability II

Chairs: F. Patrick McCluskey, University of Maryland; Jie Xue, Cisco Systems

Requirements for high reliability products continue to drive for a robust packaging design and for improvement in materials and assembly process. This session will discuss reliability performance of organic, hermetic, and Pb-Free packages.

Characterization Methods for the Mechanical Stress Caused by Packaging Processes
Soeren Hirsch, Bertram Schmidt, Marc-Peter Schmidt, University Magdeburg

Improvement of Organic Packaging Thermal Cycle Performance Measurement
William E. Bernier, David B. Stone, Anuj Jain, Stephen R. Cain, Mohamed Belazzouz, Peter Slota Jr., IBM Corporation; Glenn O. Dearing, Christian R. Lecoz, Paul J. Hart, Endicott Interconnect Technologies, Inc.

Behavior of Moisture in Sealed Electronic Enclosures
Aaron C. Der Marderosian, Sr., Raytheon CompanyA

Low Cost High-Reliability Hermetic Packaging Option
Thomas E. Salzer, Hermetric, Inc.

Copper Column Grid Array, A High Performance Lead-Free Alternate
Rocky Shih, Joyce Taylor, Francois Billaut, Hewlett Packard Company; Mario Interrante, International Business Machines Corporation; George Oxx, Wesley Enroth, Allen Mays, Solectron Corporation; Dana Korf, Sanmina-SCI Corporation

High Reliability Testing for Flip Chip Gold to Gold Interconnect
Philip Couts, TDK Corporation of America

Reliability of Soldered Components and Aluminum Wire Bonds on Plated LTCC Substrates
M. Ray Fairchild, D.H.R. Sarma, Delphi Electronics and Safety; Yung-Ping Wu, DT Microcircuits Corp.; Nicolas Gosselin, HIDEMO

THA5
3D Packaging and High Density Substrates

Chairs: Leonard Schaper, Univ. of Arkansas; JianQiang “James” Lu, Renesselaer Polytechnic Institute

This session deals with advanced developments in the design and fabrication of dense interconnect substrates and 3-D chip packaging.

Direct Cu-Cu Thermo-Compression Bonding for 3D-Stacked IC Integration
Serguei Stoukatch, Koen De Munck, Wouter Ruythooren, Piet De Moor, Deniz Sabuncuogly Tezcan, Bart Swinnen, IMEC vzw.

Electrical Interconnects for 3D Wafer Stacks
Praveen Pandojirao-Sunkojirao, Rachita Dewan, Ping Zhang, Dan O. Popa, J.-C. Chiao, Harry E. Stephanou, The University of Texas at Arlington

Fine Circuit Formation by Semi-Additive Process using Ultra Thin Copper Foil
Ryoichi Watanabe, Sukwon Lee, Cheol-Ho Choi, Samsung Electro-Mechanics Co., Ltd.

Adaptive Pattern Lithography by Laser Direct Imaging for Correctly Imaging on Distorted Substrates
Barry Ben-Ezra, David Birnbaum, Orbotech Ltd.

Bond Wire Yield Rate Optimization on SiP in a 3D Design Environment Stacked
Gordon Jensen, John Sovinsky, CAD Design Software

High-Performance Flip-Chip BGA Technology Based on Thin-Core and Coreless Package Substrate
Masateru Koide, Kenji Fukuzono, Hideaki Yoshimura, Toshihisa Sato, Kenichiro Abe, Hidehiko Fujisaki, Fujitsu Limited

Novel Concepts for BCB Processing
C. Brubaker, EV Group Inc.; M. Jennison, Avago Technologies

THA6
Photonic/ Optoelectronic Packaging

Chairs: Yongzhi He, University of California - Irvine; Ju Choi, University of California - Irvine

This session will review the latest progress in the packaging technologies for optoelectronic and photonic devices and systems for various applications.

A Thermal AWG Multiplexer Based on Passive Alignment Packaging Technology
HyungJae Lee, Tae Hoon Kim, POINtek Inc.

An Effectual Approach to Substantial Cost Savings
Gregory T. Daly, Lockheed Martin MS2

Liquid Crystal Polymer (LCP) Printed Circuit Board (PCB) Based Optoelectronic and Electronic Packaging with Functionally
Hermetic Performance

Linas Jauniskis, Brian Farrell, Andrew Harvey, Foster Miller Inc.

Interactions in Optoelectronic Packaging
John S. Mazurowski, Pennsylvania State University

1.25Gbps Optical Triplexer Module with Planar Lightwave Circuit
Yong-Sung Eom, Sung-Il Kim, Jong-Tae Moon, Electronics and Telecommunications Research Institute

Rare Earth Doped Photonic Glass Materials for the Miniaturization and Integration of Optoelectronic Devices
Ju H. Choi, Frank G. Shi, University of California - Irvine

Fluxless Soldering for Hermetic Packaging of MOEMS
Abiodun Fasoro, Amit Patil, Dan O. Popa, Jeongsik Sin, Woo Ho Lee, Heather Beardsley, Dereje Agonafer, Harry E. Stephanou, The University of Texas at Arlington

 

 

 


International Microelectronics And Packaging Society
Everything in Electronics Between the Chip and the System!
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