IMAPS 2009 - 42 International Symposium on Microelectronics - San Jose, CA  
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Images courtesy of:
Natel, Hesse & Knipps, and the San Jose Convention and Visitor Bureau.

   Platinum Premier Sponsor:

   Gold Premier Sponsor:    Silver Premier Sponsor:

   Presidential Sponsor:

Natel - Premier Sponsor, Platinum
Hesse & Knipps - Premier Sponsor, Gold
Heraeus Thick Film Division - Premier Sponsor, Gold
Metalor - Presidential Sponsor

Professional Development Courses (PDCs)

All PDCs run 9:00 am - 5:00 pm, unless otherwise noted

Do you want to broaden and strengthen your skills and knowledge, optimize your manufacturing processes, and integrate the latest advances in materials and technologies to maintain your strength in today’s competitive global market? The Technical Committee of IMAPS is pleased to present a comprehensive offering of Professional Development Courses that provide detailed information on topics of immediate interest to the Microelectronics and Packaging community.  So please be sure to choose from the 15 in-depth Professional Development Courses taught by recognized industry experts.  You will discover the following key ways that will benefit you.

  • Better understand the skills and knowledge necessary in today’s industry.
  • Be exposed to the rapidly expanding developments in new materials and technologies.
  • Consult with renowned authorities about your current R&D or manufacturing problems and challenges.
  • Learn new ways to identify, think about, and address your problems and opportunities.
  • Great opportunities to interact with industry experts and other course attendees.
  • Certificate of Attendance and much more…

Your PDC Registration Fee Includes:

  • Lunch on the day of your course
  • Refreshment breaks
  • All course materials
  • PDC Reception on Sunday evening (for Attendees & Instructors only)
  • Certificate of Attendance

PDC Lunches and Reception sponsored by:Hesse & Knipps - Premier Sponsor, Gold

PDC Cancellation policy:

IMAPS reserves the right to cancel a course if the number of attendees is not sufficient.  You can transfer to a different course or we will refund you the corresponding amount.

Sunday, November 1
Monday, November 2

S1: RF/Microwave Hybrids:
Basics, Materials and Processes

S2: Advanced Packaging for Power and Energy

S3: Hybrid Visual Inspection per Mil-STD-883

S4: Design and Analysis of Experiments

S5: Plating Processes for High Reliability Microelectronic Devices

S7 - ½ day: 9 am - Noon
Achieving High Reliability for Lead-Free Solder Joints - Materials Consideration

S8 - ½ day: 1 pm - 5 pm
Reliability of Lead-Free System - How to Alleviate Failures - Practical Issues

M1: Wire Bonding in

M2: High-Performance Thermal
Management Materials

M3: Hermeticity Testing, RGA and “Near Hermetic” Packaging Concepts

M4: Introduction to Microelectronics Packaging Technology

M6: TSV and Other Enabling Technologies for 3D IC Integration and WLP

Sunday, November 1, 2009

RF/Microwave Hybrids: Basics, Materials and Processes
Course Leader: Richard Brown, Richard Brown Associates

Course Description:
In recent years, the demands for high frequency systems and products have been growing at a rapid pace. Coupled with the continuing development of monolithic integrated circuits, MMICs, are new materials and process refinement of hybrids. As a result, system and product designers are faced with the choice between hybrids and MMICs; i.e., complete system on a chip vs. hybrids with discrete devices, or more often, somewhere in-between.

This course will begin with a short, non-mathematical review of high frequency basics. Next a comparison of MMICs and hybrids is presented. The transmission line as the basic circuit component of RF and microwave hybrids will be reviewed. Hybrid “waveguide” structures will be compared as they relate to transmission line properties. The basic materials (conductors, dielectrics and substrates) and their properties will be introduced. Their effect on impedance, circuit properties and performance will be discussed. Processing technologies suitable for RF/microwave hybrids will be reviewed. Selected packaging protocols, such as vias and bonding wires, will be discussed in light of their influence on RF/microwave performance. At the completion of this course, attendees will have a better understanding of many of the critical materials and processing factors affecting high frequency circuit performance.

Who Should Attend?
Those microwave industry professionals who want to better appreciate the critical materials, process interactions and variables affecting high frequency hybrid manufacturing. Supervisors, engineers and technicians involved in product development, design and manufacture are encouraged to attend.

Special Course Materials:
All attendees will receive a complimentary copy of RF/Microwave Hybrids: Basics, Materials and Processes, by Richard Brown, Springer Publishers, 2003 (List Price $195).

Richard Brown is a technical and engineering consultant in hybrids, with more than 30 years experience, encompassing thin and thick film, electroplating and substrate technologies. He began his career at Bell Telephone Laboratories. After joining RCA Solid State in 1968, he transferred in 1979 to the RCA Microwave Technology Center in Princeton. In 1991, Mr. Brown joined an Alcoa Electronic Packaging technology team as program manager to implement thin film on high temperature co-fired ceramic for MCMs.

He has published extensively, authoring a chapter on Thin Film for Microwave Hybrids in “Handbook of Thin Film Technology,” McGraw-Hill, NY, 1998, A. Elshabini-Riad, Ed., and most recently RF/Microwave Hybrids; Basics, Materials and Processes, Kluwer Academic Press, 2003. In 1995, ISHM awarded him the prestigious John A. Wagnon, Jr. Technical Achievement Award.

Advanced Packaging for Power and Energy
Course Leader: Dr. Douglas C. Hopkins, IMAPS Fellow, University at Buffalo

Course Description:
Advanced materials, such as conductive epoxies and adhesives or metal-bonded ceramics, allow unique packaging to increase density and improve thermal management in harsh environments. Use of SiC and GaN has fostered significant development in approaches that offer operation >200°C. New packaging techniques have been developed for high-density circuits and systems, including power supply-in-package, power supply-on-chip, and integrated thermal management. In this seminar, those and other packaging approaches, such as COF, MID, FR-4, LTCC, IMS, DBC, MMC, are characterized in a continuum to help the designer understand how they can be combined for optimal thermal management and mechanical reliability. Aluminum-based packaging is discussed for higher power packaging to show advantages of using a near mono-material metallurgical hierarchy to greatly increase reliability.

This course provides a packaging engineer with the critical issues and design guidelines for power and energy packaging in harsh environments for levels 1-5, that directly influence the electrical, mechanical and thermal circuit design, and performance, cost and reliability. When finished, the attendee should be able to compare present and evolving packaging approaches; partition a circuit for optimum packaging technologies; and identify critical test parameters for manufacturing and test of systems for harsh environments.

Who Should Attend?
Engineers and managers responsible for harsh-environment operation of electrical and physical circuit designs, which need to move to much higher thermal and packaging densities, or to improve reliability at much higher operating temperatures.

Dr. Hopkins is Research Professor at the University at Buffalo (SUNY), associate director of the UB Electronics Packaging Laboratory and director of the Electronic Power and Energy Research Lab, where he directs R&D in the physical integration of very high-density power electronic systems. He worked for GE™ and Carrier™ R&D Centers, and held visiting positions at several national labs. He is an IEEE senior member and IMAPS Fellow. He is a founding member and now chair of the IMAPS Subcommittee on Power Packaging. He was Technical Chair of the International Workshop on Integrated Power Packaging 1998, and General Chair 2000, co-sponsored by IMAPS and IEEE. He has authored over 70 journal and conference publications, received three ISHM “Best Paper of Session” awards, and other awards.

Hybrid Visual Inspection per Mil-STD-883
Course Leader: Thomas J. Green, TJ Green Associates LLC

Course Description:
The intent of this course is to give the student a good overview of the materials and processes used to assemble Hybrids/MCMs/RF Modules and review of the associated visual inspection criteria. The course begins with wafer fabrication processes (silicon and GaAs) and moves through thick and thin film substrate manufacturing, epoxy/solder die and substrate attach, ball and wedge wire and ribbon bonding. At each step of the way key processes are highlighted and the associated defects that result from improperly controlled processes are looked at in detail (e.g., defective air bridges, excessive ball squash, too much epoxy etc.). The instructor will share valuable lessons learned from real life experiences. Over 150 color photographs of actual production defects are reviewed and discussed in detail.

Course Outline:

  • Hybrid Materials and Processing Overview
  • General Inspection Guidelines and Procedures
  • MIL-PRF-38534 MIL-STD-883 TM 2017 TM 2010 Requirements

Pre Cap Visual Inspection Criteria:

  • Defects related to wafer fab, saw and break, probe test etc.
  • Thick Film/Thin film substrate defects, e.g., cracks, chipouts
  • Laser Trim defects
  • Epoxy die attach, fillet criteria, typical problems encountered
  • Eutectic solder attach
  • Wirebond defects e.g., Excessive squash out, heel cracks, misplaced bonds etc.
  • Foreign Material Identification and Contamination Control

    Who Should Attend?         
    This PDC is intended for inspectors, quality engineers, process engineers, designers, and even managers responsible for the quality and workmanship of high rel military and space qualified microelectronics.

Thomas J. Green ( is the principal at TJ Green Associates LLC (, a Veteran Owned Small Business focused on training and consulting for military, space and medical microelectronic devices. He has over twenty-five years experience in the microelectronics industry at Lockheed Martin and USAF Rome Laboratories. At Lockheed he was a Staff engineer responsible for the materials and manufacturing processes used in building custom high reliability space qualified microcircuits for military and commercial communication satellites. He has conducted experiments and presented technical papers at NIST and IMAPS on leak testing techniques and optimization of seam welding processes through statistical DOE methods. Tom is an IMAPS Fellow and active leader in the society. He has a B.S. in Materials Engineering from Lehigh University and a Masters from the University of Utah.


Design and Analysis of Experiments
Course Leader: Dr. Jianbiao (John) Pan, California Polytechnic State University

Course Description:
The Design of Experiments (DOE) is a vital tool in microelectronics packaging product/process development and product/process optimization. The appropriate use of DOE can improve product quality and decrease costs. This course will enable the participant to plan and conduct experiments, analyze the resulting data, and draw valid conclusions. Practical examples related to microelectronics and electronic packaging will be given to illustrate the use of designed experiments.

This course covers various experimental designs including single factor experiments, completely randomized block designs, full factorial and fractional factorial designs. At the end of this course, participants will be capable and confident in designing and analyzing experiments to improve and optimize manufacturing processes. Specifically you will be able to:

  • Select appropriate input variables and response variable(s)
  • Choose and conduct the appropriate type of experimental design
  • Perform ANOVA analysis, including main and interaction effects, and residual analysis to check assumptions
  • Draw valid conclusions
  • Use Minitab software to create experimental designs and perform statistical analysis

Students are encouraged to bring along laptop computers to use during class. If you don’t have access to Minitab, you can download a 30-day free trial copy from (

Special Course Materials:
All attendees will receive a complimentary copy of Design and Analysis of Experiments, 7th Ed., by Douglas C. Montgomery, John Wiley & Sons, Inc., 2008 (List Price: $161).

Who Should Attend?
Engineers, scientists, technicians, and managers in R&D, process development, and manufacturing, or individuals who desire to design their own experiments and/or analyze experimental data.

Dr. Jianbiao (John) Pan is an associate professor in the Industrial and Manufacturing Engineering Department at California Polytechnic State University, San Luis Obispo, California. He received a PhD in Industrial Engineering from Lehigh University, Bethlehem, PA. His research interests include the materials, processes, and reliability of microelectronics and optoelectronics packaging. He has studied extensively in improving microelectronics packaging processes and reliability using design of experiments methodology, and has published over 30 technical papers. He is a senior member of IEEE, IMAPS, and SME. Dr. Pan is a recipient of the 2004 M. Eugene Merchant Outstanding Young Manufacturing Engineer Award from SME. He is a Highly Commended Winner of the Emerald Literati Network Awards for Excellence 2007. He is also an invitee of the NAE Frontiers in Engineering Symposium in 2007.

Plating Processes for High Reliability Microelectronic Devices
Course Leader: Fred Mueller, CEF, General Magnaplate Corp.

Course Description:         
• Provide a thorough overview of the chemistries of nickel, gold, and other precious metals that can be deposited by electro/electroless plating on a variety of applications in the field of electronics;
• Present methods for controlling the properties of plating solutions to maximize the deposits properties;
• Understand the use of Laboratory controls including the Hull Cell and other plating cells to test solutions;
• Highlight the engineering differences and troubleshooting problems in plating processes used in Plating for Electronics.

Special Course Materials:
All attendees will receive a copy of Plating for Electronics (an AESF Publication).

Who Should Attend?
This course is intended as an introductory to intermediate level course for process engineers, quality engineers, and managers responsible for Electronic Finishing.

Mr. Mueller is a consultant and serves as a national certified instructor for the American Electroplaters and Surface Finishing Foundation (AESF). He has over twenty-five years experience in the plating industry in printed circuits and plating for electronics. He is currently the Corporate Quality Manager at General Magnaplate, Linden, NJ. As a Chemist, Fred has conducted experiments and presented technical papers at SurFin on various topics in electroplating. He has served as Chairman of the Quality in Surface Finishing Committee and the Electro-forming Committee of the AESF.

Multilayer Co-fired Ceramics
Course Leaders: Aicha Elshabini, Ph.D., & Fred D. Barlow, Ph.D., University of Idaho



S7 - ½ Day Course: 9:00 am - Noon
Achieving High Reliability for Lead-Free Solder Joints - Materials Consideration
Course Leader: Dr. Ning-Cheng Lee, Indium Corporation

Course Description:
This course covers the detailed material considerations required for achieving high reliability for lead-free solder joints. The reliability discussed includes joint mechanical properties, development of type and extent of intermetallic compounds (IMC) under a variety of material combinations and aging conditions and how those IMCs affect the reliability, failure modes, thermal cycling reliability, and the fragility of solder joints as a function of material combination, thermal history, and stress history will be addressed in details, and novel alloys with reduced fragility will be presented. Electromigration, corrosion, and tin whiskers will also be discussed. Furthermore, the reliability of through-hole solder joints will be reviewed, and recommendation will be provided, particularly for thick boards. The emphasis of this course is placed on the understanding of how various factors contribute to the failure modes, and how to select proper solder alloys and surface finishes for achieving high reliability. Also presented are the desirable future alloys and fluxes in order to meet the challenge of miniaturization.

Who Should Attend?         
Anyone who cares about achieving high reliability lead-free solder joints and would llike to know how to achieve it should take this course.

Dr. Ning-Cheng Lee is Vice President of Technology of Indium Corporation of America. He has been with Indium since 1986. Prior to joining Indium, he was with Morton Chemical and SCM. He has more than 20 years of experience in the development of fluxes and solder pastes for SMT industries. In addition, he also has very extensive experience in the development of underfills and adhesives. He received his PhD in polymer science from University of Akron in 1981, and BS in chemistry from National Taiwan University in 1973. Ning-Cheng is the author of “Reflow Soldering Processes and Troubleshooting: SMT, BGA, CSP, and Flip Chip Technologies by Newnes. He was honored as 2002 SMTA Member of Distinction, and received 2006 Exceptional Technical Achievement Award from CPMT. He serves on the SMTA board of directors.

S8 - ½ Day Course: 1:00 pm - 5:00 pm
Reliability of Lead-Free Systems - How to Alleviate Failures - Practical Issues
Course Leader: Dr. Jennie S. Hwang, H-Technologies Group, Inc.

Course Description:
The strategy and remedies to alleviate failures stemming from prevalent issues, such as tin whisker and tin pest, electromigration, intermetallics, packages, components, PCB and manufacturing-related defects and failures will be discussed. The course will outline the critical roles of intermetallic compounds at-interface and in-bulk. The formation and growth of intermetallic compounds in relation to process and reliability performance and the difference between Pb-Free and SnPb will be discussed. The effects of the process steps on the reliability of the reworked high pin count large BGA packages and the critical parameters to prevent failure will also be outlined. Scientific principles behind both the anticipated and the observed properties and performance data will be summarized. This course will conclude with system reliability in relation to cost, manufacturability and service conditions.

Main topics:

1. Tin whisker and tin pest – causes and mitigation measures
2. Electromigration vs. corrosion vs. corrosive environment
3. Solder joint voids – effects, causes, criteria vs. reliability
4. Intermetallics-related failures and prevention – at-interface, near interface, in-bulk
5. Array packages (BGA/CSP) issues including black pad problem – failure and prevention
6. Reliability vs. rework - key parameters & failure prevention (high I/O large BGA rework)
7. Packages and components – likely failures and prevention
8. PCB – likely failures and prevention (Cu-pad lifting, Pad-cratering, thick & thin board issues)
9. Production-induced failures and prevention (tomb-stoning, open solder joints with QFP, open solder joints with BGA…)
10. Scientific basis behind the failures and remedies
11. Reliability vs. cost
12. Reliability vs. industry standards
13. Reliability vs. manufacturability
14. Reliability vs. service environment
15. Ultimate reliability

Special Course Material:
All attendees will receive a complimentary copy of Environment-Friendly Electronics - Lead Free Technology, Electrochemical Publications, Ltd., Great Britain (List price $238).

Who Should Attend?
The course provides a working knowledge to all who are interested in the ultimate reliability of Pb-Free electronic packaging and systems; also designed for those who desire the scientific basis on top of the practical know-how.

Dr. Hwang has conducted pioneering lead-free R&D and hands-on production implementation and contributed to SMT manufacturing since its inception. She has held executive positions with Lockheed Martin, Sherwin Williams, SCM Corp. and IEM Corp. She also serves as an advisor to major OEMs, EMS companies and the U.S. government, providing solutions to challenging problems in production defects, field failure and reliability issues. Her formal education includes Ph.D., M.S., M.A. and B.S. degrees in materials science and engineering, chemistry, and liquid crystal science, respectively. Dr. Hwang has received numerous honors and awards for her work, including being named “R&D-Star-to-Watch”, inducted into WIT International Hall of Fame, elected to National Academy of Engineering, and Honorary Doctoral degree. She is the author of 300+ publications and several textbooks, has lectured to 25,000+ professionals in professional development courses, and is a speaker at innumerable international events. She serves on the boards of many companies, civic groups and universities and is also an invited distinguished adj. professor for the Engineering School of Case Western Reserve University, serving on the University’s Board of Trustees since 1996.

Monday, November 3, 2008

Wire Bonding in Microelectronics
Course Leader: Lee Levine, Process Solutions Consulting

Course Description:
Wire bond manufacturing defects range typically from about 1000 to 100 ppm, with exceptions to >10,000 and <50 ppm. In order to achieve the lower numbers in production, one must understand all of the conditions that affect both bond yield and reliability (since they are interrelated). This course will discuss many small- and large-wire bonding problems, as well as subjects of specific interest to hybrid/MCM device bonding. In addition, a number of advanced topics, such as high yield, fine pitch (towards 25 µm ball bond pitch), and bonding to flex will be covered. Newer developments are included along with a major discussion of wire bonding to multichip substrates, soft substrates, Cu-Lok and the special intermetallic problems occurring when fine pitch chips are used. Wire bond testing and metallurgy (covering both aluminum and gold bonds); intermetallic compounds in general; cratering; cleaning for high yield and reliability; failures resulting from electroplating; mechanical problems in wire bonding; new bond technologies and developments; how ultrasonic bonds are formed, and the metallurgy of gold and aluminum wire. It concludes with methods of making very low loops, implementing TAB and Flip Chip by using wire bonding/stud bumping techniques.

Special Course Materials:
All attendees will receive a complimentary copy of Wire Bonding in Microelectronics, by George Harman, McGraw Hill, NY, 1997 (List price $80), as well as complete course notes and explanations.

Who Should Attend?
Engineers in R&D, QA, QC, manufacturing, process development, and advanced technicians. It is assumed that participants have some familiarity with wire bonding and general device assembly technologies.

Mr. Levine’s experience includes 20 years as Principal and Staff Metallurgical Process Engineer at Kulicke & Soffa and Distinguished Member of the Technical Staff at Agere Systems. Currently he consults for his own company, Process Solutions Consulting, providing process consulting, yield improvement, SEM, EDS and Metallography services to the microelectronics industry. He has been awarded 4 patents, published more than 50 technical papers, and won the 1999 John A. Wagnon Technical Achievement award from the International Microelectronics And Packaging Society, IMAPS. Major innovations include copper ball bonding, loop shapes for thin, small outline packages (TSOP and TSSOP, and CSPs) and introduction of DOE and statistical techniques for understanding assembly processes. He is a Fellow, V.P. of the Keystone Chapter, and V.P. of Technology for IMAPS. Mr. Levine is a graduate of Lehigh University, Bethlehem, PA, where he earned a degree in Metallurgy and Materials Engineering.

High-Performance Thermal Management Materials
Course Leader: Dr. Carl Zweben, Thermal Management Materials Consultant

Course Description:
The need for advanced thermal management and packaging materials is highlighted in many roadmaps. In response, there have been revolutionary advances in the last few years. There are now many low-CTE, lightweight materials with thermal conductivities up to 1700 W/m-K (over 4X copper). Advanced materials can reduce component and system cost. There is great potential for thermal interface material performance. They can tailor PCB CTE, potentially eliminating the need for underfill. They also can increase PCB thermal conductivity, allowing heat removal from the bottom, as well as the top of a chip. Replacement of copper with Al/SiC in IGBT modules has eliminated solder joint failure, increasing life from 10 to 30 years. There are a large and increasing number of microelectronic and optoelectronic applications, including: substrates; PCBs; PCB cold plates; heat spreaders; heat sinks; microprocessor, RF and power packages; thermoelectric cooler heat sinks; laser diode and LED packages; displays; photovoltaic packaging; and detectors. This course covers the large and increasing number of high-performance thermal management materials, including properties, manufacturing processes, applications, cost, lessons learned, typical development programs, and future directions, including carbon nanotubes. The course also discusses traditional thermal management materials, of which many packaging engineers are unaware.

Who Should Attend?
Engineers, scientists and managers involved in microelectronic, optoelectronic, photovoltaic and MEMS/MOEMS thermal management and packaging design, production and R&D; packaging and thermal materials suppliers.

Dr. Zweben, now an independent consultant, directed advanced thermal management and packaging materials R&D for over 30 years. He was formerly Advanced Technology Manager and Division Fellow at GE Astro Space, where he was the first to use Al/SiC and other advanced materials in microelectronic, optoelectronic and photovoltaic packaging, and developed low-CTE PCBs. Other affiliations have included Du Pont, Jet Propulsion Laboratory and the Georgia Tech NSF Packaging Research Center. He was the first, and one of only two winners of both the GE One-in-a-Thousand and Engineer-of-the-Year awards. He is a Life Fellow of ASME, a Fellow of ASM and SAMPE, an Associate Fellow of AIAA, and has been a Distinguished Lecturer for AIAA and ASME. He has published and lectured widely on advanced thermal management and packaging materials.

Hermeticity Testing, RGA and “Near Hermetic” Packaging Concepts
Course Leaders: Thomas J. Green, TJ Green Associates LLC

Course Description:
Hermeticity of electronics packages including Hybrids, RF MMIC Modules, MEMS/MOEMS packaging for Military, Space and Medical device implant applications continues to be of critical importance.

This course begins with an overview of hermetic sealing processes. The course then examines the accepted leak test techniques as prescribed in Mil Standard 883 Test Method 1014. Issues with bomb times and pressures, measured leak rate vs. air leak rates, “one way leakers,” virtual leakers will be addressed, along with gross leak testing. In each case the focus will be on practical issues facing the industry. The basic science and applicability of both Optical Leak Test (OLT) and Cumulative Helium Leak Detection (CHLD) will be described with plenty of time for questions. The gas ambient inside the package is measured using Residual Gas Analysis. What is RGA (Residual Gas Analysis)? How does it relate to Hermeticity testing?

Packages made from polymeric materials as opposed to traditional hermetic seals (i.e., metal, ceramic, etc.) require a different approach from a testing standpoint. The problem is now one of moisture diffusion through the barrier and package interfaces. A brief review of the techniques and methods to evaluate a “non-hermetic” approach is presented.

Special Course Material:
All attendees will receive a complimentary copy of Hermeticity of Electronic Packages by Hal Greenhouse, Noyes Publications 2000 (List price $180), and a “Practical Guide to TM 1014” authored by the Instructor.

Who Should Attend?
This PDC is intended as an introductory to intermediate level course for process engineers, designers, quality engineers, and managers responsible for sealing, leak testing RGA results and “near hermetic” package testing.

Mr. Thomas Green is the principal at TJ Green Associates LLC ( a Veteran Owned Small Business focused on training and consulting for military, space and medical microelectronic devices. He has over twenty-five years experience in the microelectronics industry at Lockheed Martin and USAF Rome Laboratories. At Lockheed he was a Staff engineer responsible for the materials and manufacturing processes used in building custom high reliability space qualified microcircuits for military and commercial communication satellites. He has conducted experiments and presented technical papers at NIST and IMAPS on leak testing techniques and optimization of seam welding processes through statistical DOE methods. Tom is an IMAPS Fellow and active leader in the society. He has a B.S. in Materials Engineering from Lehigh University and a Masters from the University of Utah.

Introduction to Microelectronics Packaging
Course Leader: Phillip G. Creter, Creter & Associates

Course Description:
This up-to-date and constantly revised course provides an introduction to microelectronics packaging using simple terms for ease of understanding. No prior knowledge of microelectronics required. Emphasis will be on visual aids including actual samples, and a variety of photos and figures. The attendee will learn basic packaging definitions and current terminology of materials, processes and equipment, including: thick/thin film technology and nanotechnology as applied to microelectronics and semiconductor processing.

2009 updates include MEMS, SiP, RFID, Thru-Silicon Vias, Thin Chips/3D/WLP, Green Technology, and new metal/metal oxide transistors. An overview of major industry leaders includes Intel’s 32nm process, IBM’s C4NP, Freescale’s RCP, Samsung’s TSV, and Amkor’s SiP/SoP and StatsChipPac’s PoP.

Technical topics with video clip highlights include WLP, FC bumping, dicing, substrates (ceramic, conductors, dielectrics, co-fired, LTCC); components – passives, actives, chips vs. discrete SMT components and flip chip; assembly including details of basic package types (SO, LCC, CERDIP, QFP, QFN, BGA, stacked die, and plastic over molded lead frame). Also covered are photolithography, die attach, wire bonding, micro-soldering, plating, rework & repair, final assembly including elements of visual inspection, test, hermeticity, reliability, failure analysis, design, cleanrooms and handling techniques.

A 200+ page invaluable class handout includes an expanded glossary and list of references.

Who Should Attend?
Designed primarily for entry-level R&D/manufacturing/quality technicians/engineers or others with little knowledge of microelectronics packaging but also includes topics of interest for senior engineers’ overview, sales/marketing, purchasing, safety and management.

Phillip Creter has 30+ years of microelectronics packaging experience and is a Life member of IMAPS. He was elected a Fellow of the Society, National Treasurer and President of the New England Chapter (twice). He received a BS in Chemistry from Suffolk University and has published numerous papers, holds a U.S. patent, has given many technical presentations (received IMAPS Best Paper of Session award), and chaired technical sessions for symposia. He is currently a consultant with experience at Polymer Flip Chip Corporation, Mini-Systems, GTE and Itek Corporation. His past positions include GTE Microelectronics Center Manager, Process Engineering Manager, Process Development Manager, Materials Engineering Manager and Manufacturing Engineer. Phil currently teaches courses at microelectronics events and on the Internet. He is also a certified instructor currently teaching for the Department of Homeland Security.

Technology of Screen Printing
Course Leader: Arthur Dobie, SEFAR Printing Solutions, Inc.; David Malanga, Heraeus Inc., Thick Film Materials


TSV and Other Enabling Technologies for 3D IC Integration and WLP
Course Leader: Dr. John H. Lau, Hong Kong University Science & Technology

Course Description:
This course will elaborate on the latest development of through silicon via (TSV) and other relevant enabling technologies for 3D IC integration and packaging. Various TSV fabrication methods will be presented. The downstream processing and applications of TSV and other enabling technologies will be introduced. The relevant critical issues will be addressed as well. The scope covers overview of 3D packaging and IC integration, TSV forming and filling processes, deposition and role of insulation/barrier/adhesion layers, wafer thinning and handling, thin chip strength measurement and improving, microbump fabrication and assembly, low temperature C2C, C2W and W2W bonding, thermal-mechanical performance and thermal management, and TSV technology roadmap. Application examples, e.g., TSV for CMOS image sensor wafer-level packaging and 3D MEMS packaging will be provided. In this course, all these enabling technologies (except electrical) will be discussed in details. Most of the materials are based on the technical papers and books published by the instructors and others.

After completing this course, you will be able to:

  • Understand all important aspects of 3D IC integration and WLP
  • Understand the impact of TSV on 3D IC Integration and WLP
  • Know the 5 key process steps of TSV
  • Know the various fabrication methods of TSV
  • Understand the impacts of TSV interposers on thermal and mechanical performance
  • Know how to fabricate and characterize lead-free solder microbumps
  • Know how to assemble lead-free solder microbumps and their reliability
  • Know how to measure the strength of thin chips
  • Know how to do wafer thinning and thin-wafer handling
  • Know how to do low-temperature bonding for C2W and W2W stacking
  • Know how to do 3D MEMS packaging
  • Know how to do thermal management of 3D IC stacking
  • Integrating 3D IC integration and WLP into your SMT assembly

Course Outline:

  • Overview of 3D packaging and IC integration
  • TSV forming and process classification
  • Interfacial multilayers on the wall of TSV
  • TSV filling and planarization
  • Wafer thinning and thin-wafer handling
  • Low-cost microbumps (¡Â25µm pitch): fabrication, characterization, and assembly
  • Low temperature (<200oC) C2W and W2W bonding
  • Applications of TSV for 3D IC integration and packaging
  • Effects of TSV interposer on thermal-mechanical performance
  • Stress sensor for thin-chip strength measurement
  • TSV for CMOS image sensor wafer-level packaging
  • 3D MEMS packaging
  • Hot spots in thin chips for 3D stacking and thermal management
  • Critical issues in adopting TSV and 3D IC integration

Who Should Attend?
This short course is intended for professional engineers and technical managers in the industries who are involved in the design, materials, processing, assembly and reliability of advanced high density packages and scientists in research institutions, faculty members and postgraduate students in universities.

John Lau has been a visiting professor at HKUST since January 2009. Prior to that, he was with Institute of Microelectronics (IME, Singapore) for 2 years and HP/Agilent in US for more than 20 years. With more than 30 years of R&D and manufacturing experience, he has authored or co-authored more than 300 peer-reviewed technical publications and more than 100 book chapters, and given more than 250 presentations. He has authored and co-authored 16 textbooks on advanced packaging, solder joint reliability, and lead-free soldering and manufacturing. John earned his Ph.D. degree in theoretical and applied mechanics (University of Illinois) and three M.S. degrees in structural engineering, engineering physics and management science. He is an elected ASME Fellow, CPMT Distinguished Lecturer, and has been an IEEE Fellow since 1994.

Electronics, Energy, and the Environment

Course Leader: Harry K. Charles Jr., Ph. D.




Media Sponsors:
3D InCites - Media Sponsor
Advanced Packaging - Media Sponsor
Antennas Online - Media Sponsor
Equipment Protection - Media Sponsor
LED Journal - Media Sponsor
Semiconductor International - Media Sponsor
SolidState Technology - Media Sponsor
SMT - Media Sponsor
Thermal News - Media Sponsor
Wafer & Device Packaging and Interconnect - Media Sponsor

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