Images courtesy of:
Natel, Hesse & Knipps, and the San Jose Convention and Visitor Bureau.
Technical Program (Sessions)
Sessions (TA1 - TA5) | Afternoon Sessions (TP1 - TP5)
Sessions (WA1 - WA6) | Afternoon
Sessions (WP1 - WP5)
Sessions (THA1 - THA5)
Session | Program Grid (At-a-Glance) | Download Program PDF (13mb)
Tuesday, November 3, 2009 |
8:00 AM - 11:10 AM
Focused Sessions Track
Biomedical, Portable, and Consumer Applications
Chairs: John Mazurowski, Pennsylvania State University; Aicha Elshabini, University of Idaho
This session covers packaging in biomedical, consumer, portable, wireless, and telecom applications. Three dimensions are driving these fields - performance, cost, and volume.
Design and Process of 3D MEMS Packaging
John H. Lau, Hong Kong University Science & Technology (HKUST)
Benefits of LCP Usage on Air Cavity Packages and Electronic Components
Edson Ito, Ticona LLC
High Density Hearing Aid Chip Packaging
John Dzarnoski, Doug Link, Starkey Laboratories, Inc.
Physiological Monitoring by “Credit Card”
Harry K. Charles, Jr., Russell P. Cain, The Johns Hopkins University / APL
Multiple Gas Sensing Device Based On Nano-Porous Structure Of Zeolite Coated With Nile Red Dye
Son Nguyen, Joan Delalic, David Kargbo, Zameer Hasan, Temple University
Electromagnetic Interference (EMI)
Chairs: Terry Baum, L-3 Communications Cincinnati; Joan Delalic, Temple University
The adverse affects of electromagnetic interference on system performance can be reduced or eliminated by selecting the correct gasket material, shape or compression force, or by employing novel noise isolation structures, optimized filter designs, or new packaging technologies, as will be explained in today’s session.
Characterization of Extent of Cure of Form-in-Place Compounds
Hui Ye, Claudine Lumibao, Douglas S. McBain, Laird Technologies
Modeling and Analysis of a New Packaging Structure for Noise Isolation in Mixed-Signal Systems
Ivan N. Ndip, Stephan Guttowski, Herbert Reichl, Fraunhofer Institute for Reliability and Microintegration (IZM)
A Practical Shielding Effectiveness Evaluation of EcE Gaskets Incorporating Accelerated Aging
Douglas S. McBain, Tam Chau, Shelby Ball, Robert Antonio, Laird Technologies
The Hidden Component to High Speed Filter Design: The Footprint Influence
Akhlaq Rahman, Mark Broman, Mike Howieson, Thin Film Technology Corp.
Compression Force of a Form-In-Place (FIP) Conductive Elastomer EMI Shielding Gaskets: Theory, Measurement Techniques, and Application
Hui Ye, Claudine Y. Lumibao, Douglas S. McBain, Laird Technologies
A Study of the Influence of FIP Bead Shape on Compression Force in PCB/Shield Assemblies
Claudine Y. Lumibao, Hui Ye, Douglas S. McBain, Laird Technologies
Chairs: Jianbiao “John” Pan, California Polytechnic State University; Yan Zhang, Tessera Inc.
This session focuses on advanced materials for various microelectronics packaging including 3-D and MEMS packaging, high performance PCB, high power LED, and other high temperature applications.
Evaluation of Electroless Nickel Electroless Palladium (ENEP) Finish as a Replacement for Electroless Nickel Electroless Palladium Immersion Gold (ENEPIG) for Gold Wirebonding and SAC305 Solderability
Jaspreet Gandhi, Shijian Luo, Tom Jiang, Micron Technology Inc.
A New PCB Material for Low Skew Close Phase Matching in 10Gbps Differential System Designs
Edward P. Sayre, North East Systems Associates Inc.; Sunichi Maeda, KEI Systems, Inc.; Shinji Yoshikawa, Asahi-Kasei EMD Corporation
Development of High Performance Optical Silicone for the Packaging of High Power LEDs
Yeong-Her Lin, Jiun Pyng You, Frank G. Shi, University of California-Irvine
Fabrication of 3-D Microstructures with Permanent Dielectric Dry Film
Tobias Baumgartner, Karin Hauck, Kai Zoschke, Michael Töpper, Hidetaka Uno, Werner Liebsch, Hao Yun, Mats J. Ehlin, Karl H. Dietz, Fraunhofer IZM Berlin
The Effect of Test Conditions on TIM Reliability Testing, and the Introduction of an Improved Thermal Interface Material
Andrew D. Delano, Natalie Merrill, Honeywell
Pb-Free Solder Materials and RoHS, Processes
and Reliability 1
Chairs: Wenning Liu, Pacific Northwest National Laboratory;
Sang Ha Kim, Apple
Reliability of lead-free solder materials are still challenging researchers and engineers. This session will focus on the reliability issues such as microstructures, whisker growth, and high temperature effects.
Correlation of Crystallographic Texture of Electroplated Sn and Sn-Alloy Films to the Growth of Tin Whiskers
Aaron Pedigo, Pylin Sarobol, John Blendell, Carol Handwerker, Purdue University; Peng Su, Cisco Systems, Inc.
Impact of SMT Assembly Process on Tin Whisker Risk Mitigation
Chieh-Ju Lee, Guhan Subbarayan, Li Li, Jie Xue, Cisco Systems Inc.; Peter Verbiest, Quyen Chu, Jabil Circuit
Comparison of Whisker Growth from Pressure Induced and Environmental Induced Whisker Growth Test Methods
Michael Osterman, University of Maryland – CALCE; Peng Su, Cisco Systems, Inc.
Case Study: Bright Tin Whisker Risk in Pb-Free Connector Applications
James Henzi, C. J. Lee, Cisco Systems, Inc.
Grain Orientation and Microstructure Evolution in Sn-Ag-Cu Solder Joints as a Function of Position in Ball Grid Array Packages
Tae-Kyu Lee, Kuo-Chuan Liu, Cisco Systems, Inc.; Thomas R. Bieler, Michigan State University
Effect of Germanium Addition to Sn3.5Ag Lead Free Solder System for Overall BGA Package Robustness Improvement
Eu Poh Leng, Tay Yee Han, Wong Tzu Ling, Min Ding, Nowshad Amin, Ibrahim Ahmad, A.S.M.A Haseeb Haseeb, Freescale Semiconductor, (M) Sdn. Bhd.
Characterization of Microstructure and Internal Strain (Stress) Evolution During Thermal Cycling
Bite Zhou, Thomas R. Bieler, Lauren Blair, Stefan Zaefferer, Tae-kyu Lee, Kuo-Chuan Liu, Michigan State University
Chairs: Alissa M. Fitzgerald, A.M. Fitzgerald & Associates, LLC; David Seeger, Semiconductor Research Corp.
This session will address recent developments in MEMS device-specific packaging technologies.
Low Cost and Reliable Packaging Technology for Stacked MCP with MEMS and Control IC Chips
Mitsuyoshi Endo, Yoshiaki Sugizaki, Akihiro Kojima, Yoshiaki Shimooka, Takeshi Miyagi, Takahiro Sogo, Susumu Obata, Yusaku Asano, Ikuo Mori, Hideki Shibata, Toshiba Corporation
Understanding Micro Via Fabrication Processes in Liquid Crystal Polymer (LCP) Substrate Using Mechanical Punching for RF-MEMS and Related Electronic Packaging Applications
Mohammad K. Chowdhury, Ajay P. Malshe, University of Arkansas; Li Sun, Shawn Cunningham, WiSpry Inc.
Fluorinated Residue Removal from MEMS Structure Sidewalls and Analysis with EDS and TSA
Lee R. Levine, Process Solutions Consulting; Robert Dean, Colin Stevens, Auburn University; Charles Bowers, Eco-Snow Systems LLC; Samuel Lawrence, Lehigh University
Design of Multiwall Carbon Nanotube Based Embedded Inductors
Bruce C. Kim, University of Alabama
Tuesday, November 3, 2009 | Afternoon Sessions:
1:55 PM - 5:40 PM
Focused Sessions Track
Automotive, Industrial, Harsh Environment Electronics Applications
Chairs: Pradeep Lall, Auburn University; Min Ding, Freescale Semiconductor, Inc.
In this session electronics applications in automotive, industrial and harsh environments have been examined. The session provides a well rounded overview of issues in harsh environments encompassing materials, design, and reliability. Aspects presented include thermo-mechanical and vibration reliability of lead-free solders, power conversion modules, liquid crystal polymer substrates, methods for health monitoring and component defect identification.
Reliability Evaluation of Lead-Free Solders for Automotive Applications
Yoonki Sa, Junghwan Bang, Jun Ki Kim, Sehoon Yoo, Changwoo Lee, Korea Institute of Industrial Technology (KITECH)
Prognostication for Impending Failure in Leadfree Electronics Subjected to Shock and Vibration Using Resistance Spectroscopy
Pradeep Lall, Ryan Lowe, Kai Goebel, Auburn University
Component Quality Defects: Identification, Investigation & Remediation
D. Michael Flint, Department of Defense
A High-Temperature, High Voltage Linear Regulator in 0.8ìm SOI BCDMOS
Chiahung Su, M. A. Huque, B. J. Blalock,
S. K. Islam, L. M. Tolbert, University of Tennessee
Effect of High Temperature Vibration on Lead-Free Solder Joint Reliability for Automotive Electronics
Sehoon Yoo, Yoonki Sa, Sehyung Lee, Sanghyun Kwon, Changwoo Lee, Korea Institute of Industrial Technology (KITECH)
A High-Temperature, High-Voltage SOI Gate Driver IC with High Output Current and On-Chip Low-Power Temperature Sensor
M. A. Huque, Leon M. Tolbert, Benjamin J. Blalock, Syed K. Islam, The University of Tennessee
Design Elements and Modeling
Chairs: Herman Chu, Cisco Systems, Inc.; Douglas C. Hopkins, University of Buffalo (SUNY)
Advanced design, materials and modeling applicable to hi-power LEDs, microprocessors and power semiconductors.
Thermal System Identification Analysis of Chip Interconnects to Facilitate DVFS Implementation
Sai Ankireddi, David Copeland, Sun Microsystems, Inc.
HotPak: A Tool for Rapid Thermal Mapping & Leakage Power Analysis of Flip-Chip Packages
Sai Ankireddi, David Copeland, Stanley Pecavar, Sun Microsystems, Inc.
Vaporizable Dielectric Fluid Cooling for IGBT and Power Semiconductor Applications
David L. Saums, DS&A LLC; Jeremy C. Howes, Abhijit Sathe, Parker Hannifin Corporation
Thermal Management of a Planar Magnetic Micro-Transformer
Yazdan P. Razi, Bob Roohparvar, Flextronics International
A Stochastic Coolability Analysis for a Microprocessor Considering Chip Power Fluctuation
Sai Ankireddi, Sun Microsystems, Inc.
Ceramic and LTCC Packaging
Chairs: John Menaugh, DuPont Microcircuit Materials; Larry Zawicki, Honeywell FM&T
The use of ceramics in the electronics industry continues to grow. Ceramic applications in electronics include sensors, actuators, electro-optical materials, packaging of semiconductors, and multilayer modules for RF and Microwave applications. The reasons for the increased use is that ceramics is chemically inert, provides a hermetic package around unpackaged ICs, capable of withstanding high temperatures and the TCE closely matches the performance of the semiconductors.
Characterization of LTCC Material at G-Band
Nurul Osman, Charles Free, University of Surrey
Thermomechanical Finite Element Techniques in Multilayer Ceramic Package Design
Mark Eblen, Franklin Kim, Nobuo Takeshita,
Andy Piloto, Kyocera America, Inc.
DuPont 9K7 LTCC Low Loss Dielectric Green Tape System for High Frequency Applications
Kenneth E. Souders, K. M. Nair, M. F. McCombs,
J. M. Parisi, DuPont Microcircuit Materials
Effect of Stress on the Densification of a Low-Temperature Cofired Ceramic-Filled Glass System under Constrained Sintering
Jau-Ho Jean, Jui-Chuan Chang, Yao-Yi Hung, National Tsing Hua University
LTCC Ka-Band Switch Matrix System for On-Orbit Verification
Stefan Humbla, J. Mueller, R. Stephan, D. Stoepel, G. Vogt, M. Hein, Ilmenau University of Technology
New Plateable Thick Film Silver Conductors
for DuPont 951 Green Tape™ LTCC
Michael A. Skurski, K. M. Nair, E.I. Dupont de nemours and Co., Inc.
Development of an AlN HTCC Multilayer System with a Tungsten Cofiring Metallization
Bernd Joedecke, Marco Fritsch, Fraunhofer IKTS Institute
Pb-Free Solder Materials and RoHS, Processes
and Reliability 2
Chairs: John Lau, Hong Kong University Science & Technology (HKUST); Li Li, Cisco Systems, Inc.
The reliability of lead-free solder materials is crucial to its application in packaging. This session will focus on the experimental and modeling study of the reliability of lead-free solder.
Environmental Conditions Impacts on Pb-Free Solder Joint
Bo Liu, Tae-Kyu Lee, Kuo-Chuan Liu, Cisco Systems, Inc.
Lead-Free Solder-Joint-Reliability Model Enhancement
Jian Miremadi, Greg Henshall, Aileen Allen, Elizabeth Benedetto,
Michael Roesch, Hewlett-Packard Company
Advanced Lead-Free Server Hardware Reliability Test Methods:
Power Age / Power Cycling and Four Point Bend Test Data Results
Matthew S. Kelly, Timothy Younger, David Braun, IBM Corporation
Effect of Temperature Cycling Parameters on the Durability
of Pb-Free Solders
Michael Osterman, Preeti Chauhan, Michael Pecht, University of Maryland - CALCE
Au-Ge Based Candidate Alloys for High-Temperature Lead-Free
Vivek Chidambaram, John Hald, Jesper Hattel, Technical University of Denmark
The Failure Process of the C4 Bumps under Current Stressing
Shigeaki Suganuma, Shinko Electric Industries Co., Ltd.
Effects of Solder Voids on Thermal and Reliability Performances
of PQFN Packages
Youmin Yu, Victor Chiriac, Hai Bin Xu, Sean Xu, Freescale Semiconductor (China) Ltd.
Wirebonding and Stud Bumping
Chairs: Patrick Story, International Rectifier Corporation; Faina Zaslavsky, Crane Electronics Group
This session is filled with a significant amount of original work including: copper on gold ball bump bonding, ultra-high frequency bonding, and copper wire bonding. In addition, key factors such as: cost, performance, miniaturization, and reliability are discussed in detail.
Second Bond Stitch Width Model as a Trend Solution to LEAD Width Reduction
Tomer Levinson, Menache Alon, Shi Fei, Kulicke & Soffa Bonding Tools
Accelerated Characterization of Bonding Wire Materials
Andrew Pequegnat, Michael Mayer, University of Waterloo; John Persic, Microbonds Inc.
Practical Considerations for PowerRibbon® Bonding of Hybrid
Richard Elliott, Orthodyne Electronics
Room Temperature Wedge-Wedge Ultrasonic Bonding using Aluminum Coated Copper Wire
Matthias Petzold, Robert Klengel, Rainer Dohle, Holger Schulze, Frank Rudolf, Fraunhofer Institute for Mechanics of Materials Halle
Numerical Analysis of Ultra-High Frequency Wire Bonding
Michael Mayer, Yan Huang, University of Waterloo
Study of Formation and Growth of Intermetallic Compound in Cu-Au and Au-Al Systems for COG Bonding
Yingwei Jiang, Sonder Wang, Ronglu Sun, Weimin Chen, Freescale Semiconductor Inc.
Odd Form Factor Package Wire Bonding Case Studies
Daniel D. Evans, Jr., Palomar Technologies, Inc.
Wednesday, November 4, 2009 | Morning Sessions:
8:00 AM - 11:40 AM
Focused Sessions Track
Emerging Technology Track
Chairs: Sang Liu, Huawei Technologies Co., Ltd.; Virgil Ganescu, ITT
This session addresses a wide variety of topics ranging from component level challenges all the way to consumer applications. In addition to the packaging and assembly issues addressed herein, modeling the thermal stress as well as the cooling of a high-power optoelectronic component are presented.
Solder Jetting - A Versatile Packaging and Assembly Technology for Hybrid Photonics and Optoelectronical Systems
Erik Beckert, Thomas Oppert, Ghassem Azdasht, Elke Zakel, Thomas Burkhardt, Marcel Hornaff, Andreas Kamm, Ingo Scheidig, Ramona Eberhardt, Andreas Tünnermann, Frank Buchmann, Fraunhofer-Institute for Applied Optics and Precision Engineering
The Challenge in Packaging Microelectronics and Optoelectronics
Rick Stevens, Brian Uhlhorn, Kevin Thorson, Lockheed Martin Corporation
Micron Level Placement Accuracy for Wafer Scale Packaging of P-Side Down Lasers in Optoelectronic Products
Daniel D. Evans, Jr., Zeger Bok, Palomar Technologies, Inc.
Modeling Thermal Stresses in an Optoelectronic Adhesive
S. Cimmerelli, R. A. Pearson, Lehigh University
Laser Scribing of Copper/Low-k Dielectric Semiconductor Materials by Nanosecond and Ultrafast Pulsewidth Lasers
Andy Hooper, David Barsic, Haibin Zhang, Jim O’Brien, Electro Scientific Industries
Thermal Management Materials
Chairs: David Saums, DS&A LLC; Eric Huenger, Dow Corporation
Materials provide a critical and increasingly-important role in semiconductor package thermal management and overall electronics thermal control. This session covers a number of topics within the area of thermal management materials.
Indium Thermal Interface Material Manufacturability and Reliability
Sean Too, Mohammad Khan, Jacquana Diep,
Edwin Goh, Xiaole Zhao, Kee-Hean Keok, AMD
Evaluation of a Novel Lead Free Dielectric Material on Aluminum Substrates
Michael Creamer, Samson Shahbazi,
Mark Challingsworth, David Malanga, Jim Wood, Heraeus
High-Quality CO2 Laser Machining of LTCC Structures for Thermal Management of a Group of Single-Emitter Laser Diodes
Alberto Campos Zatarain, Howard J. Baker, Denis R. Hall, Marc Desmulliez, Heriot-Watt University
High Temperature Forging to Fabricate Fully Densified Copper Tungsten and Copper Molybdenum Heat Sink Materials
Guosheng Jiang, Changsha Saneway Electronic Materials, Co Ltd.; Zhifa Wang, Huabo Wu, Central South University; Ken Kuang, Torrey Hills Technologies, LLC
Component Level Testing of Application Specific Conditions for Pressure Sensitive Adhesive Thermal Interface Materials
Herman Chu, Anusha Selvakumar, Cisco Systems, Inc.
Process and Reliability Advantages Lower Total Ownership Cost of Eutectic Die Attach
Amanda Hartnett, Indium Corporation; Steve Buerkie, Palomar Technologies
Wafer Level/CSP Packaging Requirements
Chairs: Robert Forman, Dow Corporation; Lyndon Larson, Dow Corning Electronics
Session pertains to concepts in wafer level packaging approaches and chip-scale packaging requirements.
Reliability Study of the Bump on Flexible Lead for Wafer Level Packaging
I. Eidner, Technical University of Berlin; M. J. Wolf, O. Ehrmann, H. Reichl, Fraunhofer Institute for Reliability & Microintegration IZM
Development of Wafer Level Embedded SiP (System in Package) for Mobile Applications
Gi-Jo Jung, Byoung-Yool Jeon, In-Soo Kang, Nepes Corporation
Enhance Solder Ball Shear Value in SiP
Dyi-Chung Hu, Eric Wei, Advanced Chip Engineering Technology Inc.
Micro-Springs for Microprocessor IC Packaging and Testing
E. W. Chow, D. DeBruyker, C. Chua, B. Cheng,
K. Sahasrabuddhe, Palo Alto Research Center (PARC); I. Shubin, J. Cunningham, Y. Luo,
A. Krishnamoorthy, Sun Microsystems
Advanced Wafer-Level Integration Technology with Ultra Fine Pitch Redistributed Layers between Heterogeneous Devices
Yutaka Onozuka, Hiroshi Yamada, Atsuko Iida, Kazuhiko Itaya, Hideyuki Funaki, Toshiba Corporation
On the Use of Nanoscale Materials to Toughen Model Epoxies
Raymond Pearson, P. Dittanet, L. Bacigalupo,
Y.-L. Liang, R. Oldak, Lehigh University
Impact of Thermal History on Gap Filling
Capability of Die Attach Film
Yeqing Su, Wei Shen, Baoguan Yin, Vitto Huang, Denis Bai, Weimin Chen, Sonder Wang, Freescale Semiconductor
Package Reliability Testing
Chairs: F. Patrick McCluskey, University of Maryland (CALCE); Mudasir Ahmad, Cisco Systems, Inc.
Issues relating to packaging material selection, design, construction, assembly and testing, to ensure long term packaging reliability. Reliability encompassing temperature cycling, aging, mechanical testing (bend, shock, drop, vibration, etc.) and other related activities.
Reliability Impact of Defects in Lead-Free BGA Solder Joints - A Systematic Study
Anurag Bansal, Kuo-Chuan Liu, Jie Xue, Cisco Systems, Inc.
A Test Platform for the Thermal, Electrical,
and Mechanical Characterization of Packages
Justin Schauer, Nathaniel Pinckney, Sun Microsystems
Use of the Skin Effect for Detection of Interconnect Degradation
Michael H. Azarian, Daeil Kwon, Michael Pecht, University of Maryland – CALCE
Effects of PCB Design Variations on the Reliability of Lead-Free Solder Joints
Hongtao Ma, Kuo-Chuan Liu, Dong Hyun Kim, Cherif Guirguis, Cisco Systems, Inc.
Warpage Control of Thermally Enhanced PBGA Package with Internal Heat Spreader during Reliability Test
Min Ding, Sheila Chopin, B. Y. Low, James Guajardo, Harold Downey, Freescale Semiconductor, Inc.
Statistical Analysis of Pb-Free BGA Solder Joint Reliability Data
Weidong Xie, Michael Tsai, Kuo-Chuan Liu, Cisco Systems, Inc.
A Coupling between Electromigration (EM) and Kirkendall Effect (KE) in Sn-3.5Ag/Cu Solder Joint
Jin Yu, H. W. Kang, Y. Jung, KAIST
3D Packaging Approaches
Chairs: James J.-Q. Lu, Rensselaer Polytechnic Institute; Peng Su, Cisco Systems, Inc.
This session focuses on the latest achievement in 3-D packaging processing technologies, including Through-Silicon-Via (TSV) materials and processes.
Lithography and Wafer Bonding Solutions for 3D Integration
Thorsten Matthias, Eric Pabo, Dustin Warren, Bioh Kim, Paul Lindner, Markus Wimplinger, EV Group
A Cost-Effective PVD Thin Film Deposition System for the 3-D TSV Barrier/Seed Application and Beyond
Alex Wang, Biju Ninan, Pramod Gupta, Ravi Mullapudi, Tango Systems, Inc.
Dispensable 3D Interconnects; A Near TSV Back End Packaging Solution
Jeff Leal, Marc Robinson, Vertical Circuits
Wafer Level Batch Fabrication of Silicon Microchannel Heat Sinks and Electrical Through Silicon Vias for 3D ICs
Jesal Zaveri, Calvin King Jr., Hyung Suk Yang, Muhannad S. Bakir, Georgia Institute of Technology
Critical Issues of 3D High-Performance Interconnects
John H. Lau, Hong Kong University Science & Technology (HKUST)
Chairs: Rajen Chanchani, Sandia National Laboratory; Linus Jauniskis, Foster-Miller, Inc.
In this session, there are seven papers, discussing some of the forefront emerging technologies relating to ultra-thin microelectronics, wafer thinning, thermal management, and advanced packaging technologies.
Development of Ultra-Thin Microelectronic Multichip Assemblies
Harry K. Charles, Jr., A. S. Francomacaro, S. J. Lehtonen, A. C. Keeney, G. V. Clatterbaugh, C. V. Banda, The Johns Hopkins University / APL
Thermal Characteristics for LSI Embedding Build-up PWBs
Shin-ya Amakai, Shuji Sagara, Dai Nippon Printing Co., Ltd.
TLS-Dicing - The Key to Higher Yield and Throughput for Thin Wafers
Hans-Ulrich Zuehlke, Gabriele Eberhardt, Patrick Mende, Ronny Ullmann, Jenoptik Automatisierungstechnik GmbH
Active Demonstration of a Passively Self-Aligned, Multi-Chip Package using Proximity Communication in a Switching Fabric
John E. Cunningham, A. V. Krishnamoothy, I. Shubin, H. Eberle, N. Gura, D. Hopkins, Sun Microsystems
Advanced Packaging for Solid State Light Emitting Diode (SSLED) Lighting
Rajen Chanchani, Nathan Young, Sandia National Laboratories
Bridging the Manufacturing Gap Between Macro and Micro to Build Miniature Devices with Complex Geometries and Multiple Materials
Arthur L. Chait, EoPlex Technologies, Inc.
A Direct Fanning-Out Packaging Technology using Cu Base Plate for Embedded Fine-Pad-Pitch LSI
Hideya Murai, Kentaro Mori, Kouji Soejima, Yuuji Kayashima, Takehiko Maeda, Takuo Funaya, Katsumi Kikuchi, Katsumi Maeda, Masaya Kawano, Shintaro Yamamichi, NEC Corporation
Wednesday, November 4, 2009 | Afternoon Sessions:
1:35 PM - 5:25 PM
Information for Session WP6 - Interactive Poster Session - can be found here
Focused Sessions Track
Packaging for Extreme Environments
Chairs: Fred Barlow, University of Idaho; Anwar A. Mohammed, Infineon Technologies
Packaging electronic devices and systems that must operate effectively under extreme environmental conditions is a growing and important area. This session provides a discussion of the key challenges and advancements that represent the state of the art in both extremely hot and cold environments.
Hermetic Packaging for Highly Space-Constrained Applications
Thomas F. Marinis, Caroline K. Bjune, Joseph W. Soucy, Charles Stark Draper Laboratory
CCA Passive Vibration Damper
Joe Vecera, Bennion Cannon, Honeywell
Packaging of High Temperature 50 kW SiC Motor Drive Modules for Hybrid-Electric Vehicles
Jared M. Hornberger, B. McPherson, J. Bourne, R. Shaw, B. Reese, A. Lostetter, R. Schubach, B. Rowden, A. Mantooth, S. Ang, J. Balda, K. Okumura, T. Otsuka, Arkansas Power Electronics International, Inc.
Miniature Probe for Solar System Exploration
Jarrod Reddick, Ball Aerospace
Encapsulation of Power Modules for Extreme Environments
Fred D. Barlow, Gona Rao, Srikanth Kulkarni, Aicha Elshabini, University of Idaho
A 6.5kV IGBT Development Module for Renewable Energy Systems
Gangyao Wang, North Carolina State University; Yu Du, Yuanbo Guo, Douglas C. Hopkins, Subbashish Bhattacharya, Alex Q. Huang, University of Buffalo
Microwave and RF Applications
Chairs: Ron Barnett, National Instruments; Steve Lehnert, Space Systems Loral
Ceramic and organic Microwave Packaging from 1-36GHz. Includes: low loss and low cost techniques, novel means of vertical interconnects, deQing with NanoParticals, and removing heat from MMIC’s.
Ka-Band High Power Near Hermetic Package using Liquid Crystal Polymer
Cheng Chen, Kunia Aihara, Mark McGrath, Yiren Wang, Anh-Vu Pham, University of California, Davis
Design of Low Phase Noise Cross-Coupled VCO in 90nm CMOS Technology
Lu Wang, Prasanta Ghosh, Syracuse University
Column Distribution Analysis and RF Characterization of High-Density Vertical Interconnections Created by Magnetically Aligned Anisotropic Conductive
Sungwook Moon, William J. Chappell, Purdue University
Substrate Integration of Widely Tunable Bandpass Filters
Hjalti H. Sigmarsson, Himanshu Joshi, Sungwook Moon, Dimitrios Peroulis, William Chappell, Purdue University
Microwave Characterization and Performance Assessment of Polymer-Magnetic Nanocomposites using Transmission-Line Based Microwave Resonators
Cesar A. Morales-Silva, Julio Dewdney, Susmita Pal, Sayan Chandra, Kristen Stojak, Hariharan Srikanth, Thomas Weller, Jing Wang, University of South Florida
Invited Session on Intelligent Uses of Precious Metals in Microelectronics
Chairs: Andy London, Heraeus Materials Technology LLC
Precious Metals make up a major cost in the packaging industry. This session reviews ways to use or handle precious metals in a cost effective and intelligent way.
Precious Metal Leasing
Paul Angland, HSBC Bank USA, National Association
Cost Effective use of Gold in Thick Film Conductors
Samson Shahbazi, Mark Challingsworth, Heraeus, Thick Film Materials Division
Optimization of Silver Powder Production through Factorial Experimentation
Kirk McNeilly, Louis A. Johnson, Metalor Technologies USA - Advanced Materials Division
Gold: The High Reliability Choice in Semiconductor Packaging
Lee R. Levine, Process Solutions Consulting; Richard Holliday, World Gold Council
Design for Reliability
Chairs: Kuo-Ning Chiang, National Tsing Hua University; Ilyas Mohammed, Tessera Inc.
With more integration across chips, packages and system through 3D packaging, SiP and multi-chip modules, testing for failure and detecting the failure mechanism are very important. Design is the best stage to systematically implement a reliability improvement and monitoring scheme. In this session, papers that discuss designs to improve and quantify reliability will be presented.
A Design Rule for 3D TSV Technology to Avoid Radial and Axial Cracking in Silicon Interposer
Zhen Zhang, Microsoft Corp.
Nickel Palladium-Based Pads for Higher Reliability in Au Wire
Asaf Hashmonai, Alon Menashe, Kulicke & Soffa Industries Inc.; Tom Thieme, Atotech
Reliability Comparison of WLCSP Structures Fabricated with Polyimide, BCB, and ALX Spin-on Polymer Dielectrics
Alan Huffman, Jeff Piascik, RTI International; Philip Garrou, Microelectronic Consultants of NC; Dan Baldwin, Engent; Rex Anderson, Amkor Technology Inc.
Continuous Au/Sn Layer Formation in Tinned & Wicked Thick-Au/Ni Plated Printed Circuit Card
Jeffrey Jennings, Donna Gerrity, Carolyn Smith, Harris Corporation
Interconnection Design and Impact Life Prediction of Wafer Level Package Subjected to Drop Impact
Kuo-Ning Chiang, Chan-Yen Chou, Chao-Jen Huang, Tuan-Yu Hung, National Tsing Hua University
Silver Epoxy Filled Via Analysis for High Reliability RF MCM
Joseph J. Kreuzpaintner, Karen Wooldridge, Donna Gerrity, William Clark, Hector Deju, Harris GCSD
Monte Carlo Simulation of Void Concentrations in Surface Mounted Solder Joints
Jacob Burke, John W. Evans, NASA
3D Packaging Approaches: Applications, Assembly
Chairs: Charlie Banda, Laboratory for Physical Sciences; Leonard Schaper, University of Arkansas
3D packaging approaches offer high degrees of integration with increased I/O bandwidth densities, which enable novel architectures. This session focuses on design, assembly and applications of 3D assemblies.
Challenges of Supporting 3D IC and 3D Package Integration in the Design Space
William Acito, Cadence Design Systems
Multi-Components Integration in a SIP
Benoit Haent Jens, Alain Leborgne, Erwan Fourn, M’Hamed Drissi, Gérald Chretieny, Haent Jens, Vectrawave, IETR
Design and Reliability of µPILR® Package-on-Package (PoP)
Ilyas Mohammed, Phil Damberg, Tessera, Inc.
Design and Fabrication of a Flexible Multi Layer RF Micro Sensor using a Self Assembly Method
Bernd Scholz, North Dakota State University
High Accuracy Placement Enabling High Density and Fine Pitch in 3D-IC with High Density TSV, with Chip to Wafer (C2W) Bonding Approach
Gilbert Lecarpentier, Jean Stephane Mottet, Smart Equipment Technology (SET); François Marion, CEA/LETI
Side Mount Package (SMP) for Ultra-High Density Memory Applications
Myung Jin Yim, Jason Brand, Chan Yoo, Numonyx Inc.
3D Integration Technologies for Miniaturized Tire Pressure Monitor System (TPMS)
Nicolas Lietaer, Maaike M. V. Taklo, Armin Klumpp, SINTEF ICT; Peter Ramm, Fraunhofer IZM, Munich Division
Information for Session WP6 - Interactive Poster Session - can be found here
Thursday, November 5, 2009 | Morning Sessions:
8:00 AM - 12:00 PM
Focused Sessions Track
LED and Photovoltaic Cell Packaging
Chairs: Min Ding, Freescale Semiconductor, Inc.; John Bolger, Department of Defense
Light emitting diodes (LED) and Photovoltaic (PV) solar cells are two distinct yet related technologies that deal with conversion between photons and electrical energy. Both of them have a great future in the green industry. Papers in this session cover various packaging topics of LED and PV cells, ranging from design, process and reliability, that enable better performance, improved thermal management, enhanced reliability and lower cost.
Near Chip Scale Package for High Power, Large Area LED
Paul J. Panaccione, Jay Liu, Luminus Devices, Inc.
Mechanical Analysis on Ball Bond Lifting of Wire Bonding in an LED Package for Backlight Unit
Jong Woon Kim, Shan Gao, Si Joong Yang, Ju Pyo Hong, Seog Moon Choi, Samsung Electro-Mechanics Co., Ltd.
Light Recycling High Power LED Module for Pico Projector
Yong Chi, Hong Kong Applied Science & Technology Research Institute
Determination of Optimal Component Spacing in a High Power Light Emitting Diode Array Assembly for Solid State Lighting
S. W. Ricky Lee, Y. S. Chan, Hong Kong University of Science & Technology
Void-Free Fluxless Solder Bonding of CPV Solar Cells
Wei Shi, Paul W. Barnes, David Muhs, SST International
Electrical Modeling, Signal & Power Integrity
Chairs: Ivan Ndip, Fraunhofer Institute for Reliability and Microintegration (IZM); Judy Priest, Cisco Systems, Inc.
In this session, electrical modeling, simulation and measurement techniques for signal and power integrity will be presented.
Parallel Algorithms for Power and Signal Integrity Analysis of High-Speed Designs
Ram Achar, Carleton University
Full-Wave Electromagnetic Characterization and Measurement of Single and Double Wire Bond Transitions on High Temperature Co-Fired Ceramics (HTCC) and Low Temperature Co-Fired Ceramic (LTCC) Substrates for Broadband Package Designs
Jerry Aguirre, Marcos Vargas, Jason Bast, David O’Neill, Steve Hira, Chen Wang, Kyocera America Inc.
Embedding the Footprint into Very High Frequency Surface Mount Components Through De-Embedded Optimization
Mark Broman, Thin Film Technology
Comprehensive Multilayer Substrate Models for Co-Simulation of Power and Signal Integrity
Renato Rimolo-Donadio, Heinz-Dietrich Bruens, Christian Schuster, Technical University of Hamburg-Harburg
Reduction of Signal Line to Power Plane Coupling Using Controlled-Return-Current Transmission Lines
A. Ege Engin, San Diego State University; Ivan Ndip, Fraunhofer Institute for Reliability and Microintegration (IZM)
Impact of Metal Fill on On-Chip Interconnect Performance
Vikas S. Shilimkar, Steven G. Gaskill, Andreas Weisshaar, Oregon State University
Chairs: C. Mike Newton, nScrypt Inc.; Andy Tseng, ASE (US) Inc.
Printed Electronics is a technology sector that has been enabled by the convergence of new high resolution printing technologies with roots in the graphics industries and advances in electronics materials technologies with roots in both cermet and polymer thick film. IMAPS has been at the forefront of printed technologies over the course of its entire history. The convergence of graphic printing and low temperature sintering nanomaterial technologies opens up whole new markets whether it be flexible display, RFID, sensors fabricated on substrates that include plastics and paper media. This session will look at these advances in printing, materials and low temperature processing of electronics.
Reliability of Flexible Substrates with Printed Conductors
Eric MacDonald, University of Texas at El Paso
Polymer Nanocomposites, Printable and Flexible Technology for Electronic Packaging
Rabindra N. Das, Frank D. Egitto, Bill Wilson, Mark D. Poliks, Voya R. Markovich, Endicott Interconnect Technologies, Inc.
Direct Print Technology Fabricated Mechanical Sensors
Xudong Chen, Patrick A. Clark, Kenneth H. Church, nScrypt, Inc.; Helena Ronkainen, Jukka Paro, VTT Technical Research Centre of Finland
Low Temperature Sintering Nanoparticle Inks for Printed Electronic Devices
Zhihao Yang, Zhiyong Xu, NanoMas Technologies, Inc.; Liwei Huang, Howard Wang, Binghamton University
New Technology for Near-Instantaneous Processing of High-Temp Materials on Low-Temp Substrates
Stan Farnsworth, NovaCentrix
Inkjet Printing Approach to Fabricate Non-sintered Dielectric Film with High Packing Density for 3D Package Integration Technology
Jihoon Kim, Hun Woo Jang, Hyo Tae Kim, Eunhae Koo, Young Joon Yoon, Jong-hee Kim, Korea Institute of Ceramic Engineering and Technology
Flip-Chip and Wafer Bumping: Processes and Reliability
Chairs: Bahareh Banijamali, Tessera Inc.; Timothy Younger, IBM
Flip-chip technology has been introduced in recent years which accommodate the ever increasing demands for higher performance and I/O density, while achieving smaller form factor and offering a cost effective solution. As the industry moves toward higher I/O density, die sizes require a significant reduction while accommodating the need for tighter and finer pitches. At the same time, increasing challenges for flip-chip are seen by the movement toward lead-free solder bumps and low-k dielectric layers. This session focuses on recent development on Flip-Chip processes and Reliability.
Coreless Substrates for High Performance Flip Chip Packages
Andy Tseng, Y. C. Ding, Jeson Chen, Lia Liao, Chien Liu, Alex Wang, Penny Yang, Bernd Appelt, ASE (US) Inc.
Flip Chip Process using the Cu-Sn-Cu Double-Pillar-Bump Bonding
Tae-Sung Oh, Jung-Yeol Choi, Min-Young Kim, Hongik University
Improvement in Flip-Chip Bonding by Reduction of Oxide using Hydrogen Radical
Tsuyoshi Nakashima, Koji Miyamoto, Michihiro Sato, Kanta Nogita, Akira Izumi, Kyushu Institute of Technology
Laser Based Assembly of Ultra Fine Pitch Bumped ICs for Die-on-Die Applications
Andrew J.G. Strandjord, Elke Zakel, Thomas Oppert, Ghassem Azdasht, Thorsten Teutsch, Jing Li, Pac Tech USA - Packaging Technologies
Electromigration Study of Fine-Pitch Flip-Chip Interconnect Technology
Piyush Savalia, Yoshikuni Nakadaira, Bahareh Banijamali, Ilyas Mohammed, Tessera, Inc.
Thermosonic Gold to Gold Interconnect (GGI) Flip Chip Bonding for 7mm2 Die
Hidetoshi Horibe, Philip Couts, TDK Corporation
High Performance Interconnects and Boards
Chairs: Roger Krabbenhoft, IBM; Ronald Jensen, Honeywell Solid State Electronics Center
Increasing packaging densities and performance requirements are driving a wide variety of innovative solutions throughout the industry. This session will examine advancements that facilitate the packaging and analysis of high performance first and second level interconnects solutions. We will review novel approaches addressing high speed board to board connection, electrical analysis and design techniques, as well as high performance materials and more environmentally friendly fabrication processes.
New Methodologies for Mechanical Mating Characterization of Surface Mount Technology Card to Board Interconnections
John Torok, William L. Brodsky, Shawn Canfield, Hien P. Dang, David L. Edwards, Eric J. McKeever, Arvind K. Sinha, Mark K. Hoffmeyer, IBM Corp.
Production Measurement of Frequency Dependent Attenuation
and Phase Constant of PCB Traces
John DiTucci, Brian Butler, Introbotics Corp.; Alina Deutsch, Roger Krabbenhoft, International Business Machines (IBM)
A Case Study of the Impact of Fabrication Processes on PCB Broadband Electrical Characteristics
Jason Lin, Steven Chen, Albert Huang, Ohio Huang, Compeq Manufacturing Co., Ltd.
A Comparative Study of Microstrip, Stripline and Coplanar Lines on Different Substrate Technologies for High-Performance Applications
Robert Erxleben, Ivan Ndip, Stephan Guttowski, Herbert Reichl, Fraunhofer Institute for Reliability and Microintegration, IZM
Newly Developed Low-Transmission-Loss Multilayer Materials
for PWBs Applied to High GHz Bands
Kenichi Ikeda, Hikari Murai, Yasuyuki Mizuno, Hiroshi Shimizu, Makoto Kato, Hitachi Chemical Co. America, Ltd.
A Novel Halogen Free and Low Dk/Df Laminate Material for High Frequency Application
Sanny He, Bill Weng, ITEQ Corporation
A Novel Green Process to Manufacture Ultra High Density Packaging Substrates
Chih-Kuang Yang, Princo Corporation
International Microelectronics And Packaging Society - IMAPS
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