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Natel - Premier Sponsor, Platinum
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IMAPS 2010 - Research Triangle
43rd International Symposium on Microelectronics
Bringing Together The Entire Microelectronics Supply Chain!

Professional Development Courses (PDCs)


All PDCs ran 8:00 am - 5:00 pm, unless otherwise noted

Do you want to broaden and strengthen your skills and knowledge, optimize your manufacturing processes, and integrate the latest advances in materials and technologies to maintain your strength in today’s competitive global market? The Technical Committee of IMAPS is pleased to present a comprehensive offering of Professional Development Courses that provide detailed information on topics of immediate interest to the Microelectronics and Packaging community.  So please be sure to choose from the 15 in-depth Professional Development Courses taught by recognized industry experts.  You will discover the following key ways that will benefit you.

  • Better understand the skills and knowledge necessary in today’s industry.
  • Be exposed to the rapidly expanding developments in new materials and technologies.
  • Consult with renowned authorities about your current R&D or manufacturing problems and challenges.
  • Learn new ways to identify, think about, and address your problems and opportunities.
  • Great opportunities to interact with industry experts and other course attendees.
  • Certificate of Attendance and much more…

Your PDC Registration Fee Includes:

  • Lunch on the day of your course
  • Refreshment breaks
  • All course materials
  • PDC Reception on Sunday evening (for Attendees & Instructors only)
  • Certificate of Attendance

PDC Lunches and Reception sponsored by:
Hesse & Knipps - Premier Sponsor, Gold

PDC Cancellation policy:

IMAPS reserves the right to cancel a course if the number of attendees is not sufficient.  You can transfer to a different course or we will refund you the corresponding amount.


Sunday, October 31, 2010

S1
High-Performance Thermal Management Materials

Course Leader: Dr. Carl Zweben, Thermal Management Materials Consultant
This Course Has Been Cancelled at the Request of the Instructor. This Course has been replaced with a new course:

S1 - NEW COURSE
Polymers for Electronic Packaging

Course Leader: Dr. Jeff Gotro, Innocentrix LLC

Course Description:
The course will provide an overview of polymers and the important structure-property-process-performance relationships for electronic packaging. The main learning objectives will be 1) understand how polymers are used in electronic packaging, 2) learn why specific chemistries are used depending on the application 3) learn the fundamentals of polymer characterization related to electronic packaging 4) develop a foundation in rheology and rheology issues in electronic packaging. Participants are invited to bring problems for discussion.

Who Should Attend?
Packaging engineers involved in the development, production, and reliability testing of electronic packages would benefit. Those interested in gaining a basic understanding of the role of polymers and polymer-based materials used in electronic packaging will also find this series valuable.

Dr. Jeff Gotro has over twenty-eight years experience in polymers for electronic applications and composites having held scientific and leadership positions at IBM, AlliedSignal, Honeywell, and Ablestik Laboratories. Jeff is a nationally recognized authority in thermosetting polymers and has received invitations to speak at prestigious Gordon Research Conferences (Thermosetting Polymers and Composites). He has presented numerous invited lectures and short courses at technical meetings, has over 60 technical publications and 21 patents/patent applications. Jeff was an Adjunct Professor at Syracuse University in the Dept. of Chemical Engineering and Materials Science from 1986-1993. Jeff is a member of the Product Development and Management Association (PDMA), American Chemical Society (ACS), the Institute for Management Consultants (IMC), the Forensic Expert Witness Association (FEWA), and the International Microelectronics and Packaging Society (IMAPS).

S2
TSV and Other Key Enabling Technologies of 3D IC/Si Integrations

Course Leader: Dr. John H. Lau, ITRI

Course Description:
3D integration consists of 3D IC packaging, 3D IC integration, and 3D Si integration, which will be discussed in this lecture. Emphases are placed on the key enabling technologies for 3D IC integration, such as designs and tests, known good die (KGD), TSV (through silicon via) forming and filling, wafer thinning and handling, thin chip/wafer strength measurement and improving, lead-free microbumping (≤15µm pitch) and assembly, low temperature C2C, C2W and W2W bonding, and thermal management. Useful characterization and reliability data for 3D IC integration will also be provided. The application of 3D IC integration such as CMOS image sensor, MEMS, LED, memory + logic, logic + logic, memory + microprocessor, active and passive interposers will be presented. Furthermore, the critical issues of TSV and 3D IC integration will be given and some potential solutions or research topics will be recommended. Finally, TSV manufacturing yield and hidden costs will be discussed and several roadmaps of 3D IC integration will be provided. All the materials are based on the technical papers published within the past 3 years by others and the instructor.

Who Should Attend?
If you (students, engineers, and managers) are involved with any aspect of the electronics, LED, MEMS, and optoelectronic industry, you should attend this course. It is equally suited for R&D professionals and scientists. You will receive more than 300 pages of handouts from the Instructor’s books, “Advanced MEMS Packaging” and “Reliability of RoHS Compliant 2D & 3D IC Interconnects.”

Dr. John Lau has been the ITRI Fellow of Industrial Technology Research Institute since January 2010. Prior to that, he was a visiting professor at HKUST for one year, Director of MMC Laboratory with IME for 2 years, and a Senior Scientist/MTS at HP/Agilent in the US for more than 25 years. With more than 30 years of R&D and manufacturing experience, he has authored or co-authored more than 300 peer-reviewed technical publications, more than 20 issued and pending patents, and given more than 250 lectures/workshops/keynotes worldwide. He has authored and co-authored 16 textbooks on advanced packaging, lead-free soldering and manufacturing, reliability of 2D & 3D IC interconnects, and 3D MEMS packaging. John earned his Ph.D. degree in theoretical and applied mechanics (University of Illinois) and three M.S. degrees in structural engineering, engineering physics and management science in North America. He is an elected ASME Fellow and has been an IEEE Fellow since 1994.

S3
MEMS Reliability and Packaging

Course Leader: Dr. Slobodan Petrovic, Oregon Institute of Technology

Course Description:
From accelerometers to biomedical devices, from pressure sensors to optical displays, and from tunable lasers to DNA sensors, MEMS (Microelectromechanical systems) technology is becoming integral part of modern life. One of the biggest challenges hampering further progress of MEMS devices is the development of effective packaging solutions. Packaging provides protective housing and interface between the mechanical structure performing its intended function and the environment.  Unlike electronic packaging where high density packaging methods have been developed, MEMS packaging evolution has been slow and not adequately meeting the diverse requirements of performance and reliability. As a result of great diversity in the type of MEMS devices the packaging considerations vary drastically not only from one device type to the next, but also among the different products in the same device category.  For some devices like accelerometers, packaging must provide complete isolation from the surrounding, while for others such as DNA sensors it must enable intimate contact with the environment or optical transparency as in display devices. It is, therefore, not surprising that there are no standards in MEMS packaging and that universal solutions may not be possible.

This is a survey course structured in such a way to provide a comprehensive overview of a broad array of packaging and reliability issues. The seminar will be divided in 3 major sections: packaging design considerations, packaging types, and reliability and failure analysis.

Who Should Attend?
This is a survey course structured in such a way to provide a comprehensive overview of a broad array of packaging and reliability issues. While some prior knowledge by the participants of MEMS in general is helpful, the packaging discussion will require a fairly detailed explanation of the principles of operation, fabrication methods, and materials used in building MEMS structures. The course is therefore open to participants with no prior MEMS knowledge and would provide a reasonably broad general introduction into the field. Because each MEMS design deserves its own distinctive packaging approach, packaging considerations will be, whenever possible, illustrated using specific device examples; and every opportunity will be used to demonstrate the uniqueness of a packaging solution and its interaction with a micromachined structure. Using this dynamic teaching method, besides learning in depth about packaging and reliability, the participants will have the opportunity to gain knowledge about MEMS in general through the eyes of a packaging and reliability specialist.

Dr. Slobodan Petrovic is an associate professor in Electrical Engineering and Renewable Energy Department at Oregon Institute of Technology in Portland, OR, where he teaches solid state electronic devices, applied electromagnetic, fuel cells, batteries, and renewable energy. Prior to joining Oregon Institute of Technology, Dr. Petrovic was associate professor at the Arizona State University, where he taught courses in MEMS, Sensors, and alternative energy. His research interests are in the areas of MEMS fuel cells, sensor media compatibility, hydrogen generation and storage, and nanocatalysts for energy applications. Prior to joining ASU Dr. Petrovic held appointments at Clear Edge Power (formerly Quantum Leap Technology) as a Vice President of Engineering; at Neah Power Systems as Director of Systems Integration; and Motorola, Inc. as a Reliability Manager. Dr. Petrovic has over 25 years of experience in MEMS, sensors, energy systems; fuel cells and batteries; industrial electrochemical processes; and catalysis. He has over 50 journal publications and conference proceedings; 2 book contributions and 24 pending or issued patents.

S4
Adhesion Fundamentals in Microelectronic Packaging

Course Leader: Dr. Raymond A. Pearson, Lehigh University

Course Description:
Polymers are widely used in electronic packaging.  The lack of adhesion can adversely affect reliability as well as package performance.  The intention of this course is to review the fundamentals of adhesion and apply them to interfaces found in Plastic-Quad Flat Packs (PQFP), chip-scale packages (CSP), Flip-Chip (FC) assemblies, and optoelectronic packages. Adhesion issues in molding compounds, die attach adhesives, optoelectronic adhesives, and underfill resins will be covered.  Also, recent trends in using nanotechnology to toughen epoxy resins will be reviewed. By the end of the course, you should know how to choose the proper tools to predict and measure adhesion. The instructor strongly recommends the following textbook: "Adhesives Technology for Electronics Applications: Materials, Processes, Reliability" by James J. Licari and Dale W. Swanson (ISBN 0-8155-1513-8).

COURSE OUTLINE:
1)   Discuss Course Objectives
2)   Review Microelectronic and Optoelectronic Packages (Brief)
3)         Discuss the Role of Chemical Forces in Adhesion
4)         Examine Extrinsic Deformation Mechanisms in Polymers
5)         Review Common Tests to Assess Adhesion
6)         Evaluate the Procedures Used to Form Adhesive Bonds
7)         Apply Interfacial Fracture Toughness Concepts to Gage Reliability
8)         Review the latest trends in epoxies containing nanosize fillers.

Who Should Attend?
Engineers, scientists and managers involved in the design, process and manufacturing of IC electronic components and hybrid packaging, electronic material suppliers involved in materials manufacturing and research & development.

Dr. Raymond A. Pearson joined the Materials Science and Engineering Department at Lehigh University in August of 1990 after obtaining his doctorate in Materials Science and Engineering from University of Michigan.  Prior to graduate school, Ray had worked for seven years with General Electric Company: from 1980-1984 as an associate staff member at GE's Corporate Research and Development Center in Schenectady, New York and from 1984-1987 as a materials specialist at GEPE's  Product Technology Center in Bergen op Zoom, the Netherlands.  His research interests include all aspects of processing, deformation, yield, and fracture of polymers.  He has extensively in the area of fracture mechanisms and adhesion. In 2001, Ray became Director of the Center for Polymer Science & Engineering. He has worked closely with organizations such as the Semiconductor Research Corporation and SEMATECH.

S5
RF/Microwave Hybrids: Basics, Materials and Processes

Course Leader: Richard Brown, Richard Brown Associates, Inc.

Course Description:
The demands for high frequency systems and products are rapidly growing, driven by wireless communication and automotive applications. New materials and technologies for hybrids are coupled to the continuing development of monolithic integrated circuits, MMICs,.  Thus, system and product designers are faced with the choice between hybrids and MMICs; i.e., complete system on a chip vs. hybrids with discrete devices, or more often, somewhere in-between.  Smaller packages are tempered by the necessity for impedance matching, which defines transmission line geometries, as well as the need for overall low system losses.  Thus, the design and manufacture of high frequency circuits is governed by materials and process strategies.

This course begins with a short, non-mathematical review of high frequency basics.  Next a comparison of MMICs and hybrids is presented.  The transmission line as the basic circuit component of RF and microwave hybrids will be reviewed.  Hybrid "waveguide" structures will be compared as they relate to transmission line properties.  The basic materials (conductors, dielectrics and substrates) and their properties will be introduced.  Their effect on impedance, circuit properties and performance will be discussed.  Processing technologies and strategies suitable for RF/microwave hybrids will be reviewed.  Selected packaging protocols, such as vias and bonding wires, will be discussed in light of their influence on RF/microwave performance.  At the completion of this course, attendees will have a better understanding of many of the critical materials and processing factors affecting high frequency circuit performance.

Who Should Attend?
This introductory course will benefit those associated with the RF and microwave arena.  In particular this course will benefit those with responsibility for design and manufacturing of RF/microwave hybrids.  Supervisors, engineers and technicians involved in product development, design and manufacture are encouraged to attend.

Richard Brown is a technical and engineering consultant in hybrids, with more than 30 years experience, encompassing thin and thick film, electroplating and substrate technologies.  He began his career at Bell Telephone Laboratories.  After joining RCA Solid State in 1968, he transferred in 1979 to the RCA Microwave Technology Center in Princeton.  In 1991, Mr. Brown joined an Alcoa Electronic Packaging technology team as program manager to implement thin film on high temperature co-fired ceramic for MCMs.  He has published extensively, authoring a chapter on Thin Film for Microwave Hybrids in "Handbook of Thin Film Technology", McGraw-Hill, NY, 1998, A. Elshabini-Riad and F. D. Barlow III, Eds.  In 1995, ISHM awarded him the prestigious John A. Wagnon, Jr. Technical Achievement Award.  His text, "Materials and Processes for Microwave Hybrids" was published in 1991 by ISHM, Reston, VA., and most recently, RF/Microwave Hybrids; Basics, Materials and Processes, Kluwer Academic Press, 2002.

S6
Plating Processes for High Reliability Microelectronic Devices

Course Leader: Fred Mueller, CEF, General Magnaplate Corp.

Course Description:   
• Provides a fresh overview of the chemistries of nickel, gold, and other precious metals that can be deposited by electro/eletroless plating on a variety of applications in the field of electronics;
• Presents methods for controlling the properties of plating solutions to maximize the deposits properties,
• Understand the use of Laboratory Controls including the Hull Cell and other lab equipment to test solutions;
• Highlight the engineering differences and troubleshooting problems in plating processes used in Plating for Electronics.

Who Should Attend?    
         
This course is intended as an introductory to intermediate level course for process engineers, quality engineers, and managers responsible for Electronic Finishing.

Mr. Mueller is a consultant and serves as a national certified instructor for the American Electroplaters and Surface Finishing Foundation (AESF).  He has over twenty-five years experience in the plating industry in printed circuits and plating for electronics.  He is currently the Corporate Quality Manager at General Magnaplate, Linden, NJ.  As a Chemist, Fred has conducted experiments and presented technical papers at SurFin on various topics in electroplating. He has served as Chairman of the Quality in Surface Finishing Committee and the Electro-forming Committee of the AESF.

S7
Hybrid Visual Inspection per Mil-STD-883

Course Leader: Thomas J. Green, TJ Green Associates LLC
This Course Has Been Cancelled

½ Day Course: 8:00 am - Noon
S8
Understanding Failure and Root-Cause Analysis in Pb-Free Electronics

Course Leaders: Craig Hillman, Greg Caswell, DfR Solutions

Course Description:
Increasing needs for performance, low cost, and a constant turnover in the electronics industry makes improving functionality a constant topic of interest. However, restrictions on machine performance (is your computer much better than the one 2 years ago?) and cost (how many more companies can move to China?) have made quality/reliability a critical differentiator in today’s crowded marketplace. This has become especially true during the transition to Pb-free and ‘green’ electronics, as those companies who fail to respond promptly to field/warranty issues can be expected to be left behind.

How to ensure optimum quality/reliability of your Pb-free product? It all starts with root-cause analysis, which is the fundamental exercise in understanding how electronic products can and will fail.

This course will provide an in-depth understanding of the failure mechanisms that are unique to Pb-free electronics and provides a comprehensive review of the tools and techniques to identify those mechanisms. Mechanisms are addressed based upon the packaging level in which they are affiliated, including component packaging, discrete components, printed circuit board, and interconnects. A physics of failure (PoF) based approach to the mechanisms are taken, with an outline of drivers of these mechanisms, including defect-driven, overstress, and wearout, and how an understanding of these stress-strength interactions can provide guidance on the appropriate corrective and preventative action. A wide variety of case studies, including red phosphorus in epoxy encapsulants, creepage corrosion in immersion silver, and solder joint failures, are provided as valuable teaching examples.

Who Should Attend?
This course is intended as an introductory to intermediate level course for designers, component engineers, quality engineers, reliability engineers, and their managers.

Dr. Craig Hillman is the CEO and Managing Partner of DfR Solutions (www.dfrsolutions.com), a world-leader in quality and reliability solutions for the electronics community. Dr. Hillman and his staff are at the forefront of failure investigations of systematic defects affecting the electronics industry, including flame-retardants in epoxy encapsulants and bulging of low-ESR electrolytic capacitors. Dr. Hillman and his team at DfR Solutions has also developed an extensive expertise in Pb-free reliability issues, best practices in design for reliability (DfR) and manufacturability (DfM), thermal/mechanical/electrical simulation, reliability predictions and test-to-field correlation, component derating/uprating, qualification of circuit boards and assemblies, and a wide variety of failure mechanisms (electronic packaging, component, printed board, interconnections, and connectors). Dr. Hillman has performed over 500 failure analysis investigations, published over 40 papers in the area of electronics quality and reliability, has presented to over 200 companies and organizations, including SMTAI, IEEE, MIT, and DMSMS. Dr. Hillman has a B.S. in Metallurgical Engineering and Material and Engineering and Public Policy from Carnegie Mellon, a PhD in Material Science from University of California - Santa Barbara, and a research fellowship from Cambridge University in England.

Greg Caswell, Senior Member of the Technical Staff, is widely recognized as a pioneer in surface mount technology (SMT) and has 35 years of experience in the electronics industry.   His experience encompasses all aspects of SMT manufacturing, circuit board fabrication and materials, advanced packaging (BGA, uBGA, CSP, Flip Chip, QFN), IC fabrication processes and materials, solder reflow, robotics, RoHS, and bonding utilizing specialized nanotechnology.   He has over 230 publications, including being the Editor of the 1st book on SMT, addressing NanoTechnology CMOS, CMOS/SOS, input protection networks, surface mount technology and advanced packaging.   Greg, a Past President of IMAPS, also directed the Advanced Technology Workshop program from 1989-2000, which produced workshops each year on different aspects of current and emerging packaging technologies. He has taught short courses on SMT at IMAPS National Symposiums as well as at local chapter events and he is a member of the National Technical Program Committee.  He is currently the Editor in Chief for Advancing Microelectronics magazine and the past Chair of the GBC. He has received the IMAPS Technical Achievement (1986), Fellow of the Society (1993), and Daniel C Hughes Memorial Award (1995).

½ Day Course: 1:00 pm - 5:00 pm
S9
LED Packaging Technology: Design, Materials, Processes, and Applications

Course Leader: Dr. S. W. Ricky Lee, Hong Kong University of Science and Technology

Course Description:
With the advancement of materials and packaging technologies, the illumination performance of light-emitting diode (LED) has been greatly improved in the past decade. In recent years high power white LEDs have reached efficiencies high enough to kick off serious discussion on using LEDs for solid state lighting (SSL). The performance of high brightness LED (HB-LED) has continued to grow from about 20 Lumens/Watt to over 100 Lumens/Watt. SSL has major advantages such as energy saving, environmental friendliness, and long operational life. LED Packaging is the major enabling technology to achieve these merits. This short course will review the technology trends of lighting sources and introduce the features of LED. Technical issues in packaging LED components such as interconnection, phosphor deposition, and encapsulation will be elaborated in detail. Considerations in thermal management will be addressed. Efforts will also be made to investigate optical design, analysis and characterization. Applications of HB-LED for general lighting will be illustrated. In addition, the technology roadmap and IP issues will be discussed.

Who Should Attend?
This short course is intended for scientists in research institutions, faculty members and postgraduate students in universities, professional engineers and technical managers in the industries that are involved or interested in the design, materials, processing, and assembly of high brightness LED for solid state lighting.

Dr. Ricky Lee received his Ph.D. degree from Purdue University. Currently he is Professor of Mechanical Engineering and Director of Center for Advanced Microsystems Packaging at the Hong Kong University of Science & Technology. His research activities cover flip chip technologies and wafer level packaging, through silicon vias and 3D packaging, LED and optoelectronics packaging, lead-free soldering and solder joint reliability. Ricky has substantial publications in international journals/conference proceedings and received several best paper awards. He also co-authored three books and owns three technical patents. Ricky is Fellow of IEEE and ASME, and Institute of Physics (UK). In addition, he was elected IEEE CPMT Distinguished Lecturer and received CPMT Electronics Manufacturing Technology Award. Furthermore, he serves as Editor-in- Chief of IEEE Transactions on Components & Packaging Technologies and Associate Editor of IEEE Transactions on Advanced Packaging. Ricky is the project leader to implement HB-LED SSL on Hong Kong subway trains.

Monday, November 1, 2010

M1
Modeling and Optimization of Electronic Packaging Structures for Signal and Power Integrity

Course Leaders: Dr. Ivan Ndip, Fraunhofer Institute for Reliability and Microintegration, IZM; Professor Ege Engin, San Diego State University; Dr. Antonio Ciccomancini Scogna, Computer Simulation Technology (CST) of America

Course Description:
Successful and low-cost design of electronic packages and boards requires (in addition to thermal and thermo-mechanical issues), a good understanding of the root causes of signal integrity (SI), power integrity (PI) and electromagnetic interference (EMI) issues, as well as methods to analyze, prevent or solve them.
The objective of this course is to provide methods for accurate and efficient electrical modeling, measurement and optimization of packages and PCBs, under consideration of SI, PI and EMI/EMC issues. Techniques for extracting the relative dielectric constant and loss tangent of packaging materials will also be discussed.  Finally, guidelines for optimizing the electrical performance of high-speed packages and PCBs will be provided.

COURSE OUTLINE:
• High-speed design challenges
• Modeling and optimization of packaging structures for SI
o Lossy transmission lines considering surface roughness and tapered cross section
o Signal vias considering their return-current paths
o Through silicon vias (TSVs)
• Modeling and optimization of packaging structures for PI
o Power-ground plane pairs and simultaneous switching noise (SSN)
o Electromagnetic band gap (EBG) structures and photonic crystal power/ground layers (PCPLs) for suppressing SSN coupling
• Modeling and extraction of relative dielectric constant and loss tangent of packaging materials.

Who Should Attend?
Engineers, scientists, researchers, designers and managers involved in the process of electrical modeling, layouts and/or design of single-chip packages, system packages (e.g., SiPs, SoPs, MCMs), PCBs and their interconnections.

Dr. Ivan Ndip obtained his M.Sc. and Ph.D. with the highest distinction (Summa Cum Laude) in electrical engineering from the Technische Universitaet Berlin, Germany. In 2002, he joined the Fraunhofer-Institute for Reliability and Microintegration (IZM) Berlin as a research engineer and in 2005 he was appointed Group Manager. Since then, he has been leading a team of research engineers/scientists and has also been responsible for developing and leading research projects at IZM that focus on design and optimization of RF/high-speed modules, integrated antennas and passive RF front-end components.

Dr. Ndip is also a lecturer at the Technische Universitaet Berlin, where he teaches graduates courses on the application of electromagnetic field and circuit theory for high-frequency design and measurement of electronic packaging structures.

He has more than 70 publications and has won 5 best paper awards at leading international conferences. Dr. Ndip is also a recipient of the Tiburtius-Prize, awarded yearly for outstanding Ph.D. dissertations in the state of Berlin, Germany.

Dr. Ege Engin received his B.S. and M.S. degrees in electrical engineering from Middle East Technical University, Ankara, Turkey, and from University of Paderborn, Germany in 1998 and 2001, respectively. He received his Ph.D degree with Summa Cum Laude from the University of Hannover, Germany in 2004.

Dr. Engin has worked as a research engineer with the Fraunhofer-Institute for Reliability and Microintegration in Berlin, Germany and at Georgia Tech. He is currently an Assistant Professor in the Electrical and Computer Engineering Department of San Diego State University. He has more than 60 publications in the areas of signal and power integrity modeling and simulation and 4 patent applications. He has co-authored the book "Power Integrity Modeling and Design for Semiconductors and Systems," published by Prentice Hall in 2007.

Dr. Antonio Ciccomancini Scogna received the Laura and Ph.D. degrees in electrical engineering from the University of L’Aquila, L’Aquila, Italy, in 2001 and 2005, respectively.

He is currently a Principal Engineer at Computer Simulation Technology (CST) of America, Framingham, MA. His research interests include electromagnetic compatibility numerical modeling, printed and integrated circuits, electromagnetic packaging effects, signal integrity and power integrity analysis in high-speed digital systems. He has authored or coauthored more than 50 publications in IEEE journal transactions, IEEE conference proceedings, and Electronic Design Automation (EDA) magazines.

Dr. Ciccomancini is a member of Applied Computational Electromagnetic Society (ACES), Institution of Engineering and Technology (IET), EMC TC-9 and TC-10 Committees. In 2004, he received the CST University Publication Award for the use of the finite-integration technique in signal integrity applications. He is the recipient of DesignCon Finalist Best Paper Award in 2007 and DesignCon Best Paper Award in 2008.

M2
Introduction to Microelectronics Packaging

Course Leader: Phillip G. Creter, Creter & Associates

Course Description:
This up-to-date and constantly revised course provides an introduction to microelectronics packaging using simple terms for ease of understanding. No prior knowledge of microelectronics required. Emphasis will be on visual aids including actual pass-around microcircuit samples, and a variety of photos and figures. The attendee will learn basic packaging definitions and current terminology of materials, processes and equipment, including: thick/thin film technology and nanotechnology as applied to microelectronics and semiconductor processing. 2010 updates include the new sintered nano silver material for chip attach, MEMS, SiP, RFID, Thru-Silicon Vias, Thin Chips/2.5D-3D/WLP, and Green Technology. An overview of major industry leaders includes Intel's 32nm process, IBM's C4NP, Freescale's RCP, Samsung's TSV, and Amkor's SiP/SoP and StatsChipPac's PoP. Technical topics with video clip highlights include WLP, FC bumping, dicing, substrates (ceramic, conductors, dielectrics, co-fired, LTCC); components – passives, actives, chips vs. discrete SMT components and flip chip; assembly including details of basic package types (SO, LCC, CERDIP, QFP, QFN, BGA, CSP, stacked die, and plastic over molded lead frame). Also covered are photolithography, die attach, wire bonding, micro-soldering, plating, rework & repair, final assembly including elements of visual inspection, test, hermeticity, reliability, failure analysis, design, cleanrooms and handling techniques. A 250-page invaluable class handout includes all PowerPoint slides, an expanded glossary and extensive list of 200+ references.

Who Should Attend?
Designed primarily for entry-level R&D/manufacturing/quality technicians/engineers or others with little knowledge of microelectronics packaging but also includes topics of interest for senior engineers' overview, sales/marketing, purchasing, safety and management.

Phillip Creter has 30+ years of microelectronics packaging experience and is a Life member of IMAPS. He was elected a Fellow of the Society, National Treasurer and President of the New England Chapter (twice). He received a BS in Chemistry from Suffolk University and has published numerous papers, holds a U.S. patent, has given many technical presentations (received IMAPS Best Paper of Session award), and chaired technical sessions for symposia. He is currently a consultant with experience at Polymer Flip Chip Corporation, Mini-Systems, GTE and Itek Corporation. His past positions include GTE Microelectronics Center Manager, Process Engineering Manager, Process Development Manager, Materials Engineering Manager and Manufacturing Engineer. Phil currently teaches courses at microelectronics events and is an experienced Webinar instructor. He is also an active certified instructor for the Department of Homeland Security.

M3
Technology of Screen Printing

Course Leaders: Arthur Dobie, Sefar Inc.; David Malanga, Heraeus, Inc., Circuit Materials Division

Course Description:
Screen printing continues to offer innovative and cost effective solutions to the increasing demands for higher circuit densities.  This course is intended to increase the understanding of the screen printing process, thereby improving production yield and print quality.

Presented are some of the latest advancements in composition, screens, and printing technology that enable screen printing to meet future circuit density requirements as well as the definition required for microwave circuitry.  The advantages of screen printing, an additive deposition process, are described and compared to alternative more costly and “less-green” subtractive deposition technologies.

This course is applications-oriented in terms of how to optimize the screen printing process; how to use and specify screen correctly; rheology properties that affect print results; minimizing printing defects and trouble-shooting problems related to screens, inks and the printing process itself.

Who Should Attend?
This course is targeted for production and process engineers, plant and production managers and supervisors, and any others interested in learning how to optimize and increase the use of the screen printing process.

Art Dobie is Manager of Screen Technology for Sefar Printing Solutions, Inc.  He has been with Sefar 29 years since receiving his BS in Screen Printing Technology in 1980 from California University of Pennsylvania.

Art is an invited instructor of the Screen Printing Technical Foundation's Professional Screenmaking Workshop, and has instructed IMAPS’ “Technology of Screen Printing” PDC since its inclusion in 1991.  He has delivered numerous technical presentations to screen-printing professionals at local, national and international level symposia. 

Mr. Dobie is a Life Member and Fellow of the Society of IMAPS, and received the 2006 IMAPS Technical Achievement Award for outstanding technical contributions to screen printing technology relating to microelectronics.  In 1998, Art Dobie was inducted into the SGIA's Academy of Screen Printing Technology.

David Malanga is currently the Vice President, Business Unit Manager at Heraeus Thick Film Materials Division in West Conshohocken, PA. He is responsible for the thick film business for Heraeus in the Americas. David has over 22 years of experience at Heraeus working in R&D, formulating thick film and LTCC materials, Technical Service solving processing and application problems directly with customers, and Sales manager. David has a B.S. and M.S. in Ceramic Science and Engineering from Rutgers University. David has published various articles on thick film resistors, conductors, LTCC materials, and component metallizations worldwide. He is a Fellow of IMAPS and has held both local and national positions in the organization.

M4
Nanopackaging: Nanotechnologies in Microelectronics Packaging

Course Leader: Dr. James E. Morris, Portland State University

Course Description:
The prevalent nanotechnologies being applied to packaging reliability improvement are nanoparticles and carbon nanotubes (CNTs.) The course will outline the basic properties of both, and how they are applied in the enhancement of packaging materials for reliability improvements.

Electron transport mechanisms at small dimensions include ballistic transport, severe mean free path restrictions in very small nanoparticles, various forms of electron tunneling, electron hopping mechanisms, and more. Nanoparticle proprties which may be exploited in packaging include, melting point depression, sintering, the Coulomb blockade, theoretical maximum mechanical strengths in single grain material structures, enhanced chemical activities, and unique optical scattering properties.

The properties of CNTs will be similarly covered, and connected to their nanopackaging applications.

Who Should Attend?
The course will be beneficial to electrical, mechanical, and materials engineers alike, or anyone with an interest in electronic device design, fabrication, assembly, or application. The level will be introductory.

Dr. James Morris is an ECE Professor at Portland State, Oregon, and Emeritus at SUNY-Binghamton, having served as Department Chair at both, and founded Binghamton’s Institute for Research in Electronics Packaging. He has Physics BS/MS degrees from the University of Auckland, and an EE Ph.D. from the University of Saskatchewan. Jim is an IEEE Fellow, and has served the CPMT Society as Treasurer (1991-1997), BoG member (1996-1998), VP for Conferences (1998-2003), Distinguished Lecturer (2000), CPT-Transactions Associate-Editor (1998), IEEE Nanotechnology Council (NTC) representative (2007), won the 2005 CPMT David Feldman Outstanding Contribution Award, and was founding chair of the IEEE Education Society’s Oregon Chapter. He has edited four books on electronics packaging, established the NTC Nanopackaging TC, and contributes to IEEE Nanotechnology magazine. He was General Conference Chair of Adhesives in Electronics (1998), Advanced Packaging Materials (2001) and Polytronic (2004) and was a Nokia-Fulbright Fellow in 2009.

M5
An Electronics Expert Reliability Analysis Tool

Course Leaders: Craig Hillman, Greg Caswell, Nathan Blattau, DfR Solutions

Course Description:
This course will introduce a first‐of‐its‐kind Electronics Design Reliability (EDR) solution that will transform the process of analyzing, grading, and certifying the expected reliability of electronics products at the circuit board level.  Four outputs that become critical to the design process will be presented:
•           A reliability score – which calculates the likelihood that a product will perform reliably in the marketplace. The higher the score, the better the reliability.
•           Predicted performance over time – which product teams can use to help to project the profitability of a product over its lifecycle.
•           A physical map of reliability issues – which identifies to the user the likely points of failure (red flags) for rapid comprehension

For the first time the principles of Physics‐of‐failure (PoF)‐based analysis – a new, more accurate method for predicting product reliability  including the following will be demonstrated, addressing:
o Thermal measurement.
o PTH fatigue.
o Solder fatigue.
o Spacing calculation for holes and components.
o Design rule checks.
o Design for manufacturability.
o Mechanical response to vibration, shock, and bending
o Component stress analysis
o Degradation of light emitting diodes and laser diodes

Who Should Attend?
This PDC is intended as an introductory to intermediate level course for designers, component engineers, quality engineers, reliability engineers, and their managers.

Dr. Craig Hillman is the CEO and Managing Partner of DfR Solutions (www.dfrsolutions.com), a world-leader in quality and reliability solutions for the electronics community. Dr. Hillman and his staff are at the forefront of failure investigations of systematic defects affecting the electronics industry, including flame-retardants in epoxy encapsulants and bulging of low-ESR electrolytic capacitors. Dr. Hillman and his team at DfR Solutions has also developed an extensive expertise in Pb-free reliability issues, best practices in design for reliability (DfR) and manufacturability (DfM), thermal/mechanical/electrical simulation, reliability predictions and test-to-field correlation, component derating/uprating, qualification of circuit boards and assemblies, and a wide variety of failure mechanisms (electronic packaging, component, printed board, interconnections, and connectors). Dr. Hillman has performed over 500 failure analysis investigations, published over 40 papers in the area of electronics quality and reliability, has presented to over 200 companies and organizations, including SMTAI, IEEE, MIT, and DMSMS. Dr. Hillman has a B.S. in Metallurgical Engineering and Material and Engineering and Public Policy from Carnegie Mellon, a PhD in Material Science from University of California - Santa Barbara, and a research fellowship from Cambridge University in England.

Greg Caswell, Senior Member of the Technical Staff is widely recognized as a pioneer in surface mount technology (SMT) and has 35 years of experience in the electronics industry.   His experience encompasses all aspects of SMT manufacturing, circuit board fabrication and materials, advanced packaging (BGA, mBGA, CSP, Flip Chip, QFN), IC fabrication processes and materials, solder reflow, robotics, RoHS, and bonding utilizing specialized nanotechnology.   He has over 230 publications, including being the Editor of the 1st book on SMT, addressing NanoTechnology CMOS, CMOS/SOS, input protection networks, surface mount technology and advanced packaging.   Greg, a Past President of IMAPS, also directed the Advanced Technology Workshop program from 1989-2000, which produced workshops each year on different aspects of current and emerging packaging technologies. He has taught short courses on SMT at IMAPS National Symposiums as well as at local chapter events and he is a member of the National Technical Program Committee.  He is currently the Editor in Chief for Advancing Microelectronics magazine and the past Chair of the GBC. He has received the IMAPS Technical Achievement (1986), Fellow of the Society (1993), and Daniel C Hughes Memorial Award (1995).

Dr. Nathan Blattau, Vice President of DfR Solutions, has been involved in the packaging and reliability of electronic equipment for over eight years. Dr. Blattau is also experienced in failure analysis and accelerated testing methods. His primary research interests are in the areas of development of Physics of Failure models and algorithms, design-for-reliability in electronic packaging, nonlinear finite element analysis, solder joint reliability, fracture, and fatigue mechanics of materials. Through extensive testing, analysis, and simulation, Dr. Blattau has developed a thorough understanding of the defects and degradation mechanisms that can induce failure in Pb-free product.  Due to his efforts, Dr. Blattau was recently selected to lead a comprehensive reliability study on SN100C, a Pb-free alternative that is being considered as a replacement for SAC due to superior manufacturability. Dr. Blattau has written numerous articles and holds two patents pending in software-based simulation and accelerated life testing. He holds a B.S. in Civil Engineering, M.S. in Mechanical Engineering, and PhD in Mechanical Engineering all from the University of Maryland.

M6
Wire Bonding in Microelectronics

Course Leader: Lee Levine, Process Solutions Consulting

Course Description:
Wire bond manufacturing defects range typically from about 1000 to 100 ppm, with exceptions to >10,000 and <50 ppm. In order to achieve the lower numbers in production, one must understand all of the conditions that affect both bond yield and reliability (since they are interrelated). This course will discuss many small- and large-wire bonding problems, as well as subjects of specific interest to hybrid/MCM device bonding. In addition, a number of advanced topics, such as high yield, fine pitch (towards 25 �m ball bond pitch), and bonding to flex will be covered. Newer developments are included along with a major discussion of wire bonding to multichip substrates, soft substrates, Cu-Lok and the special intermetallic problems occurring when fine pitch chips are used. Wire bond testing and metallurgy (covering both aluminum and gold bonds); intermetallic compounds in general; cratering; cleaning for high yield and reliability; failures resulting from electroplating; mechanical problems in wire bonding; new bond technologies and developments; how ultrasonic bonds are formed, and the metallurgy of gold and aluminum wire. It concludes with methods of making very low loops, implementing TAB and Flip Chip by using wire bonding/stud bumping techniques.

It is recommendation of the instructor that you purchase a copy of the text book "Wire Bonding in Microelectronics", by George Harman, McGraw Hill, NY, 2010.

Who Should Attend?
Engineers in R&D, QA, QC, manufacturing, process development, and advanced technicians. It is assumed that participants have some familiarity with wire bonding and general device assembly technologies.

Mr. Levine experience includes 20 years as Principal and Staff Metallurgical Process Engineer at Kulicke & Soffa and Distinguished Member of the Technical Staff at Agere Systems. Currently he consults for his own company, Process Solutions Consulting, providing process consulting, yield improvement, SEM, EDS and Metallography services to the microelectronics industry. He has been awarded 4 patents, published more than 50 technical papers, and won the 1999 John A. Wagnon Technical Achievement award from the International Microelectronics and Packaging Society, IMAPS. Major innovations include copper ball bonding, loop shapes for thin, small outline packages (TSOP and TSSOP, and CSPs) and introduction of DOE and statistical techniques for understanding assembly processes. He is a Fellow, V.P of the Keystone Chapter, and V.P Technology for IMAPS.

Mr. Levine is a graduate of Lehigh University, Bethlehem, PA where he earned a degree in Metallurgy and Materials Engineering.

M7
Hermeticity Testing and RGA (Residual Gas Analysis)

Course Leaders: Thomas J. Green, TJ Green Associates LLC; Philipp Schuessler, Schuessler Consulting

Course Description:
Hermeticity of electronics packages including Hybrids, RF MMIC Modules, MEMS/MOEMS packaging for Military, Space and Medical device implant applications continues to be of critical importance.

This course begins with an overview of hermetic sealing processes.  The course then examines the accepted leak test techniques as prescribed in Mil Standard 883 Test Method 1014.  Issues with bomb times and pressures, measured leak rate vs. air leak rates, “one way leakers”, virtual leakers will be addressed, along with gross leak testing. In each case the focus will be on practical issues facing the industry.  The basic science and applicability of both Optical Leak Test (OLT) and Cumulative helium Leak Detection (CHLD) will be described with plenty of time for questions. The gas ambient inside the package is measured using Residual Gas Analysis.  What is RGA (Residual Gas Analysis)?  How does it relate to Hermeticity testing?

Packages made from polymeric materials as opposed to traditional hermetic seals (i.e. metal, ceramic etc.) require a different approach from a testing standpoint.  The problem is now one of moisture diffusion through the barrier and package interfaces.  A brief review of the techniques and methods to evaluate a "non-hermetic" approach is presented.

It is recommended that you purchase a copy of the text book “Hermeticity of Electronic Packages” by Hal Greenhouse (Noyce Publications 2000). Instructors will also provide a handout on "Practical Guide to TM 1014" authored by Mr. Green and “Assessment of RGA Failures in Microelectronic Devices”, 2010, a prepublication manuscript by Mr. Schuessler.

Who Should Attend?
This PDC is intended as an introductory to intermediate level course for process engineers, designers, quality engineers, and managers responsible for sealing, leak testing and RGA results.

Mr. Green is the principle at TJ Green Associates LLC (www.tjgreenllc.com) a Veteran Owned Small Business focused on training and consulting for military, space and medical microelectronic devices. He has over twenty-eight years experience in the microelectronics industry at Lockheed Martin and USAF Rome Laboratories. At Lockheed he was a Staff engineer responsible for the materials and manufacturing processes used in building custom high reliability space qualified microcircuits for military and commercial communication satellites. He has conducted experiments and presented technical papers at NIST and IMAPS on leak testing techniques and optimization of seam welding processes through statistical DOE methods. Tom is an IMAPS Fellow and active leader in the society. He has a B.S. in Materials Engineering from Lehigh University and a Masters from the University of Utah.

Mr. Schuessler is a chemist with a B.S. in Analytical Chemistry and an M.S. in Synthetic Inorganic Chemistry. He was a Senior Scientist at IBM/FSD and Lockheed Martin for over thirty-five years. His specialties are in materials for the manufacturing of electronic devices for DOD and NASA, and Applied R&D for the U.S. Navy in moisture permeation and hydrophobic resins. He received NASA recognition for his work on the Challenger Shuttle Recovery Team, where he extemporaneously developed a recovery and stabilization protocol for computer hardware at the recovery site and reconstruction facilities.

In Materials and Process Development, he was responsible for the polymeric seal process of the first FSD hybrid-LSI devices. He had organized an adhoc group of technologists to address hydrogen evolution and moisture formation in hermetic devices.

He worked with JEDEC task groups on test methods for the DOD/OEM community. He chaired the task groups for Method 5011 (Adhesives and Polymeric Materials) and Method 1018 (Residual Gas Analysis).
Mr. Schuessler has authored over fifty papers on various aspects of industrial chemistry and has made presentations on materials and specification issues on an international basis. He has over twenty published invention disclosures and four published patents. He has coordinated the Minnowbrook Conference since 1985.

½ Day Course: 8:00 am - Noon
M8
3D Integration and Packaging Technologies, Assessment, Status and Applications

Course Leader: James Jian-Qiang Lu, Rensselaer Polytechnic Institute

Course Description:
Based on instructor’s 3D research since late 1990s, this course will discuss the latest development of Through-Strata-Vias (or Through-Si-Vias, TSVs) and other relevant enabling technologies for 3D IC integration and packaging. A comprehensive overview of 3D integration and packaging technologies will be presented, including motivation, key technologies, technology assessment and status towards commercialization.  The major motivations discussed include miniaturization of micro-systems; performance increase in speed and data bandwidth due to a massive number of small-sized Through-Strata-Vias (TSVs); heterogeneous system integration of variety of technologies; and lower manufacturing cost for specific 3D applications.

In this course, 3D integration technologies are divided into 4 categories – transistor build-up, wafer-to-wafer (W2W) stack, chip-to-wafer (C2W) assembly, and packaging-based 3D. In transistor build-up 3D, active devices are built-up over an IC wafer. In W2W stack 3D, different systems are first fabricated independently and then stacked and interconnected vertically. The C2W assembly is similar to SoC approach, but with known-good-dies (KGDs) assembled on a wafer, then processed in wafer-level. In the last category, the ICs are packaged vertically in chip-to-chip (C2C), system-in-packaging (SiP) and package-on-package (PoP) fashions.  A particular focus will be on various TSV fabrication/processing methods and applications, with relevant critical issues addressed, such as TSV processing, alignment, bonding, wafer thinning and handling for C2C, C2W and W2W integration platforms.

This course will discuss all these technologies, with emphasis on technology status and potential applications (e.g., image sensor, memory, and memory/logic). The challenges associated with each technology category will be discussed, including integration architecture and design tools, yield and cost, thermal and mechanical constraints, and manufacturing infrastructure. Finally, future directions into micro/nano/electro-opto/bio system hyper-integrations including MEMS will be presented, showing 3D hyper-integration as a very promising emerging architecture for future computer, network, nanotech, and biotech applications.

Who Should Attend?
Engineers, managers and executives involved in future R&D investments, assembly and product development of electronic packaging, and wanting fundamental understanding of 3D technologies, as well as the materials and equipment suppliers wanting to know about the existing and future 3D integration technologies and options, will greatly benefit from this course.

Dr. James Jian-Qiang Lu received his Dr.rer.nat. (Ph.D.) degree from Technical University of Munich in December 1995, and is currently an Associate Professor in Electrical Engineering at Rensselaer Polytechnic Institute (RPI), Troy, NY.  At RPI, Dr. Lu has worked on 3D hyper-integration technology, design and applications since 1999, with focus on hyper-integration and micro-nano-bio interfaces for future chips. He has >200 publications, and gave a number of invited presentations, seminars and short courses.  He served as technical chair, workshop chair, session chair, panelist and panel moderator for many conferences.  He is a senior member of IEEE, a member of APS, MRS and ECS. He has served as the 3D Packaging Chair of the IMAPS National Technical Committee since 2006. He received the 2008 IEEE CPMT Exceptional Technical Achievement Award in May 2008 "for his pioneering contributions to and leadership in 3D integration/packaging".

½ Day Course: 1:00 pm - 5:00 pm
M9
3-D IC Integration

Course Leader: Dr. Philip E. Garrou, Microelectronic Consultants of NC

Course Description:
This course is based on the authors activity in the last 7 years with numerous 3D IC companies in the industry, the authors weekly blog and articles in Semiconductor International “Perspectives From the Leading Edge” and his two volume handbook on 3-D IC published by Wiley VCH “Handbook of 3-D IC Integration: Technology and applications of 3-D IC Circuits”.

The course will begin by defining and contrasting 3-D integration (thinning, bonding, TSV) with 3-D packaging (thinning, stacking and wire bonding to a BGA base). We will examine the various drivers for 3-D integration and the process and unit operations necessary to fabricate a 3-D stack. The process sequences proposed by numerous companies, institutes and universities will be discussed and contrasted.

We will examine the applications expected to be found in the early and later adopters for 3-D technology and the evolving infrastructure that will be necessary to accomplish this. The course will end by looking at the remaining technical and market barriers (design, thermal, test) and looking at the current best sources of 3-D information.

Who Should Attend?
This course will be aimed at the technical personnel wanting a status review of the subject and marketing/management personnel looking for a status report to help formulate their position in the business food chain.

Dr. Garrou received his B.S. from North Carolina State University (1970) and his PhD from Indiana University (1974). From 2002 – 2004 he was Global Director of Technology and New Business Development for Dow Chemicals Advanced Electronic Materials business. From 1997 - 2002 he was Technical and Commercial Director of Dows BCB dielectric business.

He currently consults in the areas of 3-D IC, thin film technology, IC packaging and interconnect and microelectronic materials for startups and fortune 500 companies. He is also a contributing editor for Semiconductor International where he covers 3-D IC and advanced packaging. 

He has authored / edited (5) microelectronic texts including Handbook of 3-D IC Integration: Technology and applications of 3-D IC Circuits for Wiley VCH and has co-authored > 100 technical publications and book chapters.
He is a fellow of IEEE and IMAPS and has served as President of both IEEE CPMT and IMAPS. He has won the IEEE CPMT “Sustained Technical Achievement” award and the IMAPS “Ashman” achievement award.

 

Event Sponsors

Logo Bags, Final Program, Internet Café and Convention Hall Signs:
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