Tuesday: Morning Sessions (TA1 - TA5) | Afternoon Sessions (TP1 - TP5)
Wednesday: Morning Sessions (WA1 - WA6) | Afternoon Sessions (WP1 - WP5)
Thursday: Morning Sessions (THA1 - THA5)
Interactive Poster Session | Program Grid (At-a-Glance) | Download Final Program PDF

Tuesday, November 2, 2010 | Morning Sessions: 8:00 AM - 11:10 AM
3D Packaging and Integration Track	Modeling and Reliability Track	Next Generation Materials Track	Assembly and Packaging Track	Advanced Technologies Track
TA1 3D Interconnect Technologies in RTP Chairs: Phil Garrou, Microelectronic Consultants of NC 3-D IC Integration is an active area of research in Research Triangle Park. We have assembled 6 invited papers from the local area to give you a flavor of what’s going on in 3D in the triangle. 3-D IC Technology – The Perfect Storm Philip Garrou, Microelectronic Consultants of NC Electrical Demonstration of TSV Interconnects and Multilevel Metallization for 3D Si Interposer Applications Erik Vick, Scott Goodwin, Dorota Temple, RTI International Low Temperature Direct Bond Technology for 3D Microelectronics Integration and Wafer Scale Packaging Paul Enquist, Ziptronix, Inc. Creating 3D Specific Systems: Architecture, Design and CAD Paul D. Franzon, W. Rhett Davis, Thor Thorolfsson, Samson Melamed, North Carolina State University Low Temperature Bonding of High Density Large Area Array Interconnects for 3D Integration Jason D. Reed, Matthew Lueck, Chris Gregory, Alan Huffman, John M. Lannon, Jr., Dorota S. Temple, RTI International	TA2 Device Design and Modeling Chair: Joan Delalic, Temple University This session discusses new modeling approaches and applies them towards the design of new devices and systems. Advanced Microfluidic Packaging for Molecular Diagnostics M. Palmieri, STMicroelectronics; T. Barbuzzi, A. Maierna, M. Marchi, G. Montalbano, G. Panvini, STMicroelectronics-Italy; T. Rodenfels, W. Stoeters, Boehringer Ingelheim microParts GmbH A Ceramic Clevis Sensor for Online Substance Concentration Measurement, Manufactured by Ceramic Injection Molding Matthias Hartmann, Steffen Doerner, Soeren Hirsch, Otto-von-Guericke University of Magdeburg (TEPROSA) Packaging of a Fingerprint Based Access Control System Sandeepsarma Josyula, Zdenka J. Delalic, Anand B., Temple University EE Cars Architecture & Linked ECU: Constraints and New Needs El Khamis Kadiri, Eric Fitterer, Bertrand Delord Manson, PSA Peugeot-Citroën Reliability Modeling to Enable Damage Assessments for Plated Through Holes Gilad Sharon, Donald Barker, University of Maryland - CALCE	TA3 Advanced Materials Chair: John Bolger, Department of Defense; Wenning Liu, Pacific Northwest National Laboratory This session covers the use of advanced materials in a wide variety of microelectronics packaging applications, including RF, conductive adhesives, proximity communications, energy storage and nanotechnology. Metal Coated Polymer Particles for Electronic Packaging Dan Goia, Keith Redford, Ionel Halaciuga, Clarkson University Achieving Ceramic-like RF Capacitor Requirements with Organic-Based Materials Jin-Hyun Hwang, John Andresakis, Bob Carter, Yuji Kageyama, Fujio Kuwako, Oak-Mitsui Technologies, LLC Characterization of Substrate Materials for End-Use in Environment Classification Syed Sajid Ahmad, Arun Shankaran, Fred Haring, Justin Vignes, Bernd Scholz, Aaron Reinholz, North Dakota State University Ferro-Electrically Enhanced Proximity Communications: Microfabrication and Characterization John E. Cunningham, Ivan Shubin, Steve Zamek, Darko Popivitch, Ashok Krishnamoorthy, Jim Mitchell, Sun Labs at Oracle Solid-State Formation of Intermetallic Compounds in Co-Sb Coupled Nanowires Seong Gi Jeon, Jae Yong Song, Ho Sun Shin, Jin Yu, Korea Advanced Institute of Science and Technology Global Technology Survey of Anisotropic Conductive Interconnect Technologies, Past Present and Future - An Industry Intellectual Property Approach Edmar M. Amaya, Gene A. Lang, EDAM LAW PLLC	TA4 Package Reliability Testing Chairs: Jae Yong Song, Korea Research Institute of Standards and Science; Mudasir Ahmad, Cisco Systems, Inc. Research on the experimental testing and simulation methods of evaluating the mechanical reliability of solder ball joints, interconnects, multichip modules, and etc., used in electronic packages. Investigation on the Failure Criterion of Reliability Testing for Pb-Free BGA Packages Weidong Xie, Tae-Kyu Lee, Kuo-Chuan Liu, Jie Xue, Cisco Systems, Inc. Validated High Speed Pull and Shear Test Methodologies to Evaluate Pb-Free BGA Mechanical Strength Mudasir Ahmad, Amir Youssef, Cisco Systems, Inc.; Ravi Assudani, Drew Nelson, Stanford University Improved Design of a High Density 3D Multichip Module for Class I Medical Devices Doug Link, Michael Kollar, Starkey Laboratories, Inc. Tape-Peel Testing as a Simple Method to Evaluate the Adhesion of Coated Layers on Metal Core PCB Bernd Scholz, Ismir Pekmic, Syed Sajid Ahmad, Aaron Reinholz, North Dakota State University Interconnect Failure Rate Estimation Based on the Extreme Value Distribution Mark Plucinski, Mark Hoffmeyer, IBM Corporation Enabling MSL-1 Capability for QFN and Other Design Leadframe Packages Dan Hart, John Ganjei, Nilesh Kapadia, MacDermid Electronic Solutions	TA5 LED Packaging Chair: John Mazurowski, Pennsylvania State University We are now using LED technology to reduce life cycle costs, and this has become a challenge for efficiency. This session covers aspects of LED packaging including electrical, mechanical, optical, and thermal- and covers issues relevant to specific applications LED Manufacturing Trends (50 Minutes) Jeff Perkins, Yole, Inc. Improvements in Solid State Lighting Applications with the use of Traditional Thick Film Technology Sarah Groman, Heraeus Materials Technology LLC; Neil Jones, TT Group Industries Thermal Management Solutions for the LED Market Andrew Kintz, Sara Paisner, Shane Thompson, Lord Corporation Thermoplastic Optical Polymers with Lead-Free Solder Reflow Resistance for HB-LED Packaging and Assembly Weijun Zhou, Quan Yuan, Chris Li, Stephen F. Hahn, Kurt A. Koppi, Berend Hoek, The Dow Chemical Company
Tuesday, November 2, 2010 | Afternoon Sessions: 1:55 PM - 5:40 PM
3D Packaging and Integration Track	Modeling and Reliability Track	Next Generation Materials Track	Assembly and Packaging Track	Advanced Technologies Track
TP1 3D TSV Processes and Modeling Chairs: James J.-Q. Lu, Rensselaer Polytechnic Institute; Zhongping Bao, Qualcomm Inc. This session focuses on the latest achievement related to Through-Silicon-Via (TSV) processes and modeling, including TSV etching, liner disposition, copper fill, planarization, and electrical and mechanical modeling. Electrical Analysis and Modeling of 3D Through-Strata-Vias (TSVs) and Pads Zheng Xu, Adam Becce, Kenneth Rose, Jiang-Qiang Lu, Rensselaer Polytechnic Institute Impact of Mechanical Simulation Methodology on Electronic Package Reliability Assessment with Applications to 3D TSS Technology Zhongping Bao, James Burrell, Qualcomm Inc. Enabling Robust Copper Fill of Super High Aspect Ratio Through Silicon Vias Greg Arendt, Damo Srinivas, Sesha Varadarajan, David Porter, Mark Willey, Novellus Systems A Novel TSV Etching using NLD and VHF CCP Plasma for 3-D Stacked Devices Yasuhiro Morikawa, Takahide Murayama, Manabu Yoshii, Koukou Suu, ULVAC, Inc. Highly Ionized Sputtering for TSV-Lining Mohamed Elghazzali, Juergen Weichart, OC Oerlikon Balzers Limited Filling and Planarizing Deep Trenches With Polymeric Material for Through-Silicon Via Technology R. K. Trichur, M. Fowler, J. W. McCutcheon, M. Daily, Brewer Science, Inc.	TP2 Design for Reliability Chair: John Torok, IBM Corporation With more integration across chips, packages and system through 3D packaging, SiP and multi-chip modules, testing for failure and detecting the failure mechanism are very important. Design is the best stage to systematically implement a reliability improvement and monitoring scheme. In this session, papers that discuss designs to improve and quantify reliability will be presented. Improvement of ELK Reliability in Flip Chip Packages using Bond-on-Lead (BOL) Interconnect Structure Eric Ouyang, MyoungSu Chae, Seng Guan Chow, Roger Emigh, Mukul Joshi, Rob Martin, Raj Pendse, STATSChipPAC Inc. Molded Underfill (MUF) Technology Development for SiP Module With Fine Flip Chip Do-Jae Yoo, Ki-Chan Kim, Young-Hoon Kwak, Min-Seok Jang, Job Ha, Jae-Cheon Doh, Chang-Bae Lee, Young-Do Kweon, Samsung Electro-Mechanics Co., Ltd. Characteristic Life Based Acceleration Transforms for Lead-Free Solder Joint Reliability under Thermal Cycling Conditions Mudasir Ahmad, Kuo-Chuan Liu, Cisco Systems, Inc. Drop Test Simulation for the Reliability of Laminate Substrate in Module Packages Yu Gu, Daniel Jin, RFMD Counterfeit Detection Strategies: When to Do It / How to Do It Greg Caswell, DfR Solutions Electromigration Performance of µPILR Fine Pitch Pb-Free Flip-Chip Packages Rajesh Katkar, Laura Mirkarimi, Tessera Inc.	TP3 Ceramic and LTCC Packaging Chairs: John Menaugh, DuPont Microcircuit Materials; Larry Zawicki, Honeywell FM&T The use of ceramics in the electronics industry continues to grow. Ceramic applications in electronics include sensors, actuators, electro-optical materials, packaging of semiconductors, and multilayer modules for RF and Microwave applications. The reasons for the increased use is that ceramics is chemically inert, provides a hermetic package around unpackaged ICs, capable of withstanding high temperatures and the TCE closely matches the performance of the semiconductors. Investigation of Silver Migration Impacts on Microwave Systems Fabricated on LTCC Substrate Under High-Power RF Excitation and High Temperature and Humidity Conditions Deepukumar M. Nair, K. M. Nair, Ken Souders, Michael Smith, Mark McCombs, James Parisi, Tim Mobley, DuPont Electronic Technologies; Bradley Thrasher, Innerpulse Inc. Selected Applications and Processing for Low Temperature Cofired Ceramic Ken A. Peterson, Daniel S. Krueger, Charles E. Sandoval, Sandia National Laboratories New Mixed Metal Transition Via-Fill Conductors for Cost Effective DuPont GreenTape™ 951 & 9K7 LTCC Circuits K. M. Nair, M. F. McCombs, K. E. Souders, S. E. Gordon, DuPont Microcircuit Materials Effect of Dielectric Selection on Sintering Behavior of LTCC Daniel S. Krueger, Laura Agee, Cristie Fadner, Brent Duncan, Greg Hilmas, Shi Zhang, Wayne Huebner, Honeywell Federal Manufacturing & Technologies; Ken Peterson, Sandia National Laboratories The Future of Maximum CAD/CAM Automation for Ceramic Hybrids John Sovinsky, CAD Design Services, Inc.	TP4 Pb-Free Solder Materials and RoHS, Processes and Reliability Chairs: Tae-Kyu Lee, Cisco Systems, Inc.; Jae-Woong Nah, IBM T. J. Watson Research Center This session provides the latest advances in materials, processes, and reliability issues in Pb-free solder materials. Pb-Free v/s Tin-Lead Reliability Comparison for Telecom/High Reliability Applications Ganesh Iyer, Gnyaneshwar Ramakrishna, Lavanya Gopalakrishnan, Kuo-Chuan Liu, Cisco Systems, Inc. Effects of Fe on the Kirkendall Void Formation of Sn-3.5Ag-xFe/Cu Solder Joints S.H. Kim, Jin Yu, KAIST Impact of Isothermal Aging on Fine Pitch BGA Packages with Sn-Ag-Cu Solder Interconnects Tae-Kyu Lee, Weidong Xie, Kuo-Chuan Liu, Jie Xue, Cisco Systems, Inc.; Thomas R. Bieler, Michigan State University A Study on the Mechanism of Black Pad Formation during Electroless Nickel Immersion Gold Process J.H. Kim, Jin Yu, KAIST; K. H. Kim, Carnegie Mellon University Nanoindentation Characterization of Lead-free Solders and Intermetallic Compounds Under Thermal Aging Shi-Wei Ricky Lee, Tong Jiang, Fubin Song, Chaoran Yang, Hong Kong University of Science and Technology Effects of Electromigration(EM) on the Kirkendall Void Formation in Sn-3.5Ag/Cu Solder Joints Yong Jung, Jin Yu, KAIST	TP5 Wafer Level/CSP Packaging Requirements Chairs: Susan Chen & George Sears, Lord Corporation Cost reduction and miniaturization are some of the challenges that the semiconductor and IC packaging industry has been facing. Wafer level packaging and chip scale packaging have gained their popularity in recent years addressing these industry needs. This session consists of interesting papers on the packaging evolution technology review and the latest technology development in these areas. On the Origins, Status, and Future of Flip Chip & Wafer Level Packaging Alan Huffman, RTI International; Philip Garrou, Microelectronic Consultants of NC 2nd Level Reliability Improvement on WLCSP Seungwook Park, Jupyo Hong, Changbae Lee, Sunhee Moon, Jinsoo Kim, Hyungjin Jeon, Dojae Yoo, Youngdo Kweon, Samsung Electro-Mechanics Co., LTD. Spin Coating of Dielectrics on Thin Silicon to Enhance Strength Characteristics Fred Haring, Syed Sajid Ahmad, Nathan Schneck, Kaycie Gerstner, Nicole Dallman, Chris Hoffarth, Aaron Reinholz, North Dakota State University Wafer-Level Hermetic Packaging for Bio-Medical Applications Antonio La Manna, Carine Gerets, Maaike Op de Beeck, Thibault Buisson, Eric Dy, Philippe Soussan, IMEC Mask and Mask-Less Injection Molded Solder (IMS) Technology for Fine Pitch Substrate Bumping Jae-Woong Nah, Peter A. Gruber, Paul A. Lauro, Claudius Feger, IBM T.J. Watson Research Center

Wednesday, November 3, 2010 | Morning Sessions: 8:00 AM - 11:40 AM
3D Packaging and Integration Track	Modeling and Reliability Track	Next Generation Materials Track	Assembly and Packaging Track	Advanced Technologies Track
WA1 3D Systems Integration Chairs: Venky Sundaram, Georgia Institute of Technology; Kevin Moores, Department of Defense This session focuses on recent advances in modules and systems enabled by 3D stacking, including materials and processes for wafer thinning, TSV fabrication, bonding and assembly, interconnection schemes, and system level modeling and characterization. The Role of Wafer Bonding in 3D Integration and Packaging James Hermanowski, Greg George, SUSS MicroTec, Inc. Advanced Thin Wafer Support Processes for Temporary Wafer Bonding Jeremy W. McCutcheon, Dongshun Bai, Brewer Science, Inc. Simulation of Process-Stress Induced Warpage of Silicon Wafers Using ANSYS® Finite Element Analysis Aditi Mallik, Roger Stout, ON Semiconductor Processing Aspects to Achieve High-End Hybrid Backside Illuminated Imagers Joeri De Vos, Koen De Munck, Mehmet Akif Erismis, Padmakumar Ramachandra Rao, Kiki Minoglou, Wenqi Zhang, Deniz S. Tezcan, Piet De Moor, Philippe Soussan, IMEC Advances in Wafer Level Processing and Integration for CIS Module Manufacturing Bioh Kim, EV Group, Inc.; Thorsten Matthias, Gerald Kreindl, Viorel Dragoi, Markus Wimplinger, Paul Lindner, EV Group Development on Silicon Module with Cu-Fillled TSV and Integrated Passive Devices Yun-Mook Park, Jun-Kyu Lee, Byung-Jin Park, Byeung-Gee Kim, Jung-Won Lee, In-Soo Kang, NEPES Corporation	WA2 Modeling & Design for Signal/Power Integrity Chairs: Ivan Ndip, Fraunhofer Institute for Reliability and Microintegration, IZM; Sanjeev Gupta, Agilent Technologies Semi-analytical, numerical and statistical methods are applied to efficiently and accurately model electronic packaging structures. Design guidelines/rules are derived to ensure signal and power integrity. PCB Effects on On-Chip Capacitor Requirements and an Efficient Resonance-Prevention ASIC Methodology Timothy Budell, Eric Tremble, IBM Systems and Technology Group A Miniaturized Ground Surface Perturbation Lattice for Noise/Coupling Mitigation in Packaging Applications Antonio Ciccomancini Scogna, CST of America Capacitance Calculation for Offset Via Structures using an Integral Approximation Approach Based on Finite Element Method Hanfeng Wang, Yaojiang Zhang, James L. Drewniak, Jun Fan, Missouri University of Science and Technology; Bruce Archambeault, IBM Corporation Successful Practices for the Modeling of Printed Circuit Boards and Substrates Using Electromagnetic Field Solvers Steven G. Pytel Jr., Sergey Polstyanko, Werner Thiel, Richard Hall, ANSYS; Scott C. McMorrow, Tom Dagostino, Teraspeed Consulting Debye Model Fitting for Time-Domain Modeling of Lossy Dielectrics A. Ege Engin, San Diego State University Statistical Analysis Approach to Improve the High Speed Signal Quality by Including the Manufacturing Process Variations of Printed Circuit Board Seungyong Baek, Mike Sapozhnikov, Warren Meggitt, Philip Pun, Jason Visneski, Ramesh Velugoti, Amit Agrawal, Cisco Systems, Inc.	WA3 Thermal Management Chairs: Woong-Sun Lee, Hynix Semiconductor Inc.; Virgil Ganescu, Harrisburg Area Community College Thermal Management Session includes topics about all thermal issues of the Electronic Packaging such as Thermal Analysis and Modeling, Thermal Interface Materials, Thermal Packaging, System Cooling, etc. Imminent needs in Future Developments of Air Cooled Microprocessors Heat Sinks V. Ganescu, Harrisburg Area Community College; A. Pascu, Politechnica University of Bucharest Kinetic Heat Sink Vijay Khanna, Gerard McVicker, Sri Sri-Jayantha, IBM - T.J. Watson Research Center New GaN Power-Electronics Packaging Solutions: A Thermal Analysis using Raman Thermography M. Faqir, A. Manoi, M. Kuball, University of Bristol; T. Mrotzek, S. Knippscheer, Plansee SE; M. Massiot, Egide; M. Buchta, H. Blanck, United Monolithic Semiconductors; S. Rochette, O. Vendier, Thales Alenia Space Using In Situ Capacitance Measurements to Monitor the Stability of Thermal Interface Materials in Complex PCB Assemblies Michael Gaynes, Timothy Chainer, Edward Yarmchuk, IBM - T.J. Watson Research Center; John Torok, David Edwards, David Olson, Katie Pizzolato, IBM Corporation Study on Thermal Proof of SnO2 Protection Thin Film for Ultra High Reflective Film Ag System H. Miyagawa, R. Satoh, Y. Iwata, E. Morinaga, S. Kamo, Osaka University	WA4 Wirebonding and Stud Bumping I Chair: Daniel Evans, Palomar Technologies, Inc. Wire bonding continues as the dominant method of chip interconnection. This session starts with an overview of the process and proceeds with some of the innovative variations that enable high reliability solutions to today's packaging. The Microelectronic Wire Bond: Past, Present, and Future Harry K. Charles, Jr., The Johns Hopkins University Applied Physics Laboratory Challenges of Wire Bonding In High Value and High Performance Medical Devices James A. Ohneck, Valtronic Technologies USA Improved Bond Reliability Through the Use of Auxiliary Wires (Security Bumps and Stand-Off Stitch) David J. Rasmussen, Palomar Technologies, Inc., Rodney Thompson, Goodrich Corporation 2.0mils Au Wire Interchip Wedge Bond Process Characterization Wang ZhiJie, Haengsun Choi, Jiang YingWei, Zhang ChangLiang, Ben Lee, Kwansun Hwang, Freescale Semiconductor (China) Limited Predicting Fusing Current for Encapsulated Wire Bonds under Transient Loads Aditi Mallik, Roger Stout, ON Semiconductor A Systematic Approach for Creating a System-In-Package (SIP) Sam Sadri, Tri Le, Stephie Althouse, NxGEN Electronics Inc.	WA5 Emerging Technologies Chair: Luu Nguyen, National Semiconductor Corporation; Mark Hoffmeyer, IBM Corporation This session will introduce emerging technologies in processes, materials, and design for electronic devices. The first four papers in this session present novel patterning processes for a variety of microstructures and substrates. These are followed by a paper introducing a unique capacitor material, and a paper discussing a novel processor design. Silicon Micro-Fabrication Technologies for Micro Filters Bivragh Majeed, Wim De Malsche, Lei Zhang, Paolo Fiorini, Deniz Sabuncuoglu Tezcan, Philippe Soussan, IMEC Understanding Cleaning of Vias Fabricated Using Micro Mechanical Punching in Liquid Crystal Polymer (LCP) Substrate Mohammad K. Chowdhury, Ajay P. Malshe, University of Arkansas; Li Sun, Shawn Cunningham, WiSpry Inc. Laser Patterning and Via Drilling of Sapphire Wafers and Die Justin Vignes, Fred Haring, Syed Ahmad, Kaycie Gerstner, Aaron Reinholz, North Dakota State University High-Dielectric-Constant PLZT Films on Metal Foils for Embedded Passives Beihai Ma, Manoj Narayanan, U. (Balu) Balachandran, Argonne National Laboratory Hardware Design for Novel Packaging of Multi-Cellular Meta-Processing Unit Son Nguyen, Joan Delalic, Temple University; Bjorn Gruenwald, Hilbert Technology The Performance Over the Frequency Range 140GHz-220GHz of Thick-Film CPW Lines Fabricated from Nano-Particle Silver A. Alshehri, R. J. Leigh, C. E. Free, University of Surrey; M. Horaczek, D. Rudka, M. Jakubowska, M. Sloma, Warsaw University of Technology
Wednesday, November 3, 2010 | Afternoon Sessions: 1:35 PM - 5:25 PM Information for Session WP6 - Interactive Poster Session - can be found here
3D Packaging and Integration Track	Modeling and Reliability Track	Next Generation Materials Track	Assembly and Packaging Track	Advanced Technologies Track	Poster Session
WP1 3D Packaging Chairs: Milind Shah, Qualcomm Inc.; Lee Levine, Process Solutions Consulting This session focuses on latest development in 3D packaging which includes package design, process and structure. Chip-last Embedded Actives and Passives in Ultra-Miniaturized Organic Packages with Chip-First Benefits Nitesh Kumbhat, Fuhan Liu, Venky Sundaram, Vivek Sridharan, Abhishek Choudhury, Hunter Chan, Rao Tummala, Georgia Institute of Technology Advanced 3D Packaging of Miniature Biomedical Sensors Dohyuk Ha, Tse-Yu Lin, Byung Guk Kim, Pedro P. Irazoqui, William J. Chappell, Purdue University Wafer Level Assembly Technique Development for Fine Pitch Flip Chip 3D Die-to-Wafer Integration Zhaozhi Li, John L. Evans, Auburn University; Brian J. Lewis, Paul N. Houston, Daniel F. Baldwin, ENGENT, Inc.; Eugene A. Stout, Theodore G. Tessier, Flip Chip International LLC Compression Molding for Thin PoP Top Packages Ravikumar Adimula, Jason Brand, Myung Jin Yim, James Zhang, Richard Strode, Chan Yoo Micron Technologies Fine Pitch 3D Dispensable Electrical Interconnects for System in Package Solutions Jeff S. Leal, Suzette K. Pangrle, Charles Whyte, Keith Barrie, Jeff Leff, Scott McGrath, Gerardo Ayala, Vertical Circuits, Inc.	WP2 System-Level Signal/Power Integrity Design Chairs: Judy Priest, Cisco Systems, Inc.; Dale Becker, IBM Corporation Techniques for system-level modeling, analyzing and suppressing signal/power integrity and EMI issues in high-speed packages and boards are presented. Fast and Accurate Multi-Layer PDN Analysis for Power Integrity and EMC Bruce Archambeault, Sam Connor, IBM Corporation; Ketan Shringarpure, Jun Fan, Missouri University of Science and Technology TSV Modeling Considering Signal Integrity Issues Ivan Ndip, Brian Curran, Kai Löbbicke, Stephan Guttowski, Herbert Reichl, Klaus-Dieter Lang, Fraunhofer Institute for Reliability and Microintegration Custom Test Fixture Design and Measurement Correlation of Differential Pairs in a Flip-Chip Organic Buildup Package Using Measurement Based De-Embedding Daniel Lambalot, Bayside Design, Inc.; Sanjeev Gupta, Agilent Technologies, EEsof-EDA Implementation of a Virtual EMI Lab to Cost-Effectively Tackle Multi-Gigahertz EMI Challenges Amolak Badesha, Agilent Technologies; Hany Fahmy, Chen Wang, Nvidia Corporation; Davy Pissoort, KHBO-FMEC Pinout Optimization for 10 Gbps+ Serial Link Routing Judy Priest, David Siadat, Cisco Systems, Inc. Accurate and Efficient BER Calculation by Statistical Simulation Based on Physical Transmit Jitter Model Fangyi Rao, Sanjeev Gupta, Agilent Technologies, Agilent Technologies, EEsof-EDA Packaging in IBIS-AMI Technology Daniel Dvorscak, Steven G. Pytel Jr., Isaac Waldron, Danil Kirsanov, ANSYS; Dale Becker, Matteo Cocchini, IBM Systems and Technology Group	WP3 High Performance Interconnects and Boards Chair: Amanda Mikhail, IBM Corporation; Anwar Mohammed, Huawei Technologies This session integrates novel approaches to design and verification of high performance interconnects and boards. Design/verification methodologies, material selections, and manufacturing methods are addressed. Characterization of Black Pad Defect on Electroless Nickel-Immersion Gold (ENIG) Plated Circuits Adam W. Mortensen, Roger M. Devaney, Hi-Rel Laboratories High Via Density Thin Metal-Core PCB using Electro-Coated Dielectric Bernd Scholz, Ismir Pekmic, Syed Sajid Ahmad, Aaron Reinholz, North Dakota State University Nanomaterials for “Green” Electronics Rabindra N. Das, Konstantinos I. Papathomas, Mark D. Poliks, Voya R. Markovich, Endicott Interconnect Technologies, Inc. Dynamic Mechanical Analysis of Laminates Joe Kuczynski, IBM Corporation A Novel Metal Core Substrate with Simplified Manufacturing Process and High Adhesion Conformal Dielectric and Circuitry Metal for High Density Chip-Scale Packaging Applications Syed Sajid Ahmad, John Jacobson, Zane Johnson, Kevin Mattson, Aaron Reinholz, Nathan Schneck, Bernd Scholz, Greg Strommen, North Dakota State University Braided Electrical Contact Element Based High Performance Connectors Michael Salloum, Che-Yu Li, BeCe Corporation	WP4 Wirebonding and Stud Bumping II Chairs: Faina M. Zaslavsky, Crane Electronics Group/Microelectronics Solutions; Yong-Bin Sun, Kyonggi University Current hot issues for mass production in wirebonding technology. Fine Pitch Cu Wire Bonding - As Good As Gold Bernd K. Appelt, William T. Chen, Andy Tseng, Yi-Shao Lai, ASE Group Inc. A Robust CUP Pad Structure Design with Thin Pad Metal for Cu Wire Bonding ChangHee Han, SG Kim, JH Shim, DH Jiang, SW Ko, BJ Lee, KC Kim, HG Lee, JS Yoon, BT Jiang, SW Hong, HD Kim, IS Yoo, YS Song, Dalsoo Kim, TLI, Inc.; Sihyun Choe, ASE Korea, Inc. Free Air Ball Consistency of Palladium Coated Copper Wire Johnny Yeung, Sylvia Sutiono, Heraeus Materials Singapore Pte Ltd.; Eugen Milke, WC Heraeus GmbH Wire Bonding UPH and Stitch Bond Improvement using 20 Micron Insulated Wire with Security Bump Chunyan Nan, Michael Mayer, Y. Norman Zhou, University of Waterloo; Jairus L. Pisigan, John Persic, Young-Kyu Song, Microbonds Inc.; Henry Bathan, STATS ChipPAC Ltd. Pure Palladium and Palladium Phosphorus Depositions used in ENEPIG and ENEP Surface Finishes - Comparison of Physical Properties and Their Influence on Soldering and Au Wire Bonding Mustafa Oezkoek, Atotech Deutschland GmbH; Hugh Roberts, Joe McGurran, Atotech USA Inc. A Method to Quickly Measure the Thickness of Aluminum Bond Pad on Silicon Substrate Son Nguyen, Z. Joan Delalic, Temple University; Horst Clauberg, Kulicke and Soffa Industries, Inc.	WP5 MEMS Packaging Chair: Yoon-Chul Sohn, Samsung Advanced Institute of Technology; Ron Barnett, National Instruments Corporation In this session, various types of MEMS and sensor device packaging will be introduced. The contents will contain packaging materials, etching, TSV interconnection, analysis, and low temperature bonding etc. Sensor Packaging: New Challenges for New Applications Caroline Beelen-Hendrikx, Coen Tak, NXP Semiconductors Low Temperature Wafer Level Packaging Technology of Bulk-Micromachined MEMS Device Heung Woo Park, SeungHun Han, Hyun Kee Lee, Yeong Gyu Lee, Seoung Ho Kim, Bok Gun Moon, Taek Hee Yun, Min Seok Jang, Si Joong Yang, Sang Hun Park, Sung Jun Lee, Won Kyu Jeung, Jung Won Lee, Samsung Electro-Mechanics Co. The Use of Metallographic and SEM Analysis for Characterization of Sidewall Surfaces in MEMS Devices with DRIE Processing Colin Stevens, Robert Dean, Auburn University; Samuel Lawrence, Lehigh University; Lee Levine, Process Solutions Consulting Wafer Level Package with Y Shaped TSV and Vacuum Sealing by Cu-Sn Isothermal Solidification for MEMS Resonator Le Luo, Yuhan Cao, Shanghai Institute of Microsystem and Information Technology, Chinese Academy of Sciences MEMS Device Sealing in a High Vacuum Atmosphere Achieving Long Term Reliable Vacuum Levels Paul W. Barnes, SST International Hermetic Sealing of Stainless Steel Packages by Seam Seal Welding Thomas Marinis, Berj Nercessian, Charles Stark Draper Laboratory	Information for Session WP6 - Interactive Poster Session - can be found here

Thursday, November 4, 2010 | Morning Sessions: 8:00 AM - 12:00 PM
3D Packaging and Integration Track	Modeling and Reliability Track	Next Generation Materials Track	Assembly and Packaging Track	Advanced Technologies Track
THA1 State of 3D Technology – Consortia View Chair: Urmi Ray, Qualcomm, Inc. This special session is to discuss the State of 3D Technology in consortia view and to show case the exemplary research and development going on under a pre-competitive umbrella to enable the framework for faster industry adoption of 3D technology. The consortia activities in 3D-IC will also be presented. A panel session will follow to focus on “Roadmap, Technical and Business Progress of 3D Integration and Packaging” with questions/answers for both sessions. 8:00 Nicolas Sillon, Group Manager Packaging and Integration, CEA-Leti Minatec 8:25 Dorota Temple, Senior Fellow and Program Director, RTI International 8:50 Klaus Hummler, Senior Principal Engineer, 3D Interconnect Program, SEMATECH North 9:15 Break 10:20 Rozalia Beica, Program Director, EMC-3D Consortium Panel Discussion: 3D-TSV Integration and Packaging: Roadmap, Technical and Business Progress 10:45 am - 12:00 pm Moderator: James J.-Q. Lu, Rensselaer Polytechnic Institute Panelists: Klaus Hummler, Senior Principal Engineer, 3D Interconnect Program, SEMATECH North Philip Garrou, Consultant, Microelectronic Consultants of NC Urmi Ray, Senior Staff Engineer, Qualcomm, Inc. Rozalia Beica, Program Director, EMC-3D Consortium Nicolas Sillon, Group Manager Packaging and Integration, CEA-Leti Minatec Dorota Temple, Senior Fellow and Program Director, RTI International	THA2 Flip-Chip and Wafer Bumping: Processes and Reliability Chairs: Lyndon Larson, Dow Corning Flip-chip based devices have been around for long time, but the newest technology nodes and materials limitations are impacting reliability and performance. This session deals with flip chip processing and packaging innovations particularly focused on process and reliability improvements. Underfill for Ultra-Low Bumped (10u) 3D Package Mary Liu, Wusheng Yin, YINCAE Advanced Materials, LLC Effects of Crystallographic Orientation of Sn on Electromigration Behavior Kiju Lee, Keun-Soo Kim, Yutaka Tsukada, Katsuaki Suganuma, Osaka University; Kimihiro Yamanaka, KYOCERA SLC Technologies Co.; Soichi Kuritani, ESPEC CORP; Minoru Ueshima, SENJU METAL INDUSTRY CO., LTD. High Yield, Near Void-Free Assembly Process of a Flip Chip in Package Using No-Flow Underfill Daniel F. Baldwin, Engent, Inc.; Sangil Lee, Georgia Institute of Technology A Study of High Cu Behavior on Electrolytic Ni and Electroless Ni Pad Finish Hyun-Kyu Lee, Yong-Chul Chu, Myung-Ho Chun, Sang-Ho Jeon, DUKSAN HI-METAL CO., LTD Fine Feature Solder Paste Printing for Solder Sphere and Solder Trace Manufacturing Fred Haring, Nicole Dallman, Kaycie Gerstner, Syed Sajid Ahmad, Aaron Reinholz, North Dakota State University; Kristi Jean, North Dakota State College of Science Thermosonic Gold to Gold Intermettalic Advantages for CSP Packaging Philip Couts, TDK Corporation of America	THA3 Laminate Substrate Materials and Technology Chair: Ronald Jensen, Honeywell The papers in this session will present a number of novel materials and process technologies related to organic laminate substrates. These include halogen-free laminate materials for high density and rf applications, coreless laminate substrates, laminates with embedded passives, electroless copper plating for thru-hole metallization, and immersion silver plating for COB surface finish. Reliability Studies in Advanced Halogen-Free Organic Laminates for Ultra-Fine Pitch 3D Packaging Koushik Ramachandran, Fuhan Liu, Nitesh Kumbhat, Baik-Woo Lee, Venky Sundaram, Rao Tummala, Georgia Institute of Technology; Mark Wilson, The Dow Chemical Company Next Generation High Dk, Low Df Organic Laminate for RF Modules and High Frequency Applications Fuhan Liu, Vivek Sridharan, Tapobrata Bandyopadhyay, Venky Sundaram, Rao Tummala, Georgia Institute of Technology; Kiyoshige Kojima, Naomi Shiga, Zeon Corporation; Toshihiko Jimbo, Zeon Chemicals L.P. A New Coreless Substrate Technology Bend K. Appelt, Alex S. F. Huang, Bruce Su, Yi-Shao Lai, ASE Group Inc. Design, Fabrication, Electrical Characterization and Reliability of Nanomaterials Based Embedded Passives Rabindra N. Das, John M. Lauffer, Steven G. Rosser , Mark D. Poliks, Voya R. Markovich, Endicott Interconnect Technologies, Inc. High Aspect Ratio Package Core Production with Electrolytic Deposited Copper Stephen Kenny, Bernd Roelfs, Atotech Germany Cost-Effective Alternatives to Palladium Activation – A Study on Autocatalytic Electroless Copper Deposition Edith Steinhaeuser, T. A. Magaya, Atotech Deutschland GmbH Immersion Silver as Universal Surface Finish for COB Technology J. Goehre, M. Schneider-Ramelow, K.-F. Becker, M. Hutter, Fraunhofer IZM	THA4 Microwave and RF Applications Chairs: Scott Morris, RF Micro Devices; Art Prejs, CREE Measurement, modeling, and materials of RF and Microwave packaging will be examined in this session. The examination will vary from bandpass filters to transmission line optimization methods. Materials discussed includes, composites consisting of nano particles. Practical Implementation of Frequency Monitoring for Widely Tunable Bandpass Filters Hjalti H. Sigmarsson, Evan Binkerd, Jeff Maas, Juseop Lee, Dimitrios Peroulis, William J. Chappell, Purdue University Modeling and Optimization of Bond Wires as Transmission Lines and Integrated Antennas at RF/Microwave Frequencies Ivan Ndip, Christian Tschoban, Stefan Schmidt, Andreas Ostmann, Stephan Guttowski, Herbert Reichl, Klaus-Dieter Lang, Fraunhofer Institute for Reliability and Microintegration, IZM High Frequency Measurement Techniques for On-Chip Inductors Bruce C. Kim, University of Alabama; Dae-Hyun Han, Dong-Eui University; Seok-Ho Noh, Andong National University Chip Embedding for Printed Circuit Boards and Subsystems Thomas Gottwald, Alexander Neumann, Schweizer Electronic AG AuSi and AuSn Eutectic Die Attach Case Studies from Small (12 mil) to Large (453 mil) Die Daniel D. Evans, Jr., Zeger Bok, Palomar Technologies Study of Grounding Schemes Utilized in Conformal Shielding Applications Scott Morris, Dan Carey, RF Micro Devices	THA5 Printed and 3D Structural Electronics Chair: Mike Newton, nScrypt, Inc. Printed and 3D Structural Electronics is a technology sector that has been enabled by the convergence of new high resolution printing technologies in the graphics and additive manufacturing industries along with advances in electronics polymer and nanomaterials. This session will look at these advances in printing, materials and low temperature processing of electronics. Inkjet Printable Dispersions of Silver and Gold Nanoparticles Dan V. Goia, Krishna Balantrapu, Lu Lu, Ionel Halaciuga, Clarkson University Evaluation of PulseForge Tool for Processing Metallic Conductive Inks on Low Temperature Substrates Part II: Screen Inks S. Farnsworth, I. Rawson, K. Schroder, D. Pope, NovaCentrix® Correlation of Dispense Characteristics of Conductive Inks to Substrate Temperature Fred Haring, Justin Vignes, Syed Sajid Ahmad, Arun Shankaran, Kaycie Gerstner, Nicole Dahlman, Aaron Reinholz, North Dakota State University Ink-Jetting for Electronic Assembly Georg Meyer-Berg, Gottfried Beer, Klaus Pressel, Infineon Technologies Direct Printing/Micro-Dispensing Solution for 3D Coating Applications Xudong Chen, Kenneth Church, nScrypt Inc. Structural Electronics Through Additive Manufacturing and Micro-Dispensing Richard Olivas, Rudy Salas, Dan Muse, Eric MacDonald, Ryan Wicker, The University of Texas at El Paso; Mike Newton, Kenneth Church, nScrypt, Inc. Fabrication of Tall Structures for Microelectronics Application Using Selective Electrodeposition Process Bernd Scholz, WeiYang Lim, Ferdous Sarwar, Syed Sajid Ahmad, Aaron Reinholz, North Dakota State University