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IMAPS 2011 - Long Beach
44th International Symposium on Microelectronics
Bringing Together The Entire Microelectronics Supply Chain!

October 9 - 13, 2011
Long Beach Convention Center
Long Beach, California, USA

IMAPS 2011 - Long Beach

Conference and Exhibition:
October 11-13, 2011
Professional Development Courses:
October 9 - 10, 2011

Professional Development Courses (PDCs)

All Sunday PDCs are half-day, running 1:00 pm - 5:00 pm, unless otherwise noted
Monday PDCs run 9:00 am - 5:00 pm, unless otherwise noted

Do you want to broaden and strengthen your skills and knowledge, optimize your manufacturing processes, and integrate the latest advances in materials and technologies to maintain your strength in today’s competitive global market? The Technical Committee of IMAPS is pleased to present a comprehensive offering of Professional Development Courses that provide detailed information on topics of immediate interest to the Microelectronics and Packaging community.  So please be sure to choose from the 16 in-depth Professional Development Courses taught by recognized industry experts.  You will discover the following key ways that will benefit you.

  • Better understand the skills and knowledge necessary in today’s industry.
  • Be exposed to the rapidly expanding developments in new materials and technologies.
  • Consult with renowned authorities about your current R&D or manufacturing problems and challenges.
  • Learn new ways to identify, think about, and address your problems and opportunities.
  • Great opportunities to interact with industry experts and other course attendees.
  • Certificate of Attendance and much more…

Your PDC Registration Fee Includes:

  • Lunch on the day of your course
  • Refreshment breaks
  • All course materials
  • PDC Reception on Sunday evening (for Attendees & Instructors only)
  • Certificate of Attendance

PDC Lunches and Reception sponsored by:
Heraeus Materials Technology - Premier Sponsor, Gold

PDC Cancellation policy:

IMAPS reserves the right to cancel a course if the number of attendees is not sufficient.  You can transfer to a different course or we will refund you the corresponding amount.

during IMAPS 2011 Registrations

Sunday, October 9, 2011
All Sunday PDCs are ½ Day Course: 1:00 pm - 5:00 pm

S1: Design and Analysis of Experiments
Course Leader: Dr. Jianbiao (John) Pan, California Polytechnic State University

Course Description:
The Design of Experiments (DOE) is a vital tool in microelectronics packaging product/process development and product/process optimization. The appropriate use of DOE can improve product quality and decrease costs. This course will enable the participant to plan and conduct experiments, analyze the resulting data, and draw valid conclusions. Practical examples related to microelectronics and electronic packaging will be given to illustrate the use of designed experiments.

This course covers various experimental designs including single factor experiments, completely randomized block designs, full factorial and fractional factorial designs. At the end of this course, participants will be capable and confident in designing and analyzing experiments to improve and optimize manufacturing processes. Specifically you will be able to:

  • Select appropriate input variables and response variable(s)
  • Choose and conduct the appropriate type of experimental design
  • Perform ANOVA analysis, including main and interaction effects, and residual analysis to check assumptions
  • Draw valid conclusions
  • Use the Minitab software to create experimental designs and perform statistical analysis
    Students are encouraged to bring along laptop computers to use during class. If you don’t have access to Minitab, you can download a 30-day free trial copy from (

Who Should Attend?
Engineers, scientists, technicians, and managers in R&D, process development, and manufacturing, or individuals who desire to design their own experiments and/or analyze experimental data.

Dr. Jianbiao (John) Pan is an associate professor in Industrial and Manufacturing Engineering Department at Cal Poly State University, San Luis Obispo, California. He received a PhD in Industrial Engineering from Lehigh University, Bethlehem, PA. His research interests include the materials, processes, and reliability of microelectronics and optoelectronics packaging. He has studied extensively in improving microelectronics packaging processes and reliability using design of experiments methodology, and has published over 30 technical papers. He is a Fellow of IMAPS, a senior member of IEEE and SME, and a member of ASME and ASEE. Dr. Pan is a recipient of the 2004 M. Eugene Merchant Outstanding Young Manufacturing Engineer Award from SME, a Highly Commended Winner of the Emerald Literati Network Awards for Excellence in 2007, and the First Place winner of the IPC’s Academic Poster Competition in 2009. 

S2: Electrical Test Strategies for High-Density Packages
Course Leader: Bruce C. Kim, Ph.D., University of Alabama in Birmingham

Course Cancelled at request of Instructor

S3: MEMS Reliability and Packaging
Course Leader: Dr. Slobodan Petrovic, Oregon Institute of Technology

Course Description:
From accelerometers to biomedical devices, from pressure sensors to optical displays, and from tunable lasers to DNA sensors, MEMS (Microelectromechanical systems) technology is becoming an integral part of modern life. One of the biggest challenges hampering further progress of MEMS devices is the development of effective packaging solutions. The intended outcome of the course is to provide a comprehensive overview of the MEMS packaging and reliability principles; with a particular emphasis on sensors and actuators used in industrial, medical, and automotive applications. Examples of these applications include accelerometers, pressure sensors, angular rate sensors, micropumps, valves, and thermal inkjet heads. The packaging discussion will also cover a wide range of other MEMS principles and devices such biological and chemical sensors, optical imaging and displays, as well as photonic applications used in the fiber-optics industry. These applications will be illustrated using examples such as lab-on-a-chip, DNA sensor, radiation imager, micromirror device, tunable laser, and wavelength locker. Three extensive case studies that will be used to most effectively demonstrate diverse packaging principles are: accelerometers, pressure sensors, and digital micromirror devices. 

Who Should Attend?
This is a survey course structured in such a way to provide a comprehensive overview of a broad array of packaging and reliability issues. While some prior knowledge by the participants of MEMS in general is helpful, the packaging discussion will require a fairly detailed explanation of the principles of operation, fabrication methods, and materials used in building MEMS structures. The course is therefore open to participants with no prior MEMS knowledge and would provide a reasonably broad general introduction into the field. 

Dr. Slobodan Petrovic is an associate professor at the Oregon Institute of Technology in Portland, OR. His research interests are in the areas of MEMS fuel cells, sensor media compatibility, hydrogen generation and storage, and nanocatalysts for energy applications. Prior to joining OIT, Dr. Petrovic was teaching at the Arizona State University; and held appointments at Clear Edge Power as a Vice President of Engineering; at Neah Power Systems as Director of Systems Integration; and Motorola, Inc. as a Reliability Manager. Dr. Petrovic has over 25 years of experience in MEMS, sensors, energy systems; fuel cells and batteries; industrial electrochemical processes; and catalysis. He has over 50 journal publications and conference proceedings; 2 book contributions and 24 pending or issued patents. 

S4: Microwave Hybrid Design for Manufacturability (DFM)
Course Leader: Thomas J. Green, TJ Green Associates LLC

Course Cancelled

S5: Understanding Failure and Root-Cause Analysis in Pb-Free Electronics
Course Leader: Greg Caswell, DfR Solutions

Course Description:
Increasing needs for performance, low cost, and a constant turnover in the electronics industry makes improving functionality a constant topic of interest. This has become especially true during the transition to Pb-free electronics, as those companies that fail to respond promptly to field/warranty issues can be expected to be left behind.  How to ensure optimum quality/reliability of your Pb-free product? It all starts with root-cause analysis, which is the fundamental exercise in understanding how electronic products can and will fail.  This course provides an in-depth understanding of the failure mechanisms that are unique to Pb-free electronics and provides a comprehensive review of the tools and techniques to identify them. Mechanisms are addressed based upon their respective packaging, including component packaging, discrete components, printed circuit board, and interconnects. A physics of failure (PoF) based approach is taken, with an outline of drivers of these mechanisms, including defect-driven, overstress, and wearout, and how understanding of these stress-strength interactions can provide guidance on the appropriate corrective and preventative action. A wide variety of case studies, including red phosphorus in epoxy encapsulants, creepage corrosion in immersion silver, and solder joint failures, are provided as valuable teaching examples.

Who Should Attend?
This PDC is intended as an introductory to intermediate level course for designers, component engineers, quality engineers, reliability engineers, and their managers.

Mr. Caswell is widely recognized as a pioneer in SMT and has 40 years of experience in the industry. His experience encompasses circuit board fabrication and materials, advanced packaging (BGA, mBGA, CSP, Flip Chip, QFN), IC fabrication, solder reflow, robotics, RoHS, and bonding utilizing specialized nanotechnology. He has over 240 publications, including being the Editor of the 1st book on SMT. More recently, he has been heavily involved in implementing RoHS complaint and lead free manufacturing processes for customers. Greg, a Past President of IMAPS, also directed the ATW program from 1989-2000, which produced workshops each year on different aspects of current and emerging packaging technologies. He is currently the Editor in Chief for Advancing Microelectronics magazine. He has received the IMAPS Technical Achievement (1986), Fellow of the Society (1993), and Daniel C Hughes Memorial Award (1995). He received his BS in Electrical Engineering from Rutgers University and a BA from St. Edwards University in Austin.

S6: Mechanical Analysis & Design for Microelectronics Packages
Course Leader: Dr. Amaneh Tasooji, Arizona State University

Course Description:
The objective of this workshop is to provide an overview and understanding of mechanical design for microelectronics packaging. Mechanical design requirement and analysis approaches are discussed in this workshop. Fundamentals of (i) mechanical loading/deformation (stress-strain behavior, including thermal loading due to CTE-mismatch), (ii) materials behavior, and (iii) failure mechanisms (brittle/ductile fracture, creep, fatigue, DBTT effects) will be reviewed. The impact of various parameters (e.g., mechanical design, materials and processing) influencing package reliability/integrity will be revisited. Closed form solutions and analytical approaches (FEM, Finite Element Methods) used in mechanical design will be disused. Classical approach used in mechanical analysis, as well as, damage tolerant approach (with discussion on Linear Elastic Fracture Mechanics) will be presented. Case studies on die-cracking and solder-joint-failures, with focus on area array package design/analysis, will be reviewed. Mechanical metrologies such as Moire used in measuring package deformation (e.g., warpage) and validating analytical FEM results will be reviewed.

Who Should Attend?
Engineers in R&D, QA, QC, manufacturing, process development, and advanced technicians. It is assumed that participants have some familiarity with microelectronics packaging and general device assembly technologies.

Dr. Amaneh Tasooji has more than 23 years of industrial and academic experience in engineering and manufacturing. She received her Ph. D. in Materials Science and Engineering from Stanford University in 1982 and has a B. S. degree in Physics. Dr. Tasooji has extensive/diverse technical knowledge in materials and processing, component design, manufacturing, and quality/reliability in many industries such as microelectronics, aerospace, and nuclear. She has had many technical and leadership responsibilities while at Honeywell/AlliedSignal and has developed many materials behavior, deformation, and fracture models for reliability analysis. Dr. Tasooji was the recipient of many technical/engineering and leadership awards including ASTM Sam Tour Award for distinguished contribution to research, development, and evaluation of corrosion testing and modeling. Dr. Tasooji has developed and delivered many graduate engineering courses (e.g., “Introduction to Micro-electronic Packaging,” “Overview of Materials Science and Engineering for Microelectronics Packaging,” “Advanced Packaging Analysis and Design: Material Considerations,” “Nuclear Materials”) and many undergraduate courses at Arizona State University (ASU). She has leveraged new technology and e-learning concepts in developing and offering conventional (face-to-face) and hybrid courses (on-campus and distance training) at ASU, emphasizing the Interactive Learning concept, and providing professionals with tools/opportunity for continuous learning. 

S7: Polymeric Packaging Requirements for Solar Modules
Course Leader: Michelle Poliskie, Consultant

Course Cancelled

S8: Technology Advances in 3D-TSV Integration and Packaging
Course Leader: Dr. James Jian-Qiang Lu, Rensselaer Polytechnic Institute

Course Description:
Based on the instructor’s 3D research activities since late 1990s, this course will discuss the latest development of Through-Strata-Vias (or Through-Si-Vias, TSVs) and other relevant enabling technologies for 3D IC integration and packaging. A comprehensive overview of 3D integration and packaging technologies will be presented, including motivation, key technologies, technology assessment and status towards commercialization.

In this course, 3D hyper-integration technologies are divided into 4 categories – 3D packaging, chip-to-wafer (C2W) assembly, transistor build-up, and wafer-to-wafer (W2W) 3D. For 3D packaging, the ICs are packaged vertically in chip-to-chip (C2C), system-in-packaging (SiP) and package-on-package (PoP) fashions. The C2W assembly is similar to SoC approach, but with known-good-dies (KGDs) assembled on an IC wafer, then processed in wafer-level. In transistor build-up 3D, active devices are built-up over an IC wafer. In W2W 3D, different systems are first fabricated independently and then stacked and interconnected vertically.

This course will discuss all these technologies, with emphasis on advances of Through-Strata-Vias (TSVs) technologies, 3D platforms and potential applications.  A particular focus will be on various TSV fabrication/processing methods and applications, with relevant critical issues addressed, such as TSV processing, alignment, bonding, wafer thinning and handling for C2C, C2W and W2W integration platforms.  Sample designs and applications towards commercialization will also be presented. The issues associated with each technology category will be discussed, including integration architecture and design tools, yield and cost, thermal and mechanical constraints, and manufacturing infrastructure. Finally, future directions into micro/nano/electro-opto/bio system hyper-integrations including MEMS will be presented, showing 3D-TSV hyperintegration as a very promising emerging architecture for future computer, network, nanotech, and biotech applications.

Who Should Attend?
Engineers and managers involved in future R&D investments, assembly and product development of electronic packaging, and wanting fundamental understanding of 3D-TSV technologies, as well as the materials and equipment suppliers wanting to know about the existing and future 3D-TSV technologies and options, will greatly benefit from this course.

James Jian-Qiang Lu is currently an Associate Professor in Electrical Engineering at Rensselaer Polytechnic Institute (RPI), Troy, NY. Dr. Lu has worked on 3D hyper-integration technology, design and applications for more than a decade. He has >200 publications in the areas from micro-nano-electronics theory and design to materials, processing, devices, integration and packaging. He gave a number of invited presentations, seminars and short courses. Dr. Lu served as technical chair, workshop chair, session chair, panelist and panel moderator, and conference committee members for many conferences. He is a Fellow and Life Member of IMAPS, and an IEEE Fellow for contributions to three-dimensional integrated circuit technology. He has served as the 3D Packaging Chair of the IMAPS National Technical Committee since 2006. He is a recipient of the 2008 IEEE CPMT Exceptional Technical Achievement Award for his pioneering contributions to and leadership in 3D integration/packaging and the 2010 IMAPS William D. Ashman Achievement Award for contributions and research in 3D integration and packaging and for leadership contributions at IMAPS conferences.

S9: Counterfeit Electronics - Risks and Mitigation
Course Leader: Bhanu Sood, University of Maryland

Course Description:
A counterfeit electronic part is one whose identity has been deliberately misrepresented. Identity of the part can include information such as manufacturer, date code, lot code, certificates of conformance or reliability ratings. Counterfeit electronics have been reported in a wide range of products, including computers, telecommunications equipment, automobiles, avionics and military systems. In addition to losses to legitimate producers of components, equipment failures or malfunctions can present situations that can cause mission failures, health and safety concerns, and even threats to national security. Counterfeit products can include everything from inexpensive capacitors and resistors to costly high-end microprocessors. Unfortunately, this problem is growing rapidly and no signs of abatement are in sight.

Lecture topics in course will include:

  • Introduction to counterfeit electronic parts
  • Electronic part supply chain
  • Counterfeit parts: types and examples
  • Sources of counterfeit parts
  • Testing and characterization
    • Visual inspection
    • Optical microscopy
    • Radiological inspection (X-ray)
    • Scanning acoustic microscopy
    • X-ray fluorescence spectroscopy (XRF)
    • Environmental scanning electron microscopy (ESEM) / Energy Dispersive Spectroscopy (EDS)
    • Materials characterization tools (DSC/FTIR/TMA/DMA)
    • Electrical testing
  • Mitigation techniques and few anti-counterfeiting efforts

Who Should Attend?
Component Engineers, Failure Analysis Engineers, Reliability Engineers, Engineering Managers, Procurement Managers, Quality Assurance functions, Contracts Personnel and anybody who is involved in policy making activities in fields of marketing or procurement of electronics parts or assemblies.

Mr. Bhanu Sood is Director of the Test Services and Failure Analysis (TSFA) Laboratory at the Center for Advanced Life Cycle Engineering (CALCE), University of Maryland. He received M.S. degrees in advance material processing and materials science from National Technical University and George Washington University respectively. His research areas include electronic materials characterization, failure mechanisms in printed circuit board (PCB) materials, electronic supply chains and counterfeit electronic parts detection techniques. Prior to joining CALCE in 2005, Mr. Sood worked at U.S. Naval Research Laboratory (NRL) in Washington DC, where he developed embedded electronic circuits using laser-assisted prototyping techniques. Mr. Sood has developed and taught industry courses in the areas of electronics reliability, root cause failure analysis techniques and counterfeit electronics. He has authored scholarly and technical papers in the areas of root cause failure analysis methodologies, PCB failure mechanisms, embedded electronics, and topics on instrumentation. Mr. Sood is a member of IEEE and ASM.

Monday, October 10, 2011
Monday PDCs run 9:00 am - 5:00 pm, unless otherwise noted

M1: Advanced Packaging Technologies: Multichip, 3-D, Chip Scale & Embedded Chip
Course Leader: Ray Fillion, Fillion Consulting

Course Description:
Advances in microelectronics packaging have become critical driving forces in the advancement of computing and portable electronics markets. Key technologies include multichip, 3-D, chip scale packaging and the newest advance, embedded chip packaging. This course will give an overview of semiconductor advances for the past 40 years and will cover how they are effecting packaging requirements. It will go into details of the various multichip approaches: SoP, SiP, MCP and MCM technologies; 3-D approaches: chip, substrate and package stacking; Chip Scale approaches: wafer and package level; and embedded chip approaches: single chip and multichip. It will look at the basic features of these packaging approaches, their construction and the processes used to fabricate and assemble them. It will look at the leading approaches and their inherent advantages and disadvantages. This course will cover key issues including yields, component handling, availability and second sourcing. The course will look at the leading companies implementing various versions of these technologies, cover the key differentiators between them and show how these packaging technologies have contributed to the advancements made in a wide range of both portable and high-end electronics.

Who Should Attend?
This course covers basic and advanced topics for product and design engineers, manufacturing process and assembly/packaging engineers, engineering managers, senior design technicians, consultants and academic specialists as well as marketing and sales personnel requiring an understanding of the capabilities, implications and options of advanced packaging and assembly technologies.

A BSEE graduate of University of Massachusetts, Ray Fillion has more than 40 years experience at GE Aerospace Electronics and GE Global Research in technical, management, licensing and business development positions. Mr. Fillion also serves or has served on Advisory Boards for a variety of technical societies, industry, academic institutions and governmental panels. He has taught courses on advanced packaging for SMTA, GE and several universities. He was the lead inventor of the embedded chip technology at GE with most of his 27 issued US patents covering embedded chip technologies. His technical areas of expertise include chip scale packages, multichip modules, 3-D packaging, power packaging, packaging for cryogenic and high temperature electronics, and microwave packaging. He has more than 125 technical publications through IMAPS, IEEE, SMTA, ECTC, SMTA and various workshops. 

M2: Polymers in Electronic Packaging
Course Leader: Dr. Jeff Gotro, InnoCentrix, LLC

Course Description:
The course will provide an overview of polymers and the important structure-property-process-performance relationships for electronic packaging. The main learning objectives will be 1) understand how polymers are used in electronic packaging, 2) learn why specific chemistries are used depending on the application, 3) learn the fundamentals of polymer characterization related to electronic packaging, 4) develop a foundation in rheology and rheology issues in electronic packaging. Participants are invited to bring problems for discussion.

Who Should Attend?
Packaging engineers involved in the development, production, and reliability testing of electronic packages would benefit. Those interested in gaining a basic understanding of the role of polymers and polymer-based materials used in electronic packaging will also find this series valuable.

Dr. Jeff Gotro has over twenty-eight years experience in polymers for electronic applications and composites having held scientific and leadership positions at IBM, AlliedSignal, Honeywell, and Ablestik Laboratories. Jeff is a nationally recognized authority in thermosetting polymers and has received invitations to speak at the prestigious Gordon Research Conferences (Thermosetting Polymers and Composites). He has presented numerous invited lectures and short courses at technical meetings, has over 60 technical publications and 21 patents/patent applications. Jeff was an Adjunct Professor at Syracuse University in the Dept. of Chemical Engineering and Materials Science from 1986-1993. Jeff is a member of the Product Development and Management Association (PDMA), American Chemical Society (ACS), Institute for Management Consultants (IMC), Forensic Expert Witness Association (FEWA), and the International Microelectronics And Packaging Society (IMAPS).

M3: Hermeticity Testing, RGA and “Near Hermetic” Packaging Concepts
Course Leader: Thomas J. Green, TJ Green Associates LLC

Course Description:
Hermeticity of electronics packages for Military, Space and Medical Class III device implant applications continues to be of critical importance. This course begins with an overview of hermetic sealing processes. Then the accepted leak test methods in Mil specs are described in detail, with an emphasis on the impact of tighter leak spec requirements. Issues with bomb times and pressures, measured leak rate vs air leak rates, helium desorption and other relevant issues will be addressed. The focus will be on practical issues facing the industry. The basic science and applicability of Optical Leak Test (OLT), Cumulative Helium Leak Detection (CHLD) and KR-85 radioisotope testing will be described with plenty of time for questions. The gas ambient inside the package is measured using Residual Gas Analysis. What is RGA and how does it relate to hermeticity testing? Packages made from polymeric materials as opposed to traditional hermetic seals (i.e., metal, ceramic, etc.) require a different approach from a testing standpoint. The problem is now one of moisture diffusion through the barrier and package interfaces.  Leak test data only provides a single, one time room ambient check of the integrity of the hermetic seal.  However, leak rates change with time based on temperature, pressure and ambient humidity conditions.  The solution is a moisture sensor mounted inside the device to monitor moisture ingress as a function of time.  Issues with “near hermetic” packages will also be discussed.

It is recommended that you purchase a copy of the text book “Hermeticity of Electronic Packages” by Hal Greenhouse (Noyce Publications 2000). Instructors will also provide a handout on “Practical Guide to TM 1014” authored by Mr. Green

Who Should Attend?
This PDC is intended as an introductory to intermediate level course for process engineers, designers, quality engineers, and managers responsible for sealing, leak testing, RGA results and “near hermetic” package testing.

Mr. Thomas Green is an independent consultant and respected teacher. Tom is the principal at TJ Green Associates LLC (, a veteran owned small business specializing in teaching and consulting for the microelectronics industry. Tom previously worked at Lockheed Martin Astro Space in Denver CO and Valley Forge PA and at USAF Rome Laboratories. At Lockheed he was a Staff engineer responsible for the materials and manufacturing processes used in building custom high reliability space qualified hybrid microcircuits for military satellites. Tom has demonstrated expertise in wirebonding, component attach, and seam sealing processes for hybrid microwave products. At Rome Labs he worked as a senior reliability engineer and analyzed component failures from AF avionic equipment. Tom is an active member of IMAPS and a Fellow of the Society. He has a B.S. in Materials Engineering from Lehigh University and a Masters from the University of Utah.

M4: Technology of Screen Printing
Course Leaders: Arthur Dobie, Sefar, Inc.; David Malanga, Heraeus Materials Technology LLC - Thick Film Materials Division

Course Description:
Screen printing continues to offer innovative and cost effective solutions to the increasing demands for higher circuit densities. This course is intended to increase the understanding of the screen printing process, thereby improving production yield and print quality. Presented are some of the latest advancements in composition, screens, and printing technology that enable screen printing to meet future circuit density requirements as well as the definition required for microwave circuitry. The advantages of screen printing, an additive deposition process, are described and compared to alternative more costly and “less-green” subtractive deposition technologies. This course is applications-oriented in terms of how to optimize the screen printing process; how to use and specify screen correctly; rheology properties that affect print results; minimizing printing defects and trouble-shooting problems related to screens, inks and the printing process itself. 

Who Should Attend?
This course is targeted for production and process engineers, plant and production managers and supervisors, and any others interested in learning how to optimize and increase the use of the screen printing process.

Art Dobie is Senior Territory Manager for Sefar, Inc. He has been with Sefar over 30 years since receiving his BS in Screen Printing Technology in 1980 from California University of Pennsylvania.  Art has co-instructed the IMAPS “Technology of Screen Printing” PDC since its inception in 1991. He has delivered numerous technical presentations to screen-printing professionals at local, national and international level symposia.  Mr. Dobie is a Life Member and Fellow of the Society of IMAPS, and received the 2006 IMAPS Technical Achievement Award for outstanding technical contributions to screen printing technology relating to microelectronics. In 1998, Art Dobie was inducted into the SGIA’s Academy of Screen Printing Technology and is a co-recipient of the SGIA’s 2010 David Swormstedt, Sr. Memorial Award.

David Malanga is currently the Business Unit Manager Americas, Thick Film Materials Division of Heraeus in West Conshohocken, PA.  David has over 20 years of experience at Heraeus working in R&D, formulating thick film and LTCC materials, Technical Service solving processing and application problems directly with customers, and as manager of the Sales Department.  David has a B.S. and M.S. in Ceramic Science and Engineering from Rutgers University. David has published various articles on thick film resistors, conductors, LTCC materials, and component metallizations worldwide. He is a Life member and Fellow of the Society of IMAPS and has held both local and national positions in the organization.

M5: Microelectronics Packaging Industry Updates and Trends
Course Leader: Phillip G. Creter, Creter & Associates

Course Description:
This NEW course features the latest in microelectronics industry updates and trends with a focus on new technology for all levels of technical experience. Each section includes a short basic review to allow easy understanding by an attendee with no prior knowledge of microelectronics. Major sections include wafer sawing, chip attach, interconnect, and final packaging. New processes/materials will include stealth dicing for wafer singulation, coping with ultra low-k dielectric problems, handling thin wafers/thin chips for bonding, sintered nanosilver chip attach, fine pitch copper wire bonding, flip-chip underfill, embedded chips, interposers, 3D-IC TSV, liquid crystal polymer for packaging, LED packaging, Wafer Level Packaging, Fan-In/Fan-Out WLP, MEMS, System-in-Package, and System-on-Chip. New applications details from industry leaders include Draper Labs (integrated-ultra-high-density circuits), Intel (32nm Sandy Bridge microprocessor), Infineon/STATSChipPAC (next generation embedded-wafer-level-BGA), Texas Instruments/Amkor (fine pitch copper pillar flip-chip packages), IBM (injection-molded-soldering) and others. Highlights of the Assembly and Packaging sections of the current International Technology Roadmap for Semiconductors provide updated packaging definitions and projections of future technology gaps for wafer-level packaging, wafer thinning, singulation and bonding for 3D integration, optoelectronics and Thru-Silicon-Vias. Emphasis will be on visual aids with pass-around microcircuit samples, and a variety of photos, figures and videos. An invaluable 200-page handout includes over 100 references.

Who Should Attend?
Designed for all levels of engineers including others with little knowledge of microelectronics packaging. Includes topics for sales/marketing, purchasing, safety, and management.

Phillip Creter has over 30 years of microelectronics packaging experience. He is currently a consultant gaining his microelectronics packaging experience at Polymer Flip Chip Corporation, Mini-Systems, GTE and Itek Corporation. His past positions include GTE’s Microelectronics Center Manager (received GTE Corporate Technical Achievement Award), Process Engineering Manager, Process Development Manager, Materials Engineering Manager, and Manufacturing Engineer. He has published more than a dozen technical papers, holds a U.S. patent, has given over twenty technical presentations, and has chaired numerous technical sessions for symposia. He has been teaching courses at the college level since 1997 and since 2004, has continuously taught microelectronics PDCs for online webinars and at various symposia and workshops. He is an active certified instructor for the Department of Homeland Security currently teaching courses locally. He is a Life member of IMAPS. He was elected Fellow of the Society, National Treasurer and President of the New England Chapter (twice).

M6: TSV and Key Enabling Technologies for 3D IC/Si Integration and WLP
Course Leader: Dr. John H. Lau, ITRI

Course Description:
3D integration consists of 3D IC packaging, 3D IC integration, and 3D Si integration, which will be discussed in this lecture. Emphases are placed on the key enabling technologies for 3D IC/Si integrations, such as TSV (through-silicon via) forming and filling, front and back-side metallization, RDL (redistribution layer), IPD (integrated passive devices), temporary wafer bonding, wafer thinning and handling, wafer de-bonding, thin chip/wafer strength measurement and improving, Cu-Cu and SiO-SiO W2W bumpless bonding, lost-cost lead-free microbumping (d”15µm pitch) and assembly, low-temperature wafer bumping and C2C, C2W, and W2W bonding, and thermal management including hot-spot temperature and fluidic microchannels. Useful characterization and reliability data for 3D IC integration will also be provided. The application of 3D IC integration such as CMOS image sensor, MEMS, LED, memory + logic, logic + logic, memory + microprocessor, active and passive interposers, and wide I/O heterogeneous structures will be presented. More than 15 companies’ passive interposes (not just Powerpoint engineering but with samples) used as substrates, carriers, and thermal management tools will be presented and discussed. Furthermore, the critical issues of TSV and 3D IC integration will be given and some potential solutions or research topics will be recommended. Finally, TSV manufacturing yield and hidden costs will be discussed and several roadmaps of 3D IC/Si integration will be provided. All the materials are based on the technical papers and books published within the past 3 years by the lecturer and others.

Who Should Attend?
If you (students, engineers, and managers) are involved with any aspect of the electronics, LED, MEMS, and optoelectronic industry, you should attend this course. It is equally suited for R&D professionals and scientists. You will receive more than 300 pages of handouts from the Instructor’s books, “Advanced MEMS Packaging” (McGraw-Hill, 2000) and “Reliability of RoHS Compliant 2D & 3D IC Interconnects” (McGraw-Hill, 2011).

Dr. John Lau has been a Fellow of ITRI in Taiwan since January 2010. Prior to that, he was a visiting professor at HKUST for 1 year, the Director of MMC Laboratory with IME in Singapore for 2 years and a Senior Scientist/MTS at HP/Agilent in California, US for more than 25 years. With more than 35 years of R&D and manufacturing experience, he has published more than 350 peer-reviewed papers, 100 book chapters, 30 issued and pending US patents, and given 270 lectures/workshops/keynotes worldwide. He has published 16 textbooks on 3D MEMS packaging, reliability of 2D and 3D IC integrations, flip chip & WLP, high-density PCB, SMT, and lead-free materials, soldering, manufacturing and reliability. John earned his PhD degree from the University of Illinois and three MA.Sc degrees in North America. John received many awards from ASME, IEEE, SME and other societies for best ASME Transactions paper, best IEEE/ECTC Proceedings paper, ASME and IEEE outstanding technical achievements, SME total excellence in electronics manufacturing, and IEEE meritorious achievement in continuing education. He is an elected ASME Fellow and has been an IEEE Fellow since 1994. 

M7: Plating Processes for High Reliability Microelectronic Devices
Course Leader: Fred Mueller, CEF, General Magnaplate Corp.

Course Description:

  • Electroplating for a variety of applications - Provide a thorough overview of plating for electronics including wire bonding, lead free solder plating/prevention of whiskers, the use of electroless nickel - immersion gold (ENIG) and other metals/processes that are used in the field of electronics.
  • Introduce the value of different rectifiers wave forms used in plating for electronics.
  • Present laboratory methods for controlling the quality of the plated deposit.
  • Highlight the engineering differences in plating processes.

Who Should Attend?                         
This course is intended as an introductory to intermediate level course for process engineers, quality engineers, and managers responsible for Electronic Finishing.

Mr. Mueller is employed in the metal finishing industry and serves as a national certified instructor for the American Electroplaters and Surface Finishing Foundation (AESF). Fred has experience as a Nadcap Chemical Process Auditor. He has over twenty-five years experience in the plating industry in printed circuits and plating for electronics. He is currently the National Quality Manager at General Magnaplate, Linden, NJ. As a Chemist, Fred has conducted experiments and presented technical papers at SurFin on various topics in electroplating.  

M8: Modeling and Optimization of Electronic Packaging Structures for Signal and Power Integrity
Course Leaders: Dr. Ivan Ndip, Fraunhofer IZM; Professor Ege Engin, San Diego State University; Dr. Antonio Ciccomancini Scogna, Computer Simulation Technology (CST) of America

Course Description:
Successful and low-cost design of electronic packages and boards requires (in addition to thermal and thermo-mechanical issues), a good understanding of the root causes of signal integrity (SI), power integrity (PI) and electromagnetic interference (EMI) issues, as well as methods to analyze, prevent or solve them. The objective of this course is to provide methods for accurate and efficient electrical modeling, measurement and optimization of packages and PCBs, under consideration of SI, PI and EMI/EMC issues. Techniques for extracting the relative dielectric constant and loss tangent of packaging materials will also be discussed. Finally, guidelines for optimizing the electrical performance of high-speed packages and PCBs will be provided.


  • High-speed design challenges
  • Modeling and optimization of packaging structures for SI
    • Lossy transmission lines considering surface roughness and tapered cross section
    • Signal vias considering their return-current paths
    • Through silicon vias (TSVs)
  • Modeling and optimization of packaging structures for PI
    • Power-ground plane pairs and simultaneous switching noise (SSN)
    • Electromagnetic band gap (EBG) structures and photonic crystal power/ground layers (PCPLs) for suppressing SSN coupling
  • Modeling and extraction of relative dielectric constant and loss tangent of packaging materials

Who Should Attend?
Engineers, scientists, researchers, designers and managers involved in the process of electrical modeling, layouts and/or design of single-chip packages, system packages (e.g., SiPs, SoPs, MCMs), PCBs and their interconnections.

Dr. Ivan Ndip obtained his M.Sc., and Ph.D. with the highest distinction (Summa Cum Laude) in electrical engineering from the Technical University Berlin, Germany. In 2002, he joined the Fraunhofer-Institute for Reliability and Microintegration (IZM) Berlin as a Research Engineer and worked on signal integrity modeling and design as well as on antenna integration. Since 2006, he has been a Senior Research Engineer and Group Manager of RF & High-Speed System Design, where he’s responsible for leading a team of Research Engineers and Graduate Students as well as for developing and leading research projects that focus on electromagnetic modeling, design and optimization of RF/high-speed packages/boards/modules, integrated antennas and passive RF front-end components.

Since 2008 Dr. Ndip has also been a Lecturer in the Department of High-Frequency and Semiconductor System Technologies, School of Electrical Engineering and Computer Sciences, Technical University Berlin. He is currently engaged in teaching courses on Numerical Techniques in Electromagnetics and on Electromagnetics for Design and Integration of Microsystems. He has more than 100 publications and has won 6 best paper awards at leading international conferences. Dr. Ndip is also a recipient of the Tiburtius-Prize, awarded yearly for outstanding Ph.D. dissertations in the state of Berlin, Germany.

Dr. Ege Engin received his B.S. and M.S. degrees in electrical engineering from Middle East Technical University, Ankara, Turkey, and from University of Paderborn, Germany in 1998 and 2001, respectively. He received his Ph.D degree with Summa Cum Laude from the University of Hannover, Germany in 2004.  Dr. Engin has worked as a research engineer with the Fraunhofer-Institute for Reliability and Microintegration in Berlin, Germany and at Georgia Tech. He is currently an Assistant Professor in the Electrical and Computer Engineering Department of San Diego State University. He has more than 60 publications in the areas of signal and power integrity modeling and simulation and 4 patent applications. He has co-authored the book “Power Integrity Modeling and Design for Semiconductors and Systems,” published by Prentice Hall in 2007.

Dr. Antonio Ciccomancini Scogna received the Laura and Ph.D. degrees in electrical engineering from the University of L’Aquila, L’Aquila, Italy, in 2001 and 2005, respectively.  He is currently a Principal Engineer at Computer Simulation Technology (CST) of America, Framingham, MA. His research interests include electromagnetic compatibility numerical modeling, printed and integrated circuits, electromagnetic packaging effects, signal integrity and power integrity analysis in high-speed digital systems. He has authored or coauthored more than 50 publications in IEEE journal transactions, IEEE conference proceedings, and Electronic Design Automation (EDA) magazines. Dr. Ciccomancini is a member of Applied Computational Electromagnetic Society (ACES), Institution of Engineering and Technology (IET), EMC TC-9 and TC-10 Committees. In 2004, he received the CST University Publication Award for the use of the finite-integration technique in signal integrity applications. He is the recipient of DesignCon Finalist Best Paper Award in 2007 and DesignCon Best Paper Award in 2008.

M9: Wire Bonding in Microelectronics
Course Leader: Lee Levine, Process Solutions Consulting, LLC

Course Description:
Wire bond manufacturing defects range typically from about 1000 to 100 ppm, with exceptions to >10,000 and <50 ppm. In order to achieve the lower numbers in production, one must understand all of the conditions that affect both bond yield and reliability (since they are interrelated). This course will discuss many small- and large-wire bonding problems, as well as subjects of specific interest to hybrid/MCM device bonding. In addition, a number of advanced topics, such as high yield, fine pitch (towards 25 mm ball bond pitch), and bonding to flex will be covered. Newer developments are included along with a major discussion of wire bonding to multichip substrates, soft substrates, Cu-Lok and the special intermetallic problems occurring when fine pitch chips are used. Wire bond testing and metallurgy (covering both aluminum and gold bonds); intermetallic compounds in general; cratering; cleaning for high yield and reliability; failures resulting from electroplating; mechanical problems in wire bonding; new bond technologies and developments; how ultrasonic bonds are formed, and the metallurgy of gold and aluminum wire. It concludes with methods of making very low loops, implementing TAB and Flip Chip by using wire bonding/stud bumping techniques.

It is recommendation of the instructor that you purchase a copy of the text book “Wire Bonding in Microelectronics,” by George Harman, McGraw Hill, NY, 2010.

Who Should Attend?
Engineers in R&D, QA, QC, manufacturing, process development, and advanced technicians. It is assumed that participants have some familiarity with wire bonding and general device assembly technologies.

Lee’s experience includes 20 years as Principal and Staff Metallurgical Process Engineer at Kulicke & Soffa and Distinguished Member of the Technical Staff at Agere Systems. Currently he consults for his own company, Process Solutions Consulting, Inc. providing process consulting, yield improvement, SEM, EDS and Metallography services to the microelectronics industry. He has been awarded 4 patents, published more than 70 technical papers, and won the 1999 John A. Wagnon Technical Achievement award from the International Microelectronics And Packaging Society (IMAPS). Major innovations include copper ball bonding, loop shapes for thin, small outline packages (TSOP and TSSOP, and CSPs) and introduction of DOE and statistical techniques for understanding assembly processes. He is an IMAPS Fellow and former IMAPS V.P Technology. Lee is also a Contributing Editor for Test and Packaging Times (, an online newsletter, where he publishes a column “Levine on Bonding”. Lee is a graduate of Lehigh University, Bethlehem, Pa where he earned a degree in Metallurgy and Materials Engineering.

M10: Basics of Microelectronic Packaging
Course Leader: Casey Krawiec, Quik-Pak

Course Description:
This course explains the fundamentals of microelectronic packaging technology. No prior knowledge of microelectronics is required. This course will provide the student with an overview of the history of microelectronics, core terminology and concepts, and the critical functions of microelectronic packaging. Students will learn the basic types of microelectronic packaging from a materials perspective. Regarding materials and package technology selection, students will gain an appreciation of the trade-offs between cost, performance, and reliability. The course will provide an overview on package assembly and test, and will conclude by reviewing the future/emerging packaging technologies.

Who Should Attend?
The course is for entry-level engineers, technicians, and others involved in manufacturing, purchasing, processing, R&D, quality, sales, and marketing. At the conclusion of this course, the student will be familiar with microelectronic packaging terminology, know the function and purpose of microelectronic packaging, understand the conditions that drive package selection (performance, cost, reliability), understand what drives material selection in package construction, and appreciate why so many packages are custom designs.

Casey Krawiec is Global Sales and Marketing Manager at Quik-Pak, a division of Delphon Industries. Previous positions include Vice President of North American Sales at StratEdge Corporation and Offshore (International) Sales Manager at Kyocera America. He began his career as a design engineer for the Department of the Navy. He has an MBA from the University of Louisville and a BS in Mechanical Engineering from the University of Kentucky. He is an officer in the local chapters of both International Microelectronics And Packaging Society and the American Society of Mechanical Engineers.

M11: RF/Microwave Hybrids; Basics, Materials and Processes
Course Leader: Richard Brown, Richard Brown Associates, Inc.

Course Cancelled

M12: An Electronics Expert Reliability Analysis Tool
Course Leader: Greg Caswell, DfR Solutions

½ Day Course: 8:00 am - Noon

Course Cancelled

M13: Area Array Microelectronics Package Reliability
Course Leader: Dr. Amaneh Tasooji, Arizona State University
½ Day Course: 1:00 pm - 5:00 pm

Course Cancelled



Event Sponsors

Logo Bags, Final Program, Internet Café and Convention Hall Signs:
NATEL - Platinum Sponsor

Logo Bags, Final Program, International Reception, Hotel Key Cards and Note Pads/Pens for Technical Sessions:
Heraeus Materials Technology - Premier Sponsor, Gold
Logo Bags, Final Program, and Lanyards :
Metalor - Premier Sponsor, Silver
GBC Forum/Reception:
Sikama - GBC Forum/Reception Sponsor
LORD - Golf "Birdie" Sponsor
Keynote Presentations:
Indium Corp - Keynote Sponsor
Exhibit Hall Lunch:
Kyocera America - Exhibit Lunch Sponsor
Bag Insert:
RIV Inc. - Bag Insert Sponsor
Golf Sponsors
Golf "Birdie" Sponsor:
LORD - Golf "Birdie" Sponsor
Golf Ball Markers:
Circuit Solutions, Inc. - Golf Ball Markers Sponsor
Golf Hole Sponsor:
Technic - Golf Hole Sponsor
Golf Hole Sponsor:
Golf Hole Sponsor: Coining Inc/Ametek
Golf Hole Sponsor:
Golf Hole Sponsor: AGC Electronics America
Golf Hole Sponsor:
Golf Hole Sponsor: Dixon Golf
Golf Hole Sponsor:
Golf Hole Sponsor: Ceradyne Viox
Media Sponsors
Chip Scale Review - Media Sponsor
US Tech - Media Sponsor
MEPTEC - Media Sponsor


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IMAPS-International Microelectronics And Packaging Society and The Microelectronics Foundation
611 2nd Street, N.E., Washington, D.C. 20002
Phone: 202-548-4001