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IMAPS 2011 - Long Beach
44th International Symposium on Microelectronics
Bringing Together The Entire Microelectronics Supply Chain!

October 9 - 13, 2011
Long Beach Convention Center
Long Beach, California, USA
www.imaps2011.org

IMAPS 2011 - Long Beach

Conference and Exhibition:
October 11-13, 2011
Professional Development Courses:
October 9 - 10, 2011

Early Registration Deadline Extended to: September 16, 2011
Hotel Deadline Extended to: September 16, 2011


Technical Program


Technical Program (Sessions)


 


Tuesday, October 11, 2011 | Morning Sessions: 8:00 AM - 11:10 AM

3D Packaging Track
Modeling, Design and Reliability Track
Next Generation Materials Track
Advanced Technologies Track
Focus Track: Adv. Packaging & System-Integration

TA1
3D - TSV Process and Materials

Chairs: James Lu, Rensselaer Polytechnic Institute; Timothy G. Lenihan, TechSearch International

This session focuses on the latest development in 3D Through-Silicon-Via (TSV) and related processes and materials, including TSV process, redistribution layers, underfill, X-ray inspection, thermal design and integration of pressure sensor.

Optimization of SiO2, Barrier/Seed Layers, and Cu Plating for a 300mm Wafer
L. Wu, March Chen, Charles Tzeng, J. H. Lau, ITRI

Use of Wafer Applied Under Fill for 3D Stacking
Antonio La Manna, K. J. Rebibis, C. Gerets, E. Beyne, IMEC                   

A Path Toward Non-Destructive 3D Metrology for Through-Silicon Vias
Jeff Gelb, Luke Hunter, Allen Gu, Tiffany Fong, S. H. Lau, Wenbing Yun, Xradia, Inc.                   

Equivalent Thermal Conductivities and Design Guidelines for Through Silicon Vias (TSVs) in 3D IC Integration
Jack Heng-Chieh Chien, Yu-Lin Chao, Ra-Min Tain, John H. Lau, ITRI

Integration of Piezoresistive Pressure Sensor with ASIC by Through Silicon Via (TSV) Technology
Tao Wang, Jian Cai, Qian Wang, Hao Zhang, Zheyao Wang, Tsinghua University

TA2
Electrical Modeling, Signal & Power Integrity

Chair: Judy Priest, Cisco System, Inc.; Sanjeev Gupta, Agilent Technologies

This session will showcase novel design and verification techniques for high speed digital systems. Topics related to SERDES modeling, interconnect modeling, Signal Integrity, Power Integrity, and EMI will provide valuable insight to system architect, board designer, package designer and ASIC engineer.

SerDes Design and Modeling over 25+ Gb/s Serial Link
Cathy Liu, Adam Healey, Pervez Aziz, LSI Corporation     

Serial Link Analysis using IBIS AMI Models
Fangyi Rao, Amolak Bade
sha, Sanjeev Gupta, Agilent Technologies       

Studying the Impact of Return Current Path on the EM Simulation of High-Speed Package Designs
Antonio Ciccomancini Scogna, Darryl Kostka, CST of America

Stripline Surface Roughness Correction Factor Extraction
Femi Akinwale, Srinidhi Raghavan Narasimhan, A. Ege Engin, San Diego State University            

An Innovative Printed Circuit Board Power Delivery Scheme
Zhenggang Cheng, Peter Gunadi, Amit Agrawal, Cisco Systems Inc.

PAM4 System Simulation Requirement for 25 Gbps Designs
Sanjeev Gupta, DingQing Lu, Agilent Technologies

TA3
Advanced Materials

Chairs: Wenning Liu, Pacific Northwest National Laboratory; Mitch Ferril, IBM; Yoon-Chul Sohn, Samsung Advanced Institute of Technology

In this session, novel materials incorporating various packaging devices & systems will be introduced. Electrical, mechanical, and thermal characteristics of the materials, in addition to reliability issues, will be discussed.

Influence of Film Thicknesses on the Electrical Properties of RuO2-Thick Film Resistors on Aluminum Nitride Ceramics (AlN)
Richard Schmidt, Markus Eberstein, Christel Kretzschmar, Fraunhofer IKTS                                  

Comprehensive Quantification of Moisture Sorption Characteristics in Polymer Material of Thin Film Form
Heejin Park, Ji-hyuk Lim, Suk-jin Ham, Bong-tae Han, Samsung Electro-Mechanics Co., LTD.

Transfer Molding Technology for Smart Power Electronics Modules - Materials and Processes
Karl-Friedrich Becker, T. Braun, M. Koch, T. Thomas, T. Schreier-Alt, V. Bader, J. Bauer, R. Aschenbrenner, M. Schneider-Ramelow, K.-D. Lang, Fraunhofer IZM                             

Modifiable Silicones for Harsh Environments
Michelle Velderrain, Matthew Lindberg, NuSil Technology 

How Silver Powder Metallurgy Affects the Physical Properties of Low Temperature Firing Silver Conductor
Samson Shahbazi, Mark Challingsworth, Heraeus Materials Technology LLC                                 

DNA to Safeguard Electrical Components & Protect Against Counterfeiting & Diversion
Janice Meraglia, Applied DNA Sciences

Superhydrophobic Coatings on Microelectronics
Andrew Jones, Vinod Sikka, Ross Nanotechnology, LLC

TA4
LED Packaging

Chairs: John Mazurowski, Penn State Electro-Optics Center; Sara Paisner, PN&S Consulting, LLC

New lighting devices are changing the industry, as government mandates are forcing obsolescence of inefficient technologies. High brightness Light Emitting Diodes (LEDs) are overtaking all other device types for illumination applications. Packaging of LEDs has become critical in optimizing the quality of light emission, in controlling thermal and electrical dissipation, and ultimately in improving stability and lifetime.

High Yield Process Improvements for High-Reliability HB-LED Automated Assembly
Donald Jay Beck, Palomar Technologies

Enhancing Reliability of LEDs and other Display Devices
Rakesh Kumar, Specialty Coating Systems, Inc.

Substrate Transfer for GaN-LED on Si (111) 4 Inch
Nga P. Pham, Maarten Rosmeulen, Cindy Demeulemeester, Vasyl Motsnyi, Deniz S. Tezcan, Haris Osman, IMEC

Effects of Phosphor Materials and Packaging Structures on Typical White LED Emitters
Yun Shuai, Nguyen T. Tran, Yongzhi He, Frank G. Shi, University of California, Irvine                    

Phosphor Temperature of White Light-Emitting Diodes
Bohan Yan, Nguyen T. Tran, Jiun-Pyng You, Frank G. Shi, University of California, Irvine

Evaluation of AuSn Eutectic Die-Attach Materials Designed for High Brightness LED Packaging
Amanda Hartnett, Seth J. Homer, Indium Corporation; Don Beck, Palomar Technologies

TA5
European Perspectives on Packaging & System-Integration I

Chairs: Ivan Ndip, Fraunhofer IZM; André Rouzaud, LETI

In this session, novel 3D integration concepts, heterogeneous integration technologies, biocompatible packaging processes as well as design techniques for cost-effective transmitter modules and printed antennas will be presented.

Heterogeneous Integration - Packaging on and in Organic Substrates
Karl-Friedrich Becker, Tanja Braun, Jörg Bauer, Lars Böttcher, Andreas Ostmann, Rolf Aschenbrenner, Fraunhofer IZM     

Design and Characterization of a Biocompatible Packaging Concept for Implantable Electronic Devices
Maaike Op de Beeck, Karen Qian, Paolo Fiorini, Josine Loo, Karl Malachowski, Chris Van Hoof, IMEC     

Screen Printed RFID Antennas on Low Cost Flexible Substrates
Kamil Janeczek, Małgorzata Jakubowska, Grażyna Kozioł, Anna Młożniak, Tomasz Serzysko, Tele & Radio Research Institute

The Road Towards Fully Hybrid CMOS Imager Sensors
Joeri De Vos, A. Jourdain, W. Zhang, K. De Munck, P. De Moor, A. La Manna, IMEC                   

Packaging and Integration Concept for High- Performance and Cost-effective IQM-based Transmitter Module for 160 Gb/s Applications
Giovanni Delrosso, B. Curran , R. Erxleben, R. Jordan, COGO OPTRONICS GmbH; H. Oppermann, I. Ndip, Fraunhofer IZM     

The Léti Two-Step Approach in the Domain of 3D Integration
André Rouzaud, Nicolas Sillon, Mark Scannell, David Henry, Léti-CEA

 


Tuesday, October 11, 2011 | Afternoon Sessions: 1:55 PM - 5:40 PM

3D Packaging Track
Modeling, Design and Reliability Track
Next Generation
Materials Track
Assembly and
Packaging Track
Advanced
Technologies Track
Focus Track: Adv. Packaging & System-Integration

TP1
3D - TSV Interposers

Chairs: Changhan "Hobie" Yun, Qualcomm, Inc.; Raghu Chaware, Xilinx, Inc.

This session focuses on 3D silicon interposers with TSV, novel TSV processing including thin wafer handling, coatings and copper filling, along with alternate interposers such as glass.

Quality and Reliability of 3D TSV Interposer and Fine Pitch Solder Micro-Bumps for 28nm Technology
Bahareh Banijamali, Suresh Ramalingam, Doug Hamilton, Myongseob Kim, Xilinx, Inc.                 

Embedded Capacitors on Silicon Interposers Enable Higher Frequency Applications
Sergey Savastiouk, Jim Hewlett, Phil Marcoux, ALLVIA, Inc.                    

Cost-Effective Precision 3D Glass Microfabrication for Electronic Packaging Applications
Jeb H. Flemming, Kevin Dunn, James Gouker, Carrie Schmidt, Colin Buckley, Life MicroFab        

Thin Wafer Handling Technologies for 300mm Wafer in 3D IC Integration
H. H. Chang, C. H. Chien, H. C. Fu, C. W. Chiang, W. L. Tsai, J. H. Lau, ITRI                                

Electrical Coupling Test Structures for Blind Copper Filled TSVs in a 300mm Wafer
Z. H. Lin, C. S. Lin, P. F. Chiu, S. S. Sheu, J. H. Lau, ITRI

Extreme Temporary Coatings and Adhesives for High- Thermal, Low-Pressure, and Low-Stress 3D-Processing
John Moore, Jared Pettit, Daetec, LLC

TP2
Design for Reliability

Chairs: Martin Goetz, Northrop Grumman; Joan Delalic, Temple University

In today's electronic package development cycle, activities are managed by multiple participants in the supply chain which might have different quality and reliability impacts to the end product. As a result, the reliability risk is much higher for companies that do not have insight into and/or control over the products received. Design-for-Reliability (DFR) approaches will come into play to manage the risk. In this session, DFR approaches for electronic products will be discussed from various perspectives.

Applicability of Existing Reliability Models: Focus on Finite Element Modeling of Various BGA Package Designs and Materials
Ali Fallah-Adl, Amaneh Tasooji, Nachiket Raravikar, Richard Harries, Sandeep Sane, Ravi Mahajan, Arizona State University

Case Study: Radial Cracks in a Rigid-Flex Assembly
Christopher Matsuoka, Crane Electronics Inc.

High Resolution Analysis of Resistance Behaviour in eWLB Metal Contacts
Sandy Klengel (Bennemann), L. Berthold, M. Krause, Fraunhofer Institute for Mechanics of Materials IWM; T. Meyer, J. Förster, K. Pressel, Infineon Technologies AG

Study of Screen Printer Parameters and Reflow Profiles for Pin-in-Paste Soldering Process
Ricardo Barbosa de Lima, Valtemar Fernandes Cardoso, Ana Neilde Rodrigues da Silvada Silva, University of Sao Paulo, Laboratory of Integrated System, LSI - Polytechnic School

Bond Over Active Circuitry Design for Reliability
Stevan G. Hunter, B. Rasmussen, T. Ruud, J. Martinez, K. Wilkins, J. Schofield, C. Salas, S. Sheffield, ON Semiconductor

Applications of Solder Fortification with Preforms
Ronald C. Lasky, Carol Gowans, Indium Corporation

Analysis and Control of Interface Reactions in Microelectronic Systems
J. H. Perepezko, S. D. Imhoff, R. Sakidja, University of Wisconsin-Madison

TP3
High Performance Interconnects and Boards

Chairs: Joe Kuczynski, IBM; Anwar Mohammed, Huawei Technologies

Increased wiring density, performance, reliability issues, and migration to lead free processes impart numerous challenges to the design and fabrication of high performance interconnects and PCBs. Issues related to reliability and performance, from the woven glass cloth to embedded components, drive board design and assembly considerations.

Design and Process Implementation for Embedding Components
Vern Solberg, Solberg Technical Consulting-Madison

An Investigation of Passivation Layer and Via Formation Process for Fine Pitch Substrate
Jin-Gul Hyun, Hyungjin Jeon, Samsung Electro-Mechanics Co., LTD.       

ToF-SIMS Analysis of Fibreglass Cloths for PCB Manufacturing
Michael Haag, Johannes Windeln, Michael Wahl, Dylan Boday, Joe Kuczynski, IBM Corporation   

High Performance Multi-Layer Board Considering Compatibility with Fine Pitch Package
Ki-Jae Song, Samsung Electronics

Making Sense of Laminate Dielectric Properties
Rich Pangier, Michael Gay, Isola                                     

Fabrication and Thermal Properties of Silicon Interposer BGA Package with Through Silicon Vias
Hao Zhang, Qian Wang, Jian Cai, Tao Wang, Li Li, Shuidi Wang, Tsinghua University                   

Very High Lead Count SMT Backplane Connector Rework Process: Recognizing the Challenges
Mitchell G. Ferrill, Jim Bielick, Eddie Kobeda, Theron Lewis, IBM

TP4
Pb-Free Solder Materials and RoHS, Processes and Reliability

Chairs: Ronald C. Lasky, Indium Corporation; Seth J. Homer, Indium Corporation

The effort to improve the performance and reliability of Pb Free/ ROHS compliant material performance continues. This session will cover application specific challenges as well as process methodologies that help improve performance and reliability for ROHS compliant materials.

High Melting Temperature Lead Free Solder for Die Attach Application
Jianxing Li, Daniel Lau, Kwok Kwong, Pingliang Tu, Brian Knight, Andy Delano, Honeywell Electronic Materials    

Mechanical Robustness of Solder Connections to Thick Film Gold
Thomas F. Marinis, Joseph W. Soucy, Draper Laboratory

Temperature and Pad Surface Finish Effects of Sn-1Ag-0.5Cu Solder Joint Strength under High Strain Rate Test Condition
Chin-Li Kao, Yi-Shao Lai, Chang-Lin Yeh, Advanced Semiconductor Engineering (ASE), Inc.         

Suppression of Kirkendall Voiding in Sn-3.5Ag/Cu Solder Joints by Pre-Annealing Process
Sunghwan Kim, Jin Yu, KAIST                                         

Manufacturability & Reliability Challenges with Leadless Near Chip Scale Packages (LNCSP) in Pb-Free Processes
Cheryl Tulkoff, Craig Hillman, DfR Solutions LLC             

Interference of Sb(III) in the Determination of Hexavalent Chromium in Thermoplastic Matrices

Sophia Lau, Joe Kuczynski, IBM

TP5
Emerging Technologies

Chairs: Luu Nguyen, National Semiconductor Corp.; Susan Bagen, Endicott Interconnect Technologies, Inc.

This session will introduce emerging technologies in thermal management, processes, materials and design for packaging of electronic devices.

Fabrication of an Electrostatically Actuated Impingement Cooling Device
Bivragh Majeed, H. Oprins, B. Vandevelde, D. S. Tezcan, P. Fiorini, IMEC                                   

Thermal Mechanical Characterization of High Power GaN Packages
Don Willis, Daniel Jin, Gary Gu, Robert Dry, RFMD

Remateable Conductive Ball-in-Pit Interconnects for Chip Powering and Alignment in Proximity Communication Enabled Multi-Chip Packages
Hiren D. Thacker, Ivan Shubin, Ying Luo, Kannan Raj, James G. Mitchell, Ashok V. Krishnamoorthy, John E. Cunningham, Oracle Labs        

Piezoelectric Nanogenerators for Mechanical Energy Harvesting
Xudong Wang, University of Wisconsin – Madison

Development of Laser Direct Ablation Process on Solder Resist in Printed Circuit Boards
Changbo Lee, Daejo Hong, Suil Kim, Cheolho Choi, Changsup Ryu, Samsung Electro-Mechanics

Embedded Actives and Its Industry Effects

Ray Fillion, Fillion Consulting

TP6
European Perspectives on Packaging & System-Integration II

Chairs: Ivan Ndip, Fraunhofer IZM; André Rouzaud, LETI

The focus of this session is on thermal and thermo-mechanical challenges and recommendations for packaging of high power microelectronics, on measurement and simulation methods for stress assessment, thermal performance analysis of LED modules as well as on reliability issues in packaging for harsh environments.

11imaps063: Technologies and Trends to Improve Power Electronic Reliability
Martin Schneider-Ramelow, M. Hutter, H. Oppermann, J.-M. Göhre, S. Schmitz, K.-D. Lang, Fraunhofer Institute for Reliability and Microintegration IZM

11imaps156: Topography and Deformation Measurement as a New Tool for Thermal Stress Assessment on Electronics Components
Michael Hertl, Insidix

Assessments and Characterizations of Stress Induced By Via-First TSV Technology
Gabriel Parès, Nicolas Sillon, CEA-LETI                           

Overview on Thermal and Mechanical Challenges of High Power RF Electronic Packaging
Cadmus Yuan, René Kretging, TNO; An Xiao, NXP Semiconductors; G.Q. Zhang, Delft University of Technology

Influence of Different Solder Materials on the Location of the Most Damaged PBGA Solder Balls and on the Life Time Reduction Due to Assembling of a Mounted Printed Circuit Board in an Electronic Control Unit
Natalja Schafet, Bruno Schrempp, Ulrich Becker, Manfred Spraul, Herbert Güttler, Robert Bosch GmbH

High Temperature Au Based Solder Reliability in Electronic Packages for Harsh Environments
M.F. Sousa, S. Riches, C. Johnston, P. S. Grant, Oxford University

 


Wednesday, October 12, 2011 | Morning Sessions: 8:00 AM - 11:40 AM

3D Packaging Track
Modeling, Design and Reliability Track
Next Generation
Materials Track
Assembly and
Packaging Track
Advanced
Technologies Track
Focus Track: Adv. Packaging & System-Integration

WA1
3D Packaging and Applications

Chairs: Ray Fillion, Fillion Consulting; Aicha Elshabini, University of Idaho

This session focuses on the latest developments in 3D SiP and PoP packaging and the materials and processes used in their fabrication.

Feasibility Study of a 3D IC Integration System-in- Packaging (SiP)
John H. Lau, M. Dai, Y. Chai, W. Li, S. Wu, ITRI               

Stacked-Die Multichip Package for Memory
Wei Koh, Powertech Technology Inc. (PTI)

Epoxy Flux - A Low Cost High Reliability Approach for PoP Assembly
Ning-Cheng Lee, Indium Corporation

3D-Stacking of UTCPs as a Module Miniaturisation
Swarnakamal Priyabadini, A. Gielen, K. Dhaenens, W. Christiaens, S. Van Put, G. Kunkel, A. E. Petersen, J. Vanfleteren, Centre for Microsystems Technology, Affiliated with IMEC vzw

Z-Axis Interconnections for Next Generation Packaging
Rabindra Das, Frank D. Egitto, John M. Lauffer, Tim Antesberger, Voya R. Markovich, Endicott Interconnect Technologies, Inc.

Fully Additive Chip Packaging: Science or Fiction?
Gerrit Oosterhuis, Ben van der Zon, TNO

MEMS Packaging with 3D-MID Technology
Nouhad Bachnak, Cicor

WA2
Materials, Processes and Reliability

Chairs: Jeffrey Gotro, InnoCentrix, LLC; James Weiler, Northrop Grumman

In this session, new solder joint adhesives and processes, reliability and fatigue tests as well as new surface finish and printing techniques will be presented.

IC Bond Pad Structural Study by Ripple Effect
Jose Martinez, Kyle Wilkins, Jason Schofield, Cesar Salas, Steven Sheffield, Brigham Young University – Idaho; Stevan Hunter, ON Semiconductor / Idaho State University

Developments in Stencil Printing Technology for 0.3mm Pitch CSP Assembly
Mark Whitmore, Clive Ashmore, DEK Printing Machines Ltd.                    

A First Room Temperature Stable and Jetable Solder Joint Encapsulant Adhesive
Mary Liu, Wusheng Yin, YINCAE Advanced Materials, LLC

A New Surface Finish for the Electronics Industry
John Ganjei, Ernie Long, Lenora Toscano, MacDermid Inc.                      

Acceleration Factors for Reliability Testing of Molded Case Tantalum Capacitors
Alexander Teverovsky, Dell Perot Systems

NanoBond® Assembly - A Rapid, Room Temperature Soldering Process
Jacques Matteau, Indium Corporation of America

Isothermal Fatigue Tests of SnPb, SnPbAg and SnBi Solder Joints
Eliane M. Grigoletto, Itamar Ferreira, Marcio T. Biasoli, UNISAL College Center of Sao Paulo

WA3
Ceramic and LTCC Packaging I

Chairs: Daniel Krueger, Honeywell, FM&T; John Menaugh, DuPont

The emphasis of this session highlights the increased interest and usage of ceramic and low temperature cofired ceramic (LTCC) packaging. It includes a diverse set of topics including new materials; bio, RF, and microwave applications; processing techniques; and technology comparisons.

Three-Dimensional Surface in LTCC for a MM-Wave Antenna
Peter Uhlig, Sybille Holzwarth, Bahram Sanadgol, Alexandra Serwa, IMST GmbH                         

Materials Interaction in Cofired Platinum /Alumina High Density Feedthrough for Implantable Neurostimulator Applications
Al Karbasi, W. Kinzy Jones, Florida International University        

Localized Temperature Stability in LTCC
Steve Dai, Sandia National Laboratories

Introducing DuPont™ GreenTape™ 9K5 Low Temperature Co-Fired Ceramic (LTCC) Tape System as a Low Dielectric Constant Stand Alone Microwave Substrate; and as a Composite Structure along with the GreenTape™ 9K7 LTCC System
Deepukumar Nair, K. M. Nair, Mark F. McCombs, James Parisi, K. E. Souders, Stephen C. Beers, DuPont Microcircuit Materials

Towards Highly Conductive Silver Pastes for LTCC Power Electronics
Markus Eberstein, Christel Kretzschmar, Thomas Seuthe, Steffen Ziesche, Uwe Partsch, Fraunhofer IKTS

Robustness and Versatility of Thin Films on Low Temperature Cofired Ceramic (LTCC)
J. Ambrose Wolf, Ken Peterson, Honeywell FM&T

WA4
Wire Bonding and Stud Bumping

Chairs: Daniel Evans, Palomar Technologies, Inc.; Lee Levine, Process Solutions Consulting, Inc.

Wire bonding continues as the dominant method of chip interconnection. This session starts with aging and testing of copper wire bonds then explores aluminum wire bonding. Fundamental discussions of ultrasonic frequencies and ball versus wedge bonding are covered with some innovative variations that enable high reliability solutions to today's packaging.

Ageing Characteristics of Cu Wire Bonds on Palladium Surface Finishes
Mustafa Oezkoek, Gustavo Ramos, Arnd Kilian, Atotech Deutschland GmbH                               

High Current Testing of Gold and Copper Wirebonds
Luu Nguyen, National Semiconductor Corporation

Aluminum as an Alternative to Copper Wirebonding
Luu Nguyen, K. Pham, A. Prabhu, A. Poddar, National Semiconductor Corporation                      

Which Frequency is Best for Wirebonding?
Josef Sedlmair, Farhad Farassat, Franz Schlicht, F&K Delvotec Bondtechnik                               

Why Wedge Bond?
Lee Levine, Process Solutions Consulting; Joe Bubel, Hesse & Knipps Inc.

Influence of Different Packaging and Footprint Technique for Microwave Absorptive Bessel Filter’s Performance
Akhlaqur Rahman, Michael Howieson, Thin Film Technology Corporation  

Comparison of Gold and Copper Wire Bonding on Aluminum and Nickel-Palladium-Gold Bond Pads for Automotive Application
Tu Anh Tran, Harold Downey, Varughese Mathew, Freescale Semiconductor Inc.

WA5
MEMS Packaging

Chairs: Yoonchul Sohn, Samsung Advanced Institute of Technology; Art Prejs, Phononic Devices, Inc.

In this session, various types of MEMS & sensor devices will be introduced. Materials, fabrication processes, evaluations, and reliabilities for the devices will also be discussed.

Packaging Technology of Multi Deflection Arrays for Multi-Shaped Beam Lithography
Thomas Burkhardt, M. Mohaupt, M. Hornaff, B. Zaage, E. Beckert, H.-J. Döring, K. Reimer, R. Eberhardt, A. Tünnermann, Fraunhofer Institute for Applied Optics and Precision Engineering

High Thermal-Transient Packaging for a SiC-Based Solid State Circuit Breaker
Theodore Baltis, James M. Pitarresi, Donald R. Hazelmyer, Douglas C. Hopkins, Binghamton University  

Evaluation of Package-Induced Mechanical Stresses using a Stress-Sensitive Testchip
Horst Theuss, Benjamin Alles, Klaus Elian, Markus Fink, Manfred Fries, Clemens Jaroschek, Franz-Peter Kalz, Andre Schubert, Mathias Vaupel, Helmut Hummel, Oliver Steffens, Infineon Technologies

Reliable Vacuum Sealing of Silicon MEMS with Measured Q-Factors of 1 Million
Brenton R. Simon, A. A. Trusov, University of California, Irvine; A. M. Shkel, DARPA; P. Zappella, P. W. Barnes, SST International

Vacuum Packaging for High-Performance Low Cost MEMS Gyro used in 6 Degrees of Freedom Inertial Navigation System
D. DeRoo, K. Shcheglov, M. Inbar, D. Smukowski, Sensors in Motion, Inc.; K. Shcheglov, M. Inbar, D. Smukowski; WAP Zappella, P. W. Barnes, SST International

MEMS Integrated Packaging for RF Circuit Testing and Self Calibration
Sukeshwar Kannan, Bruce Kim, University of Alabama; Seok-Ho Noh, Andong National University

WA6
Advanced Packaging in China (Chinese-to-English Translated Session)

Chairs: Qinghua Bill Chen, Yangtze Delta Region Institute of Tsinghua University; Yishao Lai, ASE

This special session will address recent developments in advanced packaging R&D in the Great China area.

Advanced Semiconductor Packaging Solutions: From QFN to BGA, 3D WLP
Hao Tang, Fujitsu Microelectronics

Universities’ Researches and Education in Mainland China
Jian Cai, Songliang Jia, Tsinghua University                    

Challenges in RFID Tag Bonding and Packaging
Shufang Li, Beijing University of Posts and Telecommunications

Through Silicon Vias and Holes Metallization using CoWP and Cu Nanoparticles as Barrier and Seed Layers
Wei-Ping Dow, Shao-Ping Shen, Chun-Wei Lu, Yiu-Hsiang Chang, Motonobu Kubo, Tohru Kamitamari, Eric Cheng, Jing-Yuan Lin, Fu-Chiang Hsu, National Chung Hsing University

Wafer Bumping and Characterization of Fine-Pitch Lead-Free Solder Microbumps on 12” (300mm) Wafers
John Lau, Ching-Kuan Lee, Charles Tzeng, Li Li, Cheng-Ta Ko, Chau-Jie Zhan, Ming-Ji Dai, Jie Xue, Mark Brillhart, Industrial Technology Research Institute (ITRI); Electronics & Optoelectronics Research Laboratory

 


Wednesday, October 12, 2011 | Afternoon Sessions: 1:35 PM - 5:25 PM
Information for Session WP6 - Interactive Poster Session - can be found here

3D Packaging Track
Modeling, Design and Reliability Track
Next Generation
Materials Track
Assembly and
Packaging Track
Focus Track: Adv. Packaging & System-Integration
Interactive Track

WP1
3D Packaging, Thermal/Mechanical Simulation and Modeling

Chairs: Kevin Moores, Department of Defense; Venky Sundaram, Georgia Institute of Technology

Simulation and experimental validation efforts are presented for use in modeling the advanced designs and processes inherent in leading edge packaging technology.

Studies of Mesoscale Models Parameterized by Molecular Models for Interface Failure in Epoxy Molding Compounds
Nancy Iwamoto, Honeywell International, Inc.

Experimental and Numerical Characterization of Panel Warpage for Low Cost Package Development on 1- Block Panel
Yongbo Yang, Edith Poh, Chua Shervin, S. Anom, S. Nathapong, W.L. Yuan, C. Surasit, United Test and Assembly Center     

Inclusion of Trace and Plane Joule Power Dissipation in a Coupled Electromagnetic and Thermal Analysis of a Printed Circuit Board in an Enclosure
Steve Pytel, Markus Kopp, Robert Myong, ANSYS, Inc.

Warpage and Stresses in Molded Package
Yuan Yuan, Shufeng Zhao, Freescale Semiconductor Inc.

Advanced Thermal Study of Very High Power TSV Interposer and Interconnects for the 28nm Technology FPGA
Bahareh Banijamali, Xilinx, Inc.

Mix of Analog and Digital Circuitry Analysis in a Noisy Environment

Hugues Tournier, Klaus Hu, Shuhui Deng, Wenqian Han, Ciena Inc.          

Molding Flow Modeling and Experimental Study on Void Control for Flip Chip Package Panel Molding with Moldable Underfill Technology
Jonathan Tamil, Ore Siew Hoon, Gatbonton Librado Amurao, Anom Sudibya, Gan Kian Yeow, Yang Yong Bo, Edith Candy, Poh Siew Wee, Yuan Wei Liang, Nathapong Suthiwongsunthorn, Surasit Chungpaiboonpatana, United Test and Assembly Center Ltd.

WP2
Package Reliability Testing

Chairs: Arv Sinha, IBM; Adam Schubring, Kyocera America, Inc.

This session focuses on the simulated and experimental mechanical reliability characterization techniques and testing results for electronic packages, including solder joints, die attaches and molding compounds.

Solder Strength Characterization using Hot Bump Pull Testing
Arv Sinha, Kevin O'Connell, IBM Corporation
                          
A Study of Solder Joint Failure Criteria
Jianbiao Pan, Julie Silk, California Polytechnic State University

The Reliability Impact of Reballing COTS Pb-Free BGAs to Sn/Pb for Military Applications
Greg Caswell, Joelle Arnold, DfR Solutions    

The Mechanism of the Die Crack in Exposed Pad Quad Flat Package (ePad QFP) with Large Die due to Die-Attach Adhesive with High Modulus
Dong-Nam Kim, Ho-Cheol Jang, Young-Chul Jo, Nam-Yong Kim, Seung-Geun Kang, Byung-Ju Lee, DalSoo Kim, TLi Inc.; Tea-Seob Yun, SEMITEQ

BGA Substrate Material Property Measurement vs. Predicted Values
Burton Carpenter, Betty Yeung, Huai Huang, Freescale Semiconductor, Inc.                 

Investigating Stress in Hybrid Electronics Packages Using White Light Surface Profilometry
Kelsey Folgner, Peter Fuqua, Ching-Yao Tang, Michael O'Brien, The Aerospace Corporation

Mold Compound Adhesion Reliability with SiN and SiON Passivation Surfaces
Varughese Mathew, Sheila Chopin, Trent Uehling, Ruzaini Ibrahim, Freescale Semiconductor, Inc.

WP3
Ceramic and LTCC Packaging II

Chairs: Kenneth Peterson, Sandia National Laboratories, Larry Zawicki, Honeywell FMT

This session builds on the first by highlighting properties and processes for LTCC and characterization of devices and structures that can be made with this understanding. It includes feature definition; strength, reliability, and electrical properties for LTCC, and its application to RF circuits, capacitors, and devices involving mechanical integrity of ceramic bodies.

Surface Properties of Laser-Etched LTCC Ceramic
Krzysztof Zaraska, Janina Gaudyn, Adam Bieńkowski, Andrzej Czerwiński, Mariusz Płuska, Institute of Electron Technology

Bulk and In-Circuit Dielectric Characterization of LTCC Tape Systems Through Millimeter Wave Frequency Range
Deepukumar Nair, James Parisi, Glenn Oliver, Elizabeth Hughes, Michael Smith, DuPont Microcircuit Materials

Sputter Deposition of Thin Film MIM Capacitors on LTCC Substrates for RF Bypass and Filtering Applications
J. Ambrose Wolf, D. Krueger, Honeywell FM&T; J. Murray, W. Huebner, M. O'Keefe, K. Wilder, Missouri S&T; R. Eatinger, W. Kuhn, Kansas State University                                                               

Strength and Reliability Estimation of LTCC Material with and without Metallic Features
Rajan Tandon, Sandia National Laboratories

Sensitivity Analysis-Based Design of Low Temperature Cofired Ceramic Multi Chip Modules in High Reliability Applications

Nathan Young, Kenneth Peterson, Kevin Ewsuk, Sandia National Laboratories                             

Electromagnetic Isolation Solutions in Low Temperature Cofired Ceramic (LTCC)
Laurie Euler, Daniel Krueger, Honeywell Federal Manufacturing and Technologies; Ken Peterson, Sandia National Laboratories

A Novel Design of a Planar SOFC with the Anode Supported on the Base Ceramic Structure
Barbara Dziurdzia, AGH University of Science and Technology, Department of Electronics

WP4
Substrate Materials and Technologies for the Semiconductor and Solar Industries

Chairs: Seth J. Homer, Indium Corporation; Dave Saums, DS&A LLC

Increasing performance and reliability requirements continue to place greater demand on improvements at every level in semiconductor packaging, and processes related to the solar industry. Substrate materials are of critical importance to the package structure, heat transfer, CTE mismatch, and electrical performance. This session will highlight new developments that include mechanical, thermal, dielectric, and reliability testing.

Properties and Reliability of Silicon Nitride Substrates with AMB Copper Conductor
Ina Sichert, Dieter Brunner, Gaby Boehm, Andreas Poenicke, Jochen Schilm, ANCeram GmbH     

The Adhesion Property Improvement by Forming Specific Patterns on a Surface of a Photosensitive Insulating Layer
Yoon-Su Kim, Chang-Bae Lee, Jin-Gu Kim, Young Do Kweon, Samsung Electro-Mechanics, Co., LTD.    

Use of Polyalkylene Carbonate Binders for Improved Performance in Multilayer Ceramic Capacitors
Peter Ferraro, Sugianto HanggodoIan Burn, Empower Materials Inc.

Thermal Performance Design Considerations in a Solar Panel “Smart” Junction Box
Luu Nguyen, A. Poddar, Y. Xi, B. Mazotti, National Semiconductor Corporation; L. Shen, Nvidia

Materials Selection and Processing Techniques for Small Spacecraft Solar Cell Arrays
N. Meetra Torabi, Janet K. Lumpp, University of Kentucky

Electrical Behavior of a Double-Sided PV Solar Panel
Virgil C. Ganescu, Robert Shoaff, Harrisburg Area Community College; Adrian Pascu, University POLITEHNICA

WP5
Improvements in Advanced Packaging from Japan (Japanese-to-English Translated)

Chairs: Bill Ishii, Torrey Hills Technologies, LLC; Kishio Yokouchi Fujitsu Interconnect Technologies, LTD.

This Japanese translated session focuses on various materials and design developments in Japan for advanced packaging architectures.

Wafer Level Process Compatible Underfilling Pre- Applied Film Adhesive for Flip Chip and 3D Package
Toshihisa Nonaka, Noboru Asahi, Koichi Fujimaru, Yasuko Tachibana, Toray Industries, Inc.         

Electrical Performance of Advanced Surface Laminar Circuit in High-End FCBGA Applications
Makoto Shiroshita, Kenji Terada, Kimihiro Yamanaka, Kyocera SLC Technologies Company         

Build-Up Electrical Insulation Material with Low- Dielectric Loss Tangent, Low-CTE and Low-Surface Roughness
Isao Suzuki, Sekisui Chemical Co., Ltd.

High-Quality Multiple Global Layers on Chip- Redistributed Wafer for Wafer-Level System Integration using Pseudo-SOC
Atsuko Iida, Yutaka Onozuka, Hiroshi Yamada, Toshihiko Nagano, Kazuhiko Itaya, Toshiba Corporation   

Development of IMC Bonding with Wafer Level Underfill Process for 3D-IC
Yasumitsu Orii, Sayuri Kohara, Akihiro Horibe, Keiji Matsumoto, Kuniaki Sueoka, Kazushige Toriyama, Hirokazu Noma, Keishi Okamoto, IBM Research Tokyo; Katsuyuki Sakuma, IBM Systems &Technology Group, Microelectronics Division

Optoelectronic Substrate with High-Aspect-Ratio Optical Through-Hole for Chip-To-Chip Interconnects
Atsushi Suzuki, Yutaka Takagi, Toshikazu Horio, Toshifumi Kojima, Toshikatsu Takada, Satoshi Iio, Masahiko Okuyama, NGK Spark Plug Co., Ltd.

WP6
Interactive Forum
(Poster Session)

Chairs: Kevin Ouellette, BAE Systems; Aicha Elshabini, University of Idaho

One-on-One Interactive Forum. This is your chance for detailed interaction with authors whose work is too good to miss.

 

Information for Session WP6 - Interactive Poster Session - can be found here

 


Thursday, October 13, 2011 | Morning Sessions: 8:00 AM - 12:00 PM

Modeling, Design and Reliability Track
Next Generation Materials Track
Assembly and
Packaging Track
Advanced Technologies Track
Focus Track: Adv. Packaging & System-Integration

THA1
Microwave and RF Applications

Chairs: Scott Morris, Skyworks Solutions; Milind Shah, Qualcomm Inc.; Ron Barnett, National Instruments

This session integrates novel approaches to measurement, modeling, and materials of RF and microwave packaging. The discussions will vary from integrated components to power products.

Mobile Device Passive Integration from Wafer Process
Kai Liu, YongTaek Lee, HyunTai Kim, Gwang Kim, Robert Frye, Hlaing Ma Phoo Pwint, Billy Ahn, STATS ChipPAC Ltd.

RF Sensitivity of Multi Chip Package Development by using Embedded Resistor in Package Substrate
Woong-Sun Lee, Sang-Joon Lim, Heung-Jae Shin, Jong-Tae Lee, Jung-Kwon Park, Jae-Sung Oh, Kwang-Yoo Byun, Hynix Semiconductor Inc.; Advanced PKG Technology Team

Impact of PCB Manufacturing Process Variations on Trace Impedance
Abdelghani Renbi, Johan Carlson, Jerker Delsing, Lulea University of Technology; EISLAB, Department of Computer Science, Electrical and Space Engineering

GaN Based RF Modules - Demands and Needs for Packaging
Martin Oppermann, CASSIDIAN Electronics (EADS)

Zero-Power MEMS Sensor Actuated RFID System
Yang Zhang, Kerchia Chen, Sean Burke, Scott McLaughlin, G. P. Li, Mark Bachman, Dennis Rieger, Winston Ho, University of California - Irvine; Integrated Nanosystems Research Facility

Comparison Between Multilayer Ceramic and Organic Package Substrates Based Upon Signal and Power Integrity
Jerry Aguirre, Paul Garland, Kyocera America Inc.            

Impact of Process Tolerances on the Performance of Bond Wire Antennas at RF/Microwave Frequencies

Ivan Ndip, Abdurrahman Öz, Christian Tschoban, Stefan Schmitz, Martin Schneider-Ramelow, Stephan Guttowski, Herbert Reichl, Klaus-Dieter Lang, Fraunhofer IZM

THA2
Thermal Management

Chairs: Virgil C. Ganescu, Harrisburg Area Community College; Woong-Sun Lee, Hynix Semiconductor Inc.

Heat generated by electronic devices and circuitry must be dissipated to improve reliability and prevent premature failure. A wide variety of techniques for heat dissipation (at various levels and of different applications) and control, as well as novel compound materials are presented and discussed in this session. Extreme operating conditions and environments are also looked at.

Thermal Management of Focal Plane Assembly in the Hyperspectral Imager
B. J. Wang, NSPO

Rated Power Improvement of Termination Resistor by Employing Innovative Thermal Management Techniques
Akhlaqur Rahman, Fred Olinger, Michael Howieson, Thin Film Technology Corporation                 

Power Efficiency Improvement for Low Ohm Current Sense Resistor by Optimum Thermal Management
Akhlaqur Rahman, Fred Olinger, Michael Howieson, Thin Film Technology Corporation

Performance of a Ceramic-Based Flat Plate Heat Pipe for Electronics Cooling
Merrill A. Wilson, Charles Lewinsohn, Joseph Fellows, Hyrum Anderson, Ceramatec, Inc.

Optimization of a Flux-Less Metal Thermal Interface Material by Reflow in a Vacuum Furnace
Pierino Zappella, P. W. Barnes, SST International; Sean Too, AMD

Ceramic Microcombustor as a Heat Energy Meter
Zbigniew Magonski, AGH University of Science and Technology

Simultaneous Characterization of Theta-JC and Theta- JB using Through-Package 1-D Heat Flow
Jichul Kim, Jae Choon Kim, Mina Choi, Eunseok Cho, Heung-Kyu Kwon, HoGeon Song, Sayoon Kang, Samsung Electronics

THA3
Flip-Chip and Wafer Bumping: Processes and Reliability

Chairs: Ronald Jensen, Honeywell; Lyndon Larson, Dow Corning

The continuing trend toward higher interconnect density, smaller bump geometries, and new lead-free materials presents challenges and reliability concerns for wafer bumping and flip chip assembly processes. The first 3 papers in this session discuss new wafer bumping, surface analysis, and flux removal processes for flip chip assembly. The last 3 papers address the electromigration concerns of smaller bump geometries and lead free materials.

Wafer Level Solder Bumping and Flip Chip Assembly with Solder Balls Down to 30µm
Thomas Oppert, Pac Tech Packaging Technologies GmbH; Rainer Dohle, Micro Systems Engineering GmbH; Florian Schuessler, Joerg Frenke, Stefan Haerter, University of Erlangen-Nuremberg

Surface Energy and Wettability Study of Flip Chip Packaging Materials
Jinlin Wang, Intel Corporation

IC Packaging Trends Causing Concerns in Complete Flux Removal
Rich Brooks, Kyzen Corporation

Evaluation of Electromigration in Flip-Chip Solder Joints
Hyun-Kyu Lee, Y. C. Chu, M. H. Chun, S. H. Jeon, J. U. Kwak, S. J. Lee, S. M. Bae, DUKSAN HI-METAL Co., LTD.

Accelerated Life Tests of Flip-Chips with Solder Bumps Down to 30 µm Diameter
Rainer Dohle, S. Härter, J. Goßler, J. Franke, Micro Systems Engineering GmbH       

Electro-Migration Behavior in Micro-Joints of Sn-57Bi Solder and Cu Post Bumps
Kei Murayama, Mitsutoshi Higashi, Shinko Electric Industries Co., LTD.; Taiji Sakai, Nobuaki Imaizumi, Fujitsu Laboratories LTD.

THA4
Printed Electronics and Additive Manufacturing

Chairs: John Bolger, Department of Defense; Andy Tseng, ASE, Inc.

The Printed Electronics and Additive Manufacturing Session will cover a variety of topics of interest, from processing schemes for complex structures to characterization of novel materials.

Next Generation Micro-Packaging
Xudong Chen, nScrypt, Inc.

Printable Materials and Devices for Next Generation Packaging
Rabindra N. Das, How T. Lin, Jianzhuang Huang, John M. Lauffer, Mark D. Poliks, Voya R. Markovich, Endicott Interconnect Technologies      

CubeSat Fabrication Through Additive Manufacturing and Micro-Dispensing
Rodolfo Salas, Richard Olivas, Cassie Gutierrez, Dan Muse, Eric MacDonald, Ryan Wicker, The University of Texas at El Paso; Mike Newton, Ken Church, nScrypt, Inc.

Aerosol Jet® Printer as an Alternative to Wire Bond and TSV Technology for 3D Interconnect Applications
Ken Vartanian, Michael J. Renn, Stephen Barnes, Michael O’Reilly, Optomec                               

Printable Sub-200 C nanoCu Solder
Alfred A. Zinn, Lockheed Martin Space System Company

Conductive Performance and Cure Depth of Copper Conductive Screen Ink Based on Pulsed-Light Modulated Copper-Oxide Reduction Technology
Dave Pope, Stan Farnsworth, Ian Rawson, NovaCentrix

 

THA5
Optoelectronics and Photonics Packaging

Chair: John Mazurowski, Penn State Electro-Optics Center

HALF-SESSION: Light is a valuable candidate for transmission of signals because multiple signals can be superimposed within the same space. Optical alignment and its stability become more important for optimizing optical transmission loss and system efficiency.

High-Fidelity Optical Microphone Manufactured in Laminates
Jonas Tsai, Yang Zhang, Mark Bachman, G. P. Li, University of California - Irvine                         

Temporary Protective Packaging for Optical MEMS
Lieve Bogaerts, A. Phommahaxay, C. Gerets, P. Jaenen, R. Van Hoof, S. Severi, M. Van De Peer, J. De Coster, A. La Manna, P. Soussan, A. Witvrouw, IMEC                                      

Near-Zero Shift Attachment for Optoelectronic Components
Roy J. Bourcier, Corning Incorporated

THA6
Wafer-Level Integration & System Packaging

Chair: Greg Caswell, DfR Solutions

HALF-SESSION: This session addresses new wafer-level integration and system-in-package (SiP) technologies, the evolution of package-on-package (PoP) and applications of 3D X-ray microscopy for package development.

Wafer Level Integration of MMIC and Microwave IPD with Metal/BCB Multilayer Interconnection Based on Low Resistance Silicon
Jiajie Tang, Le Luo, Shanghai Institute of Microsystem and Information Technology, CAS

3D Packages and Assembly Methodologies
Bernd K. Appelt, Calvin Cheung, ASE Group

Applications of 3D X-Ray Microscopy for Advanced Package Development
Kevin Fahey, R. Estrada, Xradia; L. Mirkarimi, D. Buckminster, M. Huynh, Tessera Technologies

 

 

 

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Bag Insert:
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Golf Sponsors
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Golf Ball Markers:
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Golf Hole Sponsor:
Technic - Golf Hole Sponsor
Golf Hole Sponsor:
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