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IMAPS 2012 - San Diego
45th International Symposium on Microelectronics
Bringing Together The Entire Microelectronics Supply Chain!

September 9 - 13, 2012
San Diego Town & Country Convention Center
San Diego, California, USA

www.imaps2012.org

IMAPS 2012 - San Diego

Conference and Exhibition:
September 11-13, 2012
Professional Development Courses:
September 9 - 10, 2012

Professional Development Courses (PDCs)


All Sunday PDCs are half-day, running 1:00 pm - 5:00 pm
Monday PDCs run 9:00 am - 5:00 pm

Do you want to broaden and strengthen your skills and knowledge, optimize your manufacturing processes, and integrate the latest advances in materials and technologies to maintain your strength in today's competitive global market? The Technical Committee of IMAPS is pleased to present a comprehensive offering of Professional Development Courses that provide detailed information on topics of immediate interest to the Microelectronics and Packaging community.  So please be sure to choose from the 15 in-depth Professional Development Courses taught by recognized industry experts.  You will discover the following key ways that will benefit you.

  • Better understand the skills and knowledge necessary in today's industry.
  • Be exposed to the rapidly expanding developments in new materials and technologies.
  • Consult with renowned authorities about your current R&D or manufacturing problems and challenges.
  • Learn new ways to identify, think about, and address your problems and opportunities.
  • Great opportunities to interact with industry experts and other course attendees.
  • Certificate of Attendance and much more…

Your PDC Registration Fee Includes:

  • Lunch on the day of your course
  • Refreshment breaks
  • All course materials
  • PDC Reception on Sunday evening (for Attendees & Instructors only)
  • Certificate of Attendance

PDC Lunches and Reception sponsored by:
Heraeus Materials Technology - Premier Sponsor, Gold

PDC Cancellation policy:

IMAPS reserves the right to cancel a course if the number of attendees is not sufficient.  You can transfer to a different course or we will refund you the corresponding amount.

PDCs under SESSIONS
during IMAPS 2012 Registrations



Sunday, September 9, 2012
All Sunday PDCs are 1/2 Day Courses (4-hours): 1:00 pm - 5:00 pm

S1: Basics of Microelectronic Packaging
PDC Instructor: Casey Krawiec, Quik-Pak

Course Description: This course will provide the student with an overview of the history of microelectronics, core terminology and concepts, and the critical functions of microelectronic packaging. Students will learn the basic types of microelectronic packaging from a materials perspective. Regarding materials and packaging technology selection, students will gain an appreciation of the trade-offs between cost, performance, and reliability. The course will provide an overview on package assembly and test, and will conclude by reviewing the future/emerging packaging technologies.

Who Should Attend? The course is for entry-level engineers, technicians, and others involved in manufacturing, purchasing, processing, R&D, quality, sales, and marketing.

Casey Krawiec has been deeply involved with microelectronics and packaging for almost 20 years. He is currently the Global Sales and Marketing Manager at Quik-Pak in San Diego. Prior to that, he was Vice President of North American Sales at StratEdge Corporation, a packaging OEM and assembler. He had also worked for Kyocera America, including a stint as the Offshore (International) Sales Manager. He began his career as a design engineer for the Department of the Navy. He has an MBA from the University of Louisville and a BS in Mechanical Engineering from the University of Kentucky. He is an officer in the local chapters of both International Microelectronics And Packaging Society and the American Society of Mechanical Engineers.

S2: TSV and Other Key Enabling Technologies for 3D IC/Si Integration
PDC Instructor: John H. Lau, ITRI

Course Description: 3D integration consists of 3D IC packaging, 3D IC integration, and 3D Si integration, which will be discussed in this lecture. Emphases are placed on the key enabling technologies for 3D IC/Si integrations, such as TSV (through-silicon via) forming and filling, front and back-side metallization, RDL (redistribution layer), IPD (integrated passive devices), temporary wafer bonding, wafer thinning and handling, wafer de-bonding, thin chip/wafer strength measurement and improving, W2W bumpless bonding, lost-cost lead-free microbumping (<=15µm pitch) and assembly, low-temperature wafer bumping and C2C, C2W, and W2W bonding, and thermal management. Useful characterization and reliability data for 3D IC integration will also be provided. The application of 3D IC integration such as CMOS image sensor, MEMS, LED, memory + logic, logic + logic, memory + microprocessor, active and passive interposers will be presented. More than 15 companies' passive interposes (samples) used as substrates, carriers, and thermal management tools will be presented and discussed. Furthermore, the critical issues of TSV and 3D IC integration will be given and some potential solutions or research topics will be recommended. Finally, TSV manufacturing yield and hidden costs will be discussed and several roadmaps of 3D IC/Si integration will be provided. All the materials are based on the technical papers and books published within the past 3 years by the lecturer and others.

Who Should Attend? If you (students, engineers, and managers) are involved with any aspect of the electronics, LED, MEMS, and optoelectronic industry, you should attend this course. It is equally suited for R&D professionals and scientists. You will receive more than 300 pages of handouts from the Instructor's books, "Advanced MEMS Packaging" (McGraw-Hill, 2010), "Reliability of RoHS Compliant 2D & 3D IC Interconnects" (McGraw-Hill, 2011), and "Through-Silicon Technology for 3D Integration" (McGraw-Hill, 2012).

Dr. John Lau has been an ITRI Fellow of Industrial Technology Research Institute (ITRI in Taiwan) since January 2010. Prior to that, he was a visiting professor at HKUST for 1 year, the Director of MMC Laboratory with IME in Singapore for 2 years and a Senior Scientist/MTS at HPL/Agilent in California, US for more than 25 years. With more than 35 years of R&D and manufacturing experience, he has published more than 350 peer-reviewed papers, 30 issued and pending US patents, given 270 lectures/workshops/keynotes worldwide, published 16 textbooks on 3D MEMS packaging, 2D and 3D IC integrations, flip chip & WLP, high-density PCB, SMT, and lead-free materials, soldering, manufacturing and reliability. John earned his PhD degree from the University of Illinois, 3 MASc degrees in North America. John received many awards, e.g., the best IEEE/ECTC Proceedings paper (1989) award, best ASME Transactions paper (Journal of Electronic Packaging, 2000) award, best IEEE Transactions paper (in CPMT, 2010) award, ASME/EEP Outstanding Technical Achievements award, IEEE/CPMT Manufacturing award, Outstanding Contribution award, and Outstanding Sustained Technical Contribution award. SME Total Excellence in Electronics Manufacturing award, and IEEE Meritorious Achievement in Continuing Education award. He is an elected ASME Fellow and has been an IEEE Fellow since 1994.

S3: High-Performance Thermal Management Materials
PDC Instructor: Carl Zweben, Ph. D., Zweben Advanced Thermal Materials

CANCELLED BY INSTRUCTOR

S4: Mechanical Design and Reliability Analysis in Microelectronics Packaging
PDC Instructor: Dr. Amaneh Tasooji, Arizona State University

Course Description: The objective of this workshop is to provide an overview of mechanical design and discuss the reliability analysis and tools used in microelectronics packaging. Mechanical design requirements and analysis approaches are reviewed, and Traditional/Classical and Damage-Tolerant (Fracture-Mechanics and LEFM) approaches are discussed. Stress-strain response (including thermal loading due to CTE-mismatch), materials behavior and constitutive models, and failure mechanisms (brittle/ductile fracture, DBTT, creep, and fatigue) are reviewed. Closed form solutions and analytical approaches (FEM, Finite Element Methods) are presented. Mechanical metrologies such as Moire™ used in measuring package deformation (e.g., warpage) and validating analytical FEM results are reviewed. Reliability analysis and tools used in ensuring mechanical integrity are discussed. Methodology used in determining acceleration factor (AF) for predicting package performance/reliability under "use condition" is presented. Statistical methods and Life prediction methodologies used in mechanical analysis and component reliability assessment are discussed.

Who Should Attend? Engineers in R&D, QA, QC, manufacturing, process development, and advanced technicians. It is assumed that participants have some familiarity with microelectronics packaging and general device assembly technologies.

Dr. Amaneh Tasooji has more than 23 years of industrial and academic experience in engineering and manufacturing. She received her Ph. D. in Materials Science and Engineering from Stanford University in 1982 and has B. S. degree in Physics. Dr. Tasooji has extensive/diverse technical knowledge in materials and processing, component design, manufacturing, and quality/reliability in many industries such as microelectronics, aerospace, and nuclear. Dr. Tasooji was the recipient of many technical/engineering and leadership awards including ASTM Sam Tour Award for distinguished contribution to research, development, and evaluation of corrosion testing and modeling. Dr. Tasooji has developed and delivered many graduate and undergraduate engineering courses (e.g., "Introduction to Micro-electronic Packaging", "Overview of Materials Science and Engineering for Microelectronics Packaging", "Advanced Packaging Analysis and Design: Material Considerations", "Nuclear Materials", etc.) at Arizona State University (ASU). She has leveraged new technology and e-learning concepts in developing and offering conventional (face-to-face) and hybrid courses (on-campus and distance training) at ASU.

S5: High Temperature Electronics
PDC Instructor: Randall Kirschman, Consultant

Course Description: High-Temperature Electronics (HTE) is a valuable option for substantially improving overall system performance. Operating temperature may be thought of as an additional design parameter when justified by system performance requirements.

Applications of HTE include many areas of science and technology, including petroleum and geothermal wells, vehicles, aircraft, Solar System exploration, and electric power. Relocating electronic subsystems to high-temperature can improve overall system efficiency, decrease size and weight, simplify maintenance and improve reliability. At the same time there are many technical challenges, related to materials interactions, component behavior, circuit design and interfacing.

The focus of this course is semiconductor electronics at high temperatures: device behavior, applications, advantages and drawbacks, technical issues and present situation. Basic materials characteristics related to electronics at high temperatures, and passive electronic component behavior are included. The temperature range covered in this course extends from +125°C upward, as high as 1000°C. Depending on the temperature range, HTE semiconductor devices may be based on Si, SiGe, GaAs, SiC, GaN, C (diamond) and other materials.

Although future developments in electronics are difficult to predict, it is likely that high-temperature electronics will find increased use for enhanced performance in extreme environments.

Tenative Outline:
I. - Introduction and definitions, course description & objectives, temperature ranges, history and background.
II. - Applications: aircraft, oil and geothermal well measurements, space exploration and power, automotive. Reasons for high-temperature operation of electronics; benefits and drawbacks.
III. - Materials behavior - non-semiconductors: thermal conductivity, thermal expansion, heat capacity, thermal diffusivity, electrical conduction, glass transition temperature, strength, temperature capabilities, dielectric properties, magnetic properties.
IV. - General semiconductor materials behavior: carrier generation, mobility, electrical conductivity, freeze-out, trapping and hot-carrier effects, thermal conductivity, behavior and capabilities of Ge, Si, SiGe, GaAs, GaN, SiC, BN, C (diamond), etc.
V. - Semiconductor device temperature capabilities/limits.
VI. - Silicon device behavior: diodes, bipolar transistors, FETs (JFETs, MOSFETs, etc.), power devices (MOSFETs, IGBTs, thyristors, GTOs, MCTs, BMFETs, etc.), integrated circuits (bipolar, CMOS, SOI, power).
VII. - Devices based on medium-bandgap semiconductor materials: GaAs, AlGaAs, GaP, etc.
VIII. - Devices based on large-bandgap semiconductor materials: GaN, SiC, BN, C (diamond), etc.
IX. - Semiconductor device and integrated circuit metallizations for high temperatures.
X. - Passive components (resistors, capacitors, inductors), wire, connectors, switches, and batteries for high temperatures.
XI. - Assemblies for high temperatures: thin-film, thick-film, die-attach, wirebonding, soldering, packaging, interfacing, design principles, examples of assemblies.
XII. - Modeling & simulation.
XIII. - Reliability & Aging: how high temperature differs from room temperature, mechanical stress, failure rates, temperature cycling studies, adaptive circuitry.
XIV. - Radiation effects & management with examples.
XV. - Design Issues: choosing components, factors, temperature/temperature range, lifetime requirements, environment & additional stresses, mechanical, resources, custom vs commercial.
XVI. - Alternative technologies for high temperature electronics: future possibilities.
XVII. - References & Bibliography

Course Objectives: Provide an overview of situations where the technologies of electronics and high temperatures are brought together. Provide an overview of the applications for high temperature electronics. Survey the relationships between fundamental phenomena, materials behavior, and device and system characteristics and performance at high temperatures. Overview the behavior of materials and components used in electronics at high temperatures: metals, ceramics, plastics, passive components, semiconductor materials and devices, and electronic circuits and assemblies. Provide practical information on materials, devices, circuits and techniques for those involved in high-temperature electronics.

Dr. Randall Kirschman is an internationally recognized authority on extreme-temperature electronics. He has been consulting to industry, government and academe since 1980 in the areas of microelectronic materials and fabrication technology, and electronics for extreme temperatures. Before going into business for himself, he managed the processing laboratory at the R&D Center at a division of Eaton Corporation, where he was responsible for the fabrication of thin-film hybrids for microwave components. Prior to that, he was on the staff of the Jet Propulsion Laboratory, performing research on a variety of semiconductor materials and devices. During 1990-91 he was a Visiting Senior Research Fellow at the Institute of Cryogenics, University of Southampton, England. Between 1998-2005, he was a member of the Physics Department at Oxford University. He edited the 1999 IEEE Press/Wiley book High-Temperature Electronics. He completed his undergraduate studies at the University of California, and earned his Ph.D. in Physics and Electrical Engineering at the California Institute of Technology in 1972.

S6: Near Hermetic Packaging Concepts for Military and Medical Devices
PDC Instructor: Thomas J Green, TJ Green Associates LLC

Course Description: Packages made from plastics/polymeric materials (e.g. LCP) as opposed to traditional hermetic seals (i.e. metals, glasses and ceramics) offer the promise of reduced cost, less weight, better performance, smaller footprint etc. - but are they as good as the replacement hermetic part? That is the focus of this half day seminar. The problem is now one of moisture permeability through the bulk of the plastic and at the interface of the adhesive, which is different than water vapor permeating a crack in a glass to metal seal. A brief review of the techniques and methods to evaluate a "near-hermetic" approach is presented along with a discussion of the pitfalls and issues of TM 1014 (Seal) and TM 1018 (Internal Water Vapor) as applied to a "near" or non-hermetic package. Leak test data only provides a single, one time room ambient check of the seal. Moisture ingress as a function of time based on ambient temperature, pressure and humidity conditions is a critical aspect in qualification. How to incorporate and use a micro moisture sensor inside the package will be reviewed in detail. The latest developments on NASA Class Y and other Mil specs intended for qualification of non-hermetics will be reviewed and questions answered.

Who Should Attend? This PDC is intended for process engineers, designers, quality engineers, and managers responsible for sealing, testing and evaluating non-hermetic polymeric cavity and molded style packages

Thomas Green is the principle at TJ Green Associates LLC (www.tjgreenllc.com) a veteran owned small business focused on training and consulting for military, space and medical microelectronic devices. He has over thirty years experience in the microelectronics industry at Lockheed Martin and USAF Rome Laboratories. At Lockheed he was a Staff engineer responsible for the materials and manufacturing processes used in building custom high reliability space qualified microcircuits for military and commercial communication satellites. Tom has broad experience in all aspects of microelectronics packaging, specifically sealing and hermeticity testing. He has conducted experiments and presented technical papers at NIST and IMAPS on leak testing techniques and optimization of seam welding processes. Tom regularly attends EIA/JEDEC meetings and is an active member of IMAPS and a Fellow of the Society. He has a B.S. in Materials Engineering from Lehigh University and a Masters from the University of Utah.

S7: Signal/Power Integrity Design for Electronic Packaging and 3D System Integration - **UPDATED COURSE**
PDC Instructors: Dr. Ivan Ndip, Fraunhofer IZM; Professor Ege Engin, San Diego State University; Dr. Antonio Ciccomancini Scogna, CST of America

Course Description: Efficient and low-cost design of electronic packages, PCBs and 3D integration technologies requires a good understanding of the root causes of signal integrity (SI), power integrity (PI) and electromagnetic interference (EMI) problems at GHz frequencies, as well as methods to analyze, prevent or solve them. The objective of this course is to illustrate a wide range of methods for electrical modeling, measurement and optimization of electronic packages, PCBs and 3D integration technologies, under consideration of SI, PI and EMI/EMC effects. Measurement techniques for extracting the relative dielectric constant and loss tangent of electronic packaging materials will also be discussed. Finally, design guidelines for system optimization will be provided.

Course Outline:

  • Introduction
    • Technologies for advanced packaging and 3D integration
    • High-speed design challenges
  • Signal Integrity Design and Optimization
    • Lossy transmission lines considering surface roughness and glass weave effect
    • Signal vias in organic and glass interposers
    • Through silicon vias (TSVs) in active and passive silicon for 3D integration
    • Efficient methods for performing signal integrity simulations, considering package/PCB co-simulation
  • Power Integrity Design and Optimization
    • Power-ground plane pairs
    • Decoupling capacitors and simultaneous switching noise (SSN)
    • Electromagnetic band gap (EBG) structures and photonic crystal power/ground layers (PCPLs) for suppressing SSN coupling
    • Efficient methods for performing power integrity simulations
  • Measurement and extraction of relative dielectric constant and loss tangent of packaging materials.

Who Should Attend? Engineers, scientists, researchers, designers, managers and technicians involved in the process of layouts, simulation, design, integration and optimization of electronic packages, PCBs and interconnections.

Dr. Ivan Ndip obtained his M.Sc., and Ph.D. with the highest distinction (Summa Cum Laude) in electrical engineering from the Technical University Berlin, Germany. In 2002, he joined the Fraunhofer-Institute for Reliability and Microintegration (IZM) Berlin as a Research Engineer and worked on signal integrity modeling and design as well as on antenna integration. Since 2006, he has been a Senior Research Engineer and Group Manager of RF & High-Speed System Design, where he's responsible for leading a team of Research Engineers and Graduate Students as well as for developing and leading research projects that focus on electromagnetic modeling, design and optimization of RF/high-speed packages/boards/modules, integrated antennas and passive RF front-end components.

Since 2008 Dr. Ndip has also been a Lecturer in the Department of High-Frequency and Semiconductor System Technologies, School of Electrical Engineering and Computer Sciences, Technical University Berlin. He is currently engaged in teaching courses on Numerical Techniques in Electromagnetics and on Electromagnetics for Design and Integration of Microsystems. He has more than 100 publications and has won 6 best paper awards at leading international conferences. Dr. Ndip is also a recipient of the Tiburtius-Prize, awarded yearly for outstanding Ph.D. dissertations in the state of Berlin, Germany.

Dr. Ege Engin received his B.S. and M.S. degrees in electrical engineering from Middle East Technical University, Ankara, Turkey, and from University of Paderborn, Germany in 1998 and 2001, respectively. He received his Ph.D degree with Summa Cum Laude from the University of Hannover, Germany in 2004. Dr. Engin has worked as a research engineer with the Fraunhofer-Institute for Reliability and Microintegration in Berlin, Germany and at Georgia Tech. He is currently an Assistant Professor in the Electrical and Computer Engineering Department of San Diego State University. He has more than 60 publications in the areas of signal and power integrity modeling and simulation and 4 patent applications. He has co-authored the book "Power Integrity Modeling and Design for Semiconductors and Systems," published by Prentice Hall in 2007.

Dr. Antonio Ciccomancini Scogna received the Laura and Ph.D. degrees in electrical engineering from the University of L'Aquila, L'Aquila, Italy, in 2001 and 2005, respectively. He is currently a Principal Engineer at Computer Simulation Technology (CST) of America, Framingham, MA. His research interests include electromagnetic compatibility numerical modeling, printed and integrated circuits, electromagnetic packaging effects, signal integrity and power integrity analysis in high-speed digital systems. He has authored or coauthored more than 50 publications in IEEE journal transactions, IEEE conference proceedings, and Electronic Design Automation (EDA) magazines. Dr. Ciccomancini is a member of Applied Computational Electromagnetic Society (ACES), Institution of Engineering and Technology (IET), EMC TC-9 and TC-10 Committees. In 2004, he received the CST University Publication Award for the use of the finite-integration technique in signal integrity applications. He is the recipient of DesignCon Finalist Best Paper Award in 2007 and DesignCon Best Paper Award in 2008.

S8: Understanding Failure and Root-Cause Analysis in Pb-Free Electronics
PDC Instructor: Greg Caswell, DfR Solutions

PDC CANCELLED

S9: Patents and Intellectual Property for Technology Companies
PDC Instructor: Paul Hoffman, Sapient Focus, Inc

PDC CANCELLED

S10: A Technologists Guide to Determining and Exploiting the Value of Innovation
PDC Instructors: Chris Halliwell, Technology Marketing Center; Lee Smith, IMAPS Executive Council, Guest Speaker

PDC CANCELLED


Monday, September 10, 2012
Monday PDCs run 9:00 am - 5:00 pm

M1: 2.5D and 3D Interposer Technologies and Applications
PDC Instructor: Venky Sundaram, Georgia Tech 3D Systems Packaging Research Center

Course Description: This course will present a comprehensive review of the latest 2.5D and 3D interposer approaches being developed worldwide. High density interposers are emerging as a mainstream technology for packaging of heterogeneous ICs and 3D ICs, but also as a simpler and better alternative to 3D ICs with TSV, eventually providing a path for integration of sub-systems or entire systems. Silicon and glass interposers are emerging as the front-runners to address the I/O, CTE, warpage and thermal limitations of current organic packages. The topics covered include Electrical & Mechanical Design, Silicon Interposers, Glass Interposers, Chip Level & Board Level Interconnections, Applications and Markets, and Manufacturing Infrastructure for interposers. Wafer based BEOL Si interposers as well as emerging panel based glass and other interposer technologies will be described in detail. A variety of materials and process options for interposer fabrication will be presented. The technical and business challenges that must be addressed for successful implementation of interposers in 3D packages will be discussed. Specific examples of key interposer developments such as Xilinx stacked silicon interconnect, MEMS packaging using glass interposers, silicon interposer for high performance CPU packaging, and logic-memory high bandwidth 3D integration will be highlighted.

Who Should Attend? The course is a must-attend event for those highly interested in interposer technology advances for the future. The course is intended for a broad audience including semiconductor and packaging managers, technologists, engineers, industry and academic researchers, and students.

Dr. Venky Sundaram is the Director of Research at the 3D Systems Packaging Research Center (PRC), Georgia Tech. He is the Program Manager for the Silicon and Glass Interposer (SiGI) industry consortium with more than 20 active global industry members. His research expertise is in the areas of System on a Package (SOP) technology, 3D packaging and integration, ultra-high density interposers, embedded components and systems integration research. He is a globally recognized expert in packaging technology and a co-founder of Jacket Micro Devices, an RF/wireless start-up acquired by AVX. Dr. Sundaram is the co-chairman of the IEEE CPMT Technical Committee on High Density Substrates and is on the Executive Council of IMAPS as Director of Education Programs. Dr. Sundaram has won several best paper awards and has 15+ patents and 100+ publications. He received his BS from IIT Mumbai, and MS and PhD in Materials Science and Engineering from Georgia Tech.

M2: Microelectronics Packaging 2012 Industry Updates and Trends
PDC Instructor: Phillip G. Creter, Creter & Associates

Course Description: This NEW course (including leading edge technical developments to mid 2012) features the latest in microelectronics updates and trends for all levels of technical experience. Specific topics discussed: 2.5D-Interposers (Silicon/Glass), 3D-IC-TSV Packages, 3D Package-on-Package, Advanced Interconnections (including Copper Wire Bonding), Embedded Chip/Wafer Level Packaging, Emerging Packaging, Flip Chip and Wafer Bumping (including Copper Pillars), Handling Thin Wafers, Lead-Free Solder, LED Packaging, Low Cost Packaging, Low-Temperature Co-Fired Ceramic, MEMS Packaging, Package and Solder Joint Reliability (including Electromigration), Polymers/Molding Compounds Used in Packaging, Printed Electronics, System-in-Package/System-on-Chip, Wafer Thinning/Handling, and Future Trends for Wafer Level Packaging.

A short review of basic packaging steps of wafer singulation, chip attach, interconnect, and final packaging is presented to allow easy understanding by an attendee with no prior knowledge of microelectronics packaging.

Technical innovations related to the above topics is presented with input from leading organizations: Advanced Semiconductor Engineering (ASE), Amkor, Cisco Systems, Draper Labs, Fraunhofer IZM, Georgia Institute of Technology, IBM, Infineon, Institute of Microelectronics, A*STAR, Intel, Industrial Technology Research Institute (ITRI), International Technology Roadmap for Semiconductors (ITRS), Qualcomm, Samsung, Taiwan Semiconductor Manufacturing Company (TSMC), Xilinx and others.

Emphasis will be on visual aids with pass-around microcircuit samples, and a variety of photos, figures and videos. An invaluable handout (300+ slides) includes over 200 references.

Who Should Attend? Designed for all levels of engineers including others with little knowledge of microelectronics packaging. Topics for sales/marketing, purchasing, safety, and management.

Phillip Creter has over 30 years of microelectronics packaging experience. He is currently a consultant gaining his microelectronics packaging experience at Polymer Flip Chip Corporation, Mini-Systems, GTE and Itek Corporation. His past positions include GTE's Microelectronics Center Manager (received Corporate Technical Achievement Award), Process Engineering Manager, Process Development Manager, Materials Engineering Manager, and Manufacturing Engineer. He has published more than a dozen technical papers, holds a U.S. patent, has given over twenty technical presentations, and has chaired numerous technical sessions for symposia. He has been teaching courses at the college level since 1997. Since 2004, has continuously taught microelectronics PDCs for online webinars and at various symposia and workshops. He is an active certified instructor for the Department of Homeland Security currently teaching courses locally. He is a Life member of IMAPS. He was elected Fellow of the Society, National Treasurer and President of the New England Chapter (twice).

M3: Wire Bonding
PDC Instructor: Lee Levine, Process Solutions Consulting, Inc.

PDC CANCELLED

M4: Package on Package Technology - What It Is, What Works, What Doesn’t Work
PDC Instructor: Ning-Cheng Lee, Indium Corporation

Course Description: This course covers Package on Package (PoP) Technology, including trends, designs, material selection, processes, and reliability. The approaches of enhancing the reliability will be discussed in details, including effect of fluxes, solder alloy types, processes, profiles, via designs, and ball sizes. Being the solution with the highest potential, epoxy flux will be introduced and will be compared with other solutions. Finally, head in pillow control at reflow soldering, particularly at PoP will be instructed. The control includes considerations on materials, processes, and designs.

Course Content:

  • Trends
  • Designs
  • Processes - General
  • Processes - Rework of PoP
  • Processes - Selection of Dip Transfer Fluxes and Solder Pastes for PoP Assembly
  • Processes - Low Volume PoP Assembly Process Development
  • Processes - Design for Efficient PoP Underfilling
  • Processes - Comparison of Various Polymeric Reinforcement Approaches for PoP/CSP
  • Reliability - One-Pass vs Two-Pass
  • Reliability - Effect of SOP & Material on Yield & Drop Test Performance
  • Reliability - Effect of Materials & Profiles
  • Reliability - Materials Selection & Parameter Optimization
  • Reliability - Mixed Alloy
  • Reliability - Effect of Coplanarity and Design
  • Reliability - Effect of Ball Size, Via Size, Alloy Type on Stack-up Height & Reliability
  • Reliability - Opens/Head-in-Pillow - The Primary Failure Mode of PoP

Who Should Attend? Anyone who cares about successful implementation of package on package technology, and like to know how to achieve it should take this course.

Ning-Cheng Lee is the Vice President of Technology of Indium Corporation of America. He has been with Indium since 1986. Prior to joining Indium, he was with Morton Chemical and SCM. He has more than 20 years of experience in the development of fluxes and solder pastes for SMT industries, plus experience in underfills and adhesives. He received his PhD in polymer science from University of Akron in 1981, and BS in chemistry from National Taiwan University in 1973. Ning-Cheng is the author of "Reflow Soldering Processes and Troubleshooting: SMT, BGA, CSP, and Flip Chip Technologies", and co-author of "Electronics Manufacturing with Lead-Free, Halogen-Free, and Conductive-Adhesive Materials". He was honored as 2002 Member of Distinction from SMTA, 2003 Lead Free Co-Operation Award from Soldertec, 2006 Exceptional Technical Achievement Award from CPMT, 2007 Distinguished Lecturer from CPMT, 2009 Distinguished Author from SMTA, and 2010 Electronics Manufacturing Technology Award from CPMT.

M5: Polymers in Electronic Packaging
PDC Instructor: Dr. Jeffrey Gotro, InnoCentrix, LLC

Course Description: The course will provide an overview of polymers and the important structure-property-process-performance relationships for electronic packaging. The main learning objectives will be 1) understand how polymers are used in electronic packaging, 2) learn why specific chemistries are used depending on the application 3) learn the fundamentals of polymer characterization related to electronic packaging 4) develop a foundation in rheology and rheology issues in electronic packaging. Participants are invited to bring problems for discussion.

Who Should Attend? Packaging engineers involved in the development, production, and reliability testing of electronic packages would benefit. Those interested in gaining a basic understanding of the role of polymers and polymer-based materials used in electronic packaging will also find this PDC valuable.

Dr. Jeff Gotro has over twenty-eight years of experience in polymers for electronic applications and composites having held scientific and leadership positions at IBM, AlliedSignal, Honeywell, and Ablestik Laboratories. Jeff is a nationally recognized authority in thermosetting polymers and has received invitations to speak at prestigious Gordon Research Conferences (Thermosetting Polymers and Composites). He has presented numerous invited lectures and short courses at technical meetings, has over 60 technical publications and 21 patents/patent applications. Jeff was an Adjunct Professor at Syracuse University in the Dept. of Chemical Engineering and Materials Science from 1986-1993. Jeff is a member of the Product Development and Management Association (PDMA), American Chemical Society (ACS), the Institute for Management Consultants (IMC), the Forensic Expert Witness Association (FEWA), and the International Microelectronics and Packaging Society (IMAPS).

M6: Adhesion Fundamentals in Microelectronic Packaging
PDC Instructor: Raymond A. Pearson, Lehigh University

Course Description: Polymers are widely used in electronic packaging. The lack of adhesion can adversely affect reliability as well as package performance. The intention of this course is to review the fundamentals of adhesion and apply them to interfaces found in Plastic-Quad Flat Packs (PQFP), chip-scale packages (CSP), Flip-Chip (FC) assemblies, and optoelectronic packages. Adhesion issues in molding compounds, die attach adhesives, optoelectronic adhesives, and underfill resins will be covered. Also, recent trends in using nanotechnology to toughen epoxy resins will be reviewed. By the end of the course, you should know how to choose the proper tools to predict and measure adhesion.

Who Should Attend? Engineers, scientists and managers involved in the design, process and manufacturing of IC electronic components and hybrid packaging, electronic material suppliers involved in materials manufacturing and research & development.

Dr. Raymond A. Pearson joined the Materials Science and Engineering Department at Lehigh University in August of 1990 after obtaining his doctorate in Materials Science and Engineering from University of Michigan. Prior to graduate school, Ray had worked for seven years with General Electric Company: from 1980-1984 as an associate staff member at GE's Corporate Research and Development Center in Schenectady, New York and from 1984-1987 as a materials specialist at GEPE's Product Technology Center in Bergen op Zoom, the Netherlands. His research interests include all aspects of processing, deformation, yield, and fracture of polymers. He has extensively in the area of fracture mechanisms and adhesion. In 2001, Ray became Director of the Center for Polymer Science & Engineering. He has worked closely with organizations such as the Semiconductor Research Corporation and SEMATECH.

M7: Technology of Screen Printing
PDC Instructors: Art Dobie, Sefar Inc.; David Malanga, Heraeus, Inc., Thick Film Division

Course Description: Screen printing continues to offer innovative and cost effective solutions to the increasing demands for higher circuit densities. This course is intended to increase the understanding of the screen printing process, thereby improving production yield and print quality.

Presented are some of the latest advancements in composition, screens, and printing technology that enable screen printing to meet future circuit density requirements as well as the definition required for microwave circuitry. The advantages of screen printing, an additive deposition process, are described and compared to alternative more costly and "less-green" subtractive deposition technologies. This course is applications-oriented in terms of how to optimize the screen printing process; how to use and specify screen correctly; rheology properties that affect print results; minimizing printing defects and trouble-shooting problems related to screens, inks and the printing process itself.

Who Should Attend? This course is targeted for production and process engineers, plant and production managers and supervisors, and all others interested in learning how to optimize and increase the use of the screen printing process.

Art Dobie is Technical marketing Manager for Sefar, Inc. He has been with Sefar over 30 years since receiving his BS in Screen Printing Technology in 1980 from California University of Pennsylvania. Art has co-instructed the IMAPS "Technology of Screen Printing" PDC since its inception in 1991. He has delivered numerous technical presentations to screen-printing professionals at local, national and international level symposia. Mr. Dobie is a Life Member and Fellow of the Society of IMAPS, and received the 2006 IMAPS Technical Achievement Award for outstanding technical contributions to screen printing technology relating to microelectronics. In 1998, Art Dobie was inducted into the SGIA's Academy of Screen Printing Technology and is a co-recipient of the SGIA's 2010 David Swormstedt, Sr. Memorial Award.

David Malanga is currently the Business Unit Manager Americas, Thick Film Materials Division of Heraeus in West Conshohocken, PA. David has over 20 years of experience at Heraeus working in R&D, formulating thick film and LTCC materials, Technical Service solving processing and application problems directly with customers, and as manager of the Sales Department. David has a B.S. and M.S. in Ceramic Science and Engineering from Rutgers University. David has published various articles on thick film resistors, conductors, LTCC materials, and component metallizations worldwide. He is a Life member and Fellow of the Society of IMAPS and has held both local and national positions in the organization.

M8: Hermeticity Testing of Microelectronics for Aerospace and Medical Applications
PDC Instructor: Thomas J Green, TJ Green Associates LLC

Course Description: Hermeticity testing of microelectronic packages is critical for aerospace and Class III medical implants. This course begins with an overview of hermetic sealing processes. Then the accepted leak test methods in Mil specs are described in detail, with an emphasis on the impact of tighter leak spec requirements. Issues with bomb times and pressures, measured leak rate vs air leak rates, helium desorption and other relevant issues will be addressed. The focus will be on practical issues facing the industry. The basic science and applicability of Optical Leak Test (OLT), Cumulative Helium Leak Detection (CHLD) and KR-85 radioisotope testing will be described with plenty of time for questions. The gas ambient inside the package as measured using Residual Gas Analysis (RGA) provides insight into the hermetic seal. Testing of small cavity MEMS packages according to the traditional Mil Spec TM 1014 requirements may not be sufficient to guarantee reliable operation. Difficulties and limitations in fine leak testing of small volume packages will be addressed. Surface area to volume ratio is an important concept, along with material outgassing and solutions to mitigate these problems. The instructor provides numerous excel spreadsheets to help with the calculations (e.g. Howl and Mann equation). Recommended Text Book: "Hermeticity of Electronic Packages" by Hal Greenhouse (Noyce Publications 2000). Instructors will also provide a handout on "Practical Guide to TM 1014" authored by Mr. Green.

Who Should Attend? This PDC is intended for process engineers, designers, quality engineers, and managers responsible for sealing, leak testing and RGA test results for hermetic packages.

Thomas Green is the principle at TJ Green Associates LLC (www.tjgreenllc.com) a veteran owned small business focused on training and consulting for military, space and medical microelectronic devices. He has over thirty years of experience in the microelectronics industry at Lockheed Martin and USAF Rome Laboratories. At Lockheed he was a Staff engineer responsible for the materials and manufacturing processes used in building custom high reliability space qualified microcircuits for military and commercial communication satellites. Tom has broad experience in all aspects of microelectronics packaging, specifically sealing and hermeticity testing. He has conducted experiments and presented technical papers at NIST and IMAPS on leak testing techniques and optimization of seam welding processes. Tom regularly attends EIA/JEDEC meetings and is an active member of IMAPS and a Fellow of the Society. He has a B.S. in Materials Engineering from Lehigh University and a Masters from the University of Utah.

M9: Design and Analysis of Experiments
PDC Instructor: Jianbiao Pan, California Polytechnic State University

Course Description: The Design of Experiments (DOE) is a vital tool in microelectronics packaging product/process development and product/process optimization. The appropriate use of DOE can improve product quality and decrease costs. This course will enable the participant to plan and conduct experiments, analyze the resulting data, and draw valid conclusions. Practical examples related to microelectronics and electronic packaging will be given to illustrate the use of designed experiments.

This course covers various experimental designs including single factor experiments, completely randomized block designs, full factorial and fractional factorial designs. At the end of this course, participants will be capable and confident in designing and analyzing experiments to improve and optimize manufacturing processes. Specifically you will be able to:

  • Select appropriate input variables and response variable(s)
  • Choose and conduct the appropriate type of experimental design
  • Perform ANOVA analysis, including main and interaction effects, and residual analysis to check assumptions
  • Draw valid conclusions
  • Use the software to create experimental designs and perform statistical analysis.

Students are encouraged to bring along laptop computers to use during class.

Who Should Attend? Engineers, scientists, technicians, and managers in R&D, process development, and manufacturing, or individuals who desire to design their own experiments and/or analyze experimental data.

Dr. Jianbiao (John) Pan is an associate professor in Industrial and Manufacturing Engineering Department at Cal Poly State University, San Luis Obispo, California. He received a PhD in Industrial Engineering from Lehigh University, Bethlehem, PA. His research interests include the materials, processes, and reliability of microelectronics and optoelectronics packaging. He has studied extensively in improving microelectronics packaging processes and reliability using design of experiments methodology, and has published over 30 technical papers. He is a Fellow of IMAPS, a senior member of IEEE and SME, and a member of ASME, ASQ, and ASEE. Dr. Pan is a recipient of the 2011 Outstanding Educator Award from IMAPS, the 2004 M. Eugene Merchant Outstanding Young Manufacturing Engineer Award from SME, a Highly Commended Winner of the Emerald Literati Network Awards for Excellence in 2007, and the First Place winner of the IPC's Academic Poster Competition in 2009.

 

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