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IMAPS 2012 - San Diego
45th International Symposium on Microelectronics
Bringing Together The Entire Microelectronics Supply Chain!

September 9 - 13, 2012
San Diego Town & Country Convention Center
San Diego, California, USA

IMAPS 2012 - San Diego

Conference and Exhibition:
September 11-13, 2012
Professional Development Courses:
September 9 - 10, 2012

Early Registration / Hotel Deadline: August 15, 2012

Technical Program (Sessions)


Tuesday, September 11, 2012 | Morning Sessions: 8:00 AM - 11:15 AM

Registration: 7:00am-6:30pm
Exhibit Hall Open: 11:00am-7:00pm

2.5D/3D Packaging Track
Modeling, Design and Reliability Track
Next Generation
Materials Track
Assembly and
Packaging Track
Technologies Track

Packaging & System-Integration: A Global Perspective Track

TSV Materials & Processes

Chairs: Tim Lenihan, TechSearch International; Sesh Ramaswami, Applied Material

This session addresses a number of different issues associated with TSV costs, reliability, production and future developments.

Predicting the Reliability of Zero-Level TSVs
Greg Caswell, DfR Solutions (Craig Hillman)

Scallop-Free Bosch Process
Brad Eaton, Applied Materials

Optimizing Product Cost with Supply Chain Cost Modeling
Chet A. Palesko, SavanSys Solutions LLC (Alan C. Palesko)

3D Integration of Wide IO Memory Cube Stacking to 28 nm Logic Chip with High Density TSV through a Fabless Supplier Chain
Sam Gu, Qualcomm (D.W. Kim, V. Ramachandran, B. Henderson, U. Ray, and M. Nowak)

Break in Foyer: 9:40-10am

Understanding and Controlling Cu Protrusions in 3D TSV Processing
Seth Kruger, SEMATECH (Klaus Hummler, Robert Geer, Jack Enloe, Iqbal Ali, Brian Sapp, Kathleen Dunn, Aaron Cordes, Thomas Murray, Stefan Pieper, Sitaram Arkalgud)

An Overview - Temporary Wafer Bonding / Debonding for 2.5D and 3D Technologies
Rajen Chanchani, Consultant

A Novel Wafer-Level Double Side Packaging and Its Microwave Performance
Le Luo, Chinese Academy of Sciences (Xiao Chen, Jiajie Tang, Gaowei Xu)

Design for Reliability I

Chairs: Stevan Hunter, ON Semiconductor; Greg Caswell, DfR Solutions

This session addresses reliability issues ranging from die attach methodologies to packaging for enhanced reliability and test. Come learn about how to improve the reliability of these packaging approaches.

High-Reliability Component Attachment Process for <5µm Placement Accuracy
Donald J. Beck, Palomar Technologies (Zeger Bok, Senior Applications Engineer & Dan Martinez, Senior Manufacturing Engineer)

Getters and Design to Reliability: A Tool For Lifetime Assurance
Richard C. Kullberg, Vacuum Energy Inc. (Bradley L. Phillip)

Advanced Manufacturing Methods for Brazing High-Reliability Electronic Packages
Iris Labadie, Kyocera America, Inc.

Reliability Analysis of Low-Silver BGA Solder Joints Using Four Different Failure Criteria
Jianbiao Pan, California Polytechnic State University (Erin Kimura)

Break in Foyer: 9:40-10am

Advanced Materials & Novel Assembly Processes

Chairs: Yoon-Chul Sohn, Samsung Advanced Institute of Technology; Cristina Chu, NEXX Systems

In this session, novel materials incorporating various packaging devices & systems will be introduced. Electrical, mechanical, and thermal characteristics of the materials, in addition to reliability issues, will be discussed.

NiV stress control utilizing PVD with an Ar / N2 gas mixture
Georgiy Seryogin, TEL NEXX (S. Golovato, S. Smith, K. Williams)

Planarization of Deep Structures Using Self-Leveling Materials
Dongshun Bai, Brewer Science, Inc.(Michelle Fowler, Curtis Planje, Xie Shao)

Effects of the Impurities on the Embrittlement Phenomena of Electroplated Nickel Films
Yoonchul Sohn, Samsung Advanced Institute of Technology (Minjong Bae, Inyong Song, Sangeui Lee, Dongouk Kim, Kunmo Chu, Dongun Kim, Sunghoon Park, Hajin Kim, Intaek Han)

CO2 Technology Transforms Manufacturing
David Jackson, CleanLogix LLC

Break in Foyer: 9:40-10am

Mixed Attachment Technology Studies in RF & Optoelectronic Packages Requiring High Accuracy Placement
Daniel D. Evans, Jr., Palomar Technologies (Zeger Bok)

XTRONIC®: Enabler of Improved Performance with Reduced Precious Metal Usage in Microelectronics
B. Munoz, Xtalic Corporation (J.S. Sylvester, J.P. Cahalen and A.C. Lund)

Pb-Free Solder and RoHS
Chairs: Seth Homer, Indium Corp.; Ron Lasky, Indium Corp.

The push towards Pb Free and ROHS compliance is on going. This session is focused on process and reliabilty improvement while still meeting these requirements.

Lead-free Solder Durability in Wide Temperature Range Thermal-Vibration Environments
Patrick McCluskey, University of Maryland (Michael Crandall)

Pb-free PBGA Design Points to Improve Handling Robustness
Isabel de Sousa, IBM Canada (Brian Roggeman, Universal Instruments Corp.; Oswaldo Chacon, IBM Canada; Niki Spencer, IBM Systems & Technology Group; Mamoru Ueno, IBM Japan Ltd.)

High Reliability High Melting Lead-Free Mixed BiAgX Solder Paste System
Ning-Cheng Lee, Indium Corporation (Hongwen Zhang)

Effect of Extended Dwell Time on Thermal Fatigue Life of Ceramic Chip Resistors
Elviz George, Center for Advanced Life Cycle Engineering (Michael Osterman, Michael Pecht, and Richard Coyle)

Break in Foyer: 9:40-10am

Material Analysis of Lead Free Solder Deposited by Electrochemical Deposition
Tom Ritzdorf, Applied Materials (Sam Lee, Ian Drucker)

Smart and quick Dk, Df extraction flow of halogen-free and lead-free materials under different temperatures
Chang-Chih Liu, Industrial Technology Research Institute

Medical Device Packaging

Chairs: Kedar Shah, Lawrence Livermore National Lab; Sean Ferrian, Ferrian Consulting

The challenges and innovations in medical device packaging will be explored in this session. New materials, designs and issues will be reviewed and discussed. Novel devices will be presented to address the growing demand for implantables.

Reliability Study of Reference Semiconductor Encapsulation Materials for Biocompatible Packaging
Karl Malachowski, IMEC Belgium (Karen Qian, Maaike Op de Beeck, Rita Verbeeck, George Bryce, Harold Dekkers, Deniz Sabuncuoglu Tezcan)

Assembly and Packaging of a Wireless, Chronically-Implantable Neural Prosthetic Device
Kedar G. Shah, Lawrence Livermore National Laboratory (Vanessa Tolosa, Angela Tooker, Terri DeLima, Sarah Felix, Heeral Sheth, Satinderpall Pannu)

Epidermal electronics for health and fitness monitoring
Conor Rafferty, MC10, Inc (Colby Hobart, Brian Elolampi, Stephen Lee, Henry Wei, Yung-Yu Hsu, Dan Davis)

Laminate Materials for Microfluidic PCBs
Sarkis Babikian, University of California Irvine (Brian Soriano, G.P. Li, Mark Bachman)

Break in Foyer: 9:40-10am

Process integration solution for damage-free bevel for deep Si etch applications
Bivragh Majeed, imec (Nina Tutunjyan, Paolo Fiorini and Deniz. S. Tezcan)

Parylene as thin flexible 3-D packaging enabler for biomedical implants
Jimin Maeng, Purdue University (Dohyuk Ha, Pedro P. Irazoqui, William J. Chappell)

Miniaturization of Electronic Substrates for Medical Device Applications
Rabindra Das, Endicott Interconnect Technologies, Inc. (Frank D. Egitto, Francesco Marconi, Bill Wilson, Voya R. Markovich)

European Perspectives I

Chairs: Ivan Ndip, Fraunhofer IZM; Gabriel Pares, CEA LETI

Novel processes and technologies for biocompatible, MEMS, high-power and high-temperature packaging are presented in this session.

Realisation of High Temperature Electronics Packaging Technology for Sensor Conditioning and Processing Circuits
Steve Riches, GE Aviation Systems - Newmarket (Colin Johnston - Oxford University Materials)

Improvement of MEMs Packaging technologies through Residual Gas Analysis solutions
Gabriel Pares, Andre Rouzaud, CEA LETI (P. Nicolas, PL. Charvet, D. Bloch, X. Baillin)

Systematic feedback loop for silicon die pick& place process in reconstituted fan-out ewlb wafers in high volume production
Alberto Martins, NANIUM S.A. (Nelson Pinho - NANIUM S.A., Harald Meixner - DATACON (besi))

European R&D Trends in wire bonding technologies
Dr. Martin Schneider-Ramelow, Fraunhofer IZM Berlin (J. Goehre, U. Geisler, S. Schmitz, K.-D. Lang)

Break in Foyer: 9:40-10am

Biocompatible encapsulation and interconnection technology for implantable electronic devices
Maaike Op de Beeck, imec (John O'Callaghan, Karen Qian, Bishoy Mosaad, Alex Radisic, Karl Malachowski, Chris Van Hoof)

Packaging of High Power UV LED Modules on Ceramic and Aluminum Substrates
Marc Schneider, Karlsruhe Institute of Technology (KIT) (Benjamin Leyrer, Christian Herbold, Stefan Maikowske)

Exhibit Hall Open: 11:00am-7:00pm
Annual Business Meeting: 11:25am-11:40am
Awards Ceremony: 11:40am-12:00pm

Keynote: 12:00pm-12:45pm
Matt Grob, Qualcomm, Executive Vice President and Chief Technology Officer
Title: The Path to a 1000x Increase in Capacity for Mobile Networks

Lunch Break in Exhibit Hall: 12:50pm-1:50pm
Lunch Kiosks (Food available for purchase)


Tuesday, September 11, 2012 | Afternoon Sessions: 2:00 PM - 5:55 PM

Break in Exhibit Hall: 3:15pm-4:15pm
Exhibitor "Power Hour" Session on Materials For Packagin
Chairs: Ray Petit, Pacific Rim; Clark Steddom, Circuit Solutions, Inc.

University Poster Session - Interactive Forum: 2:30 - 4:30pm

2.5D/3D Packaging Track
Modeling, Design and Reliability Track
Next Generation
Materials Track
Assembly and
Packaging Track
Technologies Track

Packaging & System-Integration: A Global Perspective Track

TSV Interposers

Chairs: Bahareh Banijamali, Xilinx; Urmi Ray, Qualcomm

Integration using Si interposers offer better performance, form factor, scalability. Latest technology updates from a variety of different implantation schemes will be presented.

Through-silicon-via for silicon package
Yann LAMY, CEA, LETI, Minatec campus (Sylvain Joblot, Christine Ferrandon, Jean-Francois Carpentier, Gilles Simon)

High Frequency Signal Propagation in Through Silicon Vias
Srinidhi Raghavan Narasimhan, San Diego State University (A. Ege Engin)

Through Silicon Via (TSV) Technology Creates Electro-Optical Interfaces
Phil Marcoux, ALLVIA

Break in Exhibit Hall: 3:15-4:15pm

Quality and Reliability of 3D TSV interposer and Fine Pitch Solder micro-bumps FPGA/SERDES package
Bahareh Banijamali, Xilinx

Enabling the 2.5D Integration
John Y. Xie, Ph.D., Altera Corp.

Design and Process Optimization of Through Silicon Via Interposer for 3D-IC Integration
Pejman Monajemi, Invensas Corp. (Michael Newman, Cyprian Uzoh, Terrence Caskey)

Process Challenges in 0-Level Packaging using 100µm-Thin Chip Capping with TSV
Nga P. Pham, IMEC (Vladimir Cherman, Nina Tutunjyan, Lieve Teugels, Deniz S. Tezcan, Harrie A.C. Tilmans)

Electrical Modeling, Signal & Power Integrity

Chairs: Judy Priest, Cisco Systems, Inc.; Sanjay Sethi, Toshiba America

High speed interfaces and large scale integration presents increasingly complex challenges for electrical modeling and measurements. Chip, package, and board level SI/PI issues are explored and solved.

An Extended Comparison of 25 Gbps NRZ & PAM-4 Modulation Used in Legacy & Premium Backplane Channels
Chad Morgan, TE Connectivity (Adam Healey - LSI Corporation)

Measurement-based Signal Quality Test and Analysis of High-speed TSV Channel
Heegon Kim, KAIST (Jun So Pak, Daniel H. Jung, Jonghoon J. Kim and Joungho Kim)

IC Package optimization targeting multiple form factors
John Park, Mentor Graphics

Break in Exhibit Hall: 3:15-4:15pm

Impact of etch factor on characteristic impedance, crosstalk and board density
Abdelghani Renbi, Lulea University of Technology (Arash Risseh, Rikard Qvarnstrom, Jerker Delsing)

Propagation Delay Analysis in 3D Stacked Memory using Novel MOS Depletion Layer Modeling Approach for TSV
Kaushal Kannan, Nitte Meenakshi Institute of Technology (G.Harihara Sarma, Sukeshwar Kannan)

Thin-Film Signal and Power Redistribution Layers Based on AL-X and Cu
John Bailey, Auburn University ECE Department (Alexander Pfeiffenberger)

Meander Delay Compensation in High-Speed Digital Multilayer Packages
Robert C. Frye, RF Design Consulting LLC (Kai Liu, STATS ChipPAC Inc.

Polymers, Underfill/Encapsulants and Adhesives

Chairs: Jeff Gotro, Innocentrix; Mark Poliks, Endicott Interconnect Technologies

Polymers continue to be an enabling technology for both electronic reliability and technology extension. This session will hightlight recent advances in nanotechnology, underfills, and uses of polymers in electronic packaging.

The application of PEEK to implantable electronic devices packaging: water permeation calculation method and maximum lifetime with desiccant
Nathaniel Dahan, University College London

Precision Jetting of Glob Top Materials - A Methodology for Process Optimization
Karl-F. Becker, Fraunhofer IZM (Mathias Koch, Joerg Bauer, Tanja Braun, Rolf Aschenbrenner, Martin Schneider-Ramelow, Klaus-Dieter Lang)

Simulation and Experiment of Molded Underfill Voids
MyoungSu Chae, StatsChipPAC (MyoungSu Chae, Eric Ouyang, Jaehan Chung, Dokok Yu, Denny Gu,Gwang Kim, Billy Ahn)

Break in Exhibit Hall: 3:15-4:15pm

Highly conducting carbon nanotube composite for light-weight electric heating unit applications
Kun-mo Chu, Samsung Advanced Institute of Technology (Sung-hoon Park)

Multi-functional carbon nanotube composites with super-hydrophobic properties
Sung-Hoon Park, Samsung Advanced Institute of Technology (Eun-Hyoung Cho, Paul Theilmann, Kun-Mo Chu, Dong-Ouk Kim)

Managing Voids in Underfill Process within 5-micron Gap Under Large Die
Hanzhuang Liang, Nordson ASYMTEK

Wirebonding, Stud Bumping & Substrate Materials I

Chairs: Dan Evans, Palomar Technologies; Lee Levine, Process Solutions Consulting

Wire bonding continues as the dominant method of chip interconnection. This session explores Cu and Ag wire bonding, pad damage testing, Pb-coated Cu wire, wedge bonding advancements, low substrate temperature ball bonding, and discusses the future scalability of wire bonding.

Use of Wire Bonding to Study Bond Pad Damage from Wafer Probe
Stevan Hunter, ON Semiconductor and Idaho State University (Jonathan Clark, Darin Hornberger, Lance Rubio, Brigham Young University)

Pd-coated Cu Wire Bonding Reliability Requirement for Device Design, Process Optimization and Testing
Ivy Qin, Kulicke and Soffa (Inderjit Singh, Shin Low (Xilinx), Cuong Huynh, Horst Clauberg, and Bob Chylak (K&S), Hui Xu and Viola L. Acoff (U. of Alabama))

Wedge Bonding  RF and Microwave Devices
Lee Levine, Hesse & Knipps Inc (Joe Bubel)

Break in Exhibit Hall: 3:15-4:15pm

Gold Ball Wire Bonding with Heated Tool for Automotive Microelectronics
David J Rasmussen, Palomar Technologies

Glass-Insulated Bonding Wire Scales to Support Advances in Miniaturization
Dominik Stephan, RED Micro Wire (Yarden Tsach, Danny Hacohen) - will be presented by Lee Levine

Emerging Technologies

Chairs: Luu Nguyen, Texas Instruments; Susan Bagen, Endicott Interconnect Technologies

This session will introduce emerging technologies in thermal management, processes, materials and design for packaging of electronic devices.

Demonstration of Inkjet Printed Nanoparticle-based Inks for Solder Bump Replacement
Jacob Sadie, University of California, Berkeley (Steven Volkman, Vivek Subramanian)

A Novel Packaging Concept for Electronics in Textile UHF Antennas
Christian Boehme, Fraunhofer IZM (Rene Vieroth)

Comparison between Single & Multi Beam Laser Grooving of Low-K layers
Henry de Jonge, Jeroen van Borkulo, ALSI (Peter Dijkstra, Rene Hendriks)

Break in Exhibit Hall: 3:15-4:15pm

DNA Marking to Assure Product Authenticity
Mitchell Warren Miller, Applied DNA Sciences (Janice Meraglia)

The electrical and mechanical performance of Quilt Packaging based on solder paste
Quanling Zheng, University of Notre Dame

Advanced Stepper Through-Silicon Alignment (TSA) Evaluation and Overlay of Distorted Bonded Wafer Stacks
Doug Shelton, Canon USA (Chih-Yu (Charles) Wang)

Japan Perspective I

Chairs: Bill Ishii, Torrey Hills Technologies; Kishio Yokouchi, Fujitsu Interconnect Technologies

This session focuses on various interconnect and reliablility technologies, as well as design developments in Japan for advanced packaging architechtures.

Effect of preformed IMC Layer on Electromigration of Solder Capped Cu Pillar Bump Interconnection on an organic substrate
Yasumitsu Orii, IBM Research Tokyo (Kazushige Toriyama, Sayuri Kohara, Hirokazu Noma, Keishi Okamoto, IBM Research Tokyo; Keisuke Uenishi, Osaka University)

Planar Power Inductor with Magnetic Film for Embedded LSI Package
Tomoharu Fujii, Shinko Electric Industries Co., Ltd. (Kazutaka Kobayashi, Hiroshi Shimizu, Shinji Nakazawa, Shinko Electric Industries Co., Ltd.; Toshiro Sato, Fumihiro Sato, Hiroki Kobayashi, Shinshu University)

Investigation of electrical performance and mechanical reliability of device embedded power module
Masaya Tanaka, Dai Nippon Printing (Keisuke Sawada, Toru Serizawa, Shuji Sagara, Tatsuya Ikeuchi)

Break in Exhibit Hall: 3:15-4:15pm

New Flip Chip Interconnect Technology for High Performance and High Reliability Applications
Eiji Yamaguchi, CONNECTEC JAPAN Corporation (Mutsuo Tsuji, Nozomi Shimoishizaka, Takahiro Nakano, Katsunori Hirata)

Control of package warpage by package substrate design for low profile package-on-package structure
Takeshi Furusawa, IBIDEN CO., LTD. (Naomi Kawamura, Toshiki Furutani, Takashi Kariya)

Low Temperature Hybrid Bonding of Organic/Inorganic Substrates at Atmospheric Pressure
Akitsu Shigetou, National Institute for Materials Science

Electromigration Reliability of Glass Ceramic Multilayer Substrate with Various Surface Finishes
Hiroshi Matsumoto, Kyocera Corporation (Akira Wakazaki, Shingo Sato, Takashi Okunosono, Chihiro Makihara)

Reception in Exhibit Hall: 5:30pm-7pm


Wednesday, September 12, 2012 | Morning Sessions: 8:00 AM - 11:15 AM

Registration: 7:00am-6:00pm
Exhibit Hall Open:

2.5D/3D Packaging Track
Modeling, Design and Reliability Track
Next Generation
Materials Track
Assembly and
Packaging Track
Technologies Track

Packaging & System-Integration: A Global Perspective Track

2.5D/3D Packaging & Apps

Chairs: Kevin Moores, US Department of Defense; Chair: Anwar Mohammad, Huawei Technologies

This session examines emerging applications of 2.5D/3D packaging technology and key assembly issues that must be addressed in any such stacked application, including bump inspection, underfill, and temporary bonding/debonding.

Small Pitch Micro-Bumping and Experimental Investigation for Under Filling 3D Stacking
Antonio La Manna, IMEC-Belgium (Joeri De Vos)

Challenges in 3D Inspection of Microbumps Used in 3D Packaging
Reza Asgari, Rudolph Technologies, Inc.

Underfill Dispensing for 3D Die Stacking with Through Silicon Vias
Fred Fuliang Le, HKUST (Ricky Lee, Jingshen Wu, Matthew Yuen)

Exhibit Hall Open: 9-5:30pm
Break in Exhibit Hall: 9:15-10am

Use of 3D Packaging Technology for Satellite Active Antennas Front-ends
Barbara Bonnet, Thales Alenia Space (R. Chiniard, H. Legay, P. Monfraix, D. Nevo, O. Vendier, J.-L. Cazaux, Thales Alenia Space; P. Couderc, 3D Plus)

Package-Interposer-Package (PIP): A Breakthrough Package-on-Package (PoP) Technology for 3D-Integration
Rabindra Das, Endicott Interconnect Technologies, Inc. (Frank D. Egitto, Barry Bonitz, Mark. D. Polliks, and Voya R. Markovich)

Temporary Bonding and Debonding - An Overview of Today's Materials and Methods
Chris Rosenthal, SUSS MicroTec (Wilfried Bair)


Design for Reliability II

Chairs: Kevin McGrath, Northrop Grumman; Mark Nakamoto, Qualcomm

This session spans reliability topics from Process development, though Design, Package Architecture, Analysis and End of Life. Please join us in this broad sampling of reliability issues from Process to System level.

RF/Microwave Die Attach of Gallium Nitride Devices Achieving Less Than 1% Void Free in a Flux Free Environment
Pierino I. Zappella, SST International (Paul W. Barnes, Bruce Wilson)

A Numerical Study of Single Phase Dielectric Fluid Immersion Cooling of Multichip Modules
Roy W. Knight, Auburn University (Seth Fincher, Sushil H. Bhavnani, Daniel K. Harris, R. Wayne Johnson)

Supply Chain: Obsolescence Management & The Impact on Reliability
Greg Caswell,DfR Soltuions (Cheryl Tulkoff)

Exhibit Hall Open: 9-5:30pm
Break in Exhibit Hall: 9:15-10am

Ceramic & LTCC Packaging

Chairs: Dan Krueger, Honeywell FM&T; Ken Peterson, Sandia National Lab.

The emphasis of this session highlights the increased interest and usage of ceramic and low temperature cofired ceramic (LTCC) packaging. It includes a diverse set of topics including new materials; bio, RF, and microwave applications; processing techniques; and technology comparisons.

Characterization of Silicate Sensors on Low Temperature Cofire Ceramic (LTCC) Substrates Using DSC and XRD techniques
Mary C. Ruales, Universidad del Turabo

A ceramic tubular probe for online substance concentration measurement, manufactured by ceramic injection molding
Matthias Hartmann, Otto-von-Guericke University of Magdeburg (Prof. Dr. rer. nat. Bertram Schmidt)

Development of High Dielectric Strength Ceramic Film Capacitors for Advanced Power Electronics Devices
Beihai Ma, Argonne National Laboratory (Manoj Narayanan, Shanshan Liu, Uthamalingam (Balu) Balachandran)

Exhibit Hall Open: 9-5:30pm
Break in Exhibit Hall: 9:15-10am

Comparison of Silver vs. Gold Systems in High-Q FTTF LTCC Inductors
Matthew Clewell, Kansas State University (William B Kuhn)

Evaluation of Exothermic Reactions in Cofired Platinum /Alumina Microsystems
Kinzy Jones, Florida International university (Ali Karbasi)

Radiation Mechanisms and Electromagnetic Interference in Ceramic Electronic Packages
Jerry Aguirre, Kyocera America Inc (Marcos Vargas)

Wirebonding, Stud Bumping & Substrate Materials II
Chairs: Bernd Appelt, ASE US; Mike Ferrara, RF Micro Devices

In this session new observations in wire bond assembly will be discussed followed materials and process effects on substrates and assembly.

Copper Wire Bonding: R&D to High Volume Manufacturing
Bob Chylak, Kulicke and Soffa Industries, Inc. (Horst Clauberg, John Foley, Ivy Qin)

IC Bond Pad "Ripple Effect" Investigation
Stevan Hunter, ON Semiconductor (Darin Hornberger, Lance Rubio, Lynda Pierson)

How to Deal with Resonances in Wirebonding
Dr Josef Sedlmair, F&K Delvotec Bondtechnik GmbH

Exhibit Hall Open: 9-5:30pm
Break in Exhibit Hall: 9:15-10am

Response of Long Sculpted Wire Bonds to Vibrational Excitation
Thomas F. Marinis, Charles Stark Draper Laboratory (Joseph W. Soucy)

A Process For Treating Woven Glass Cloth
Dylan Boday, IBM Corp (Joe Kuczynski, Michael Haag, Johannes Windeln, Michael Waal)

High Performance Interconnect & Boards

Chairs: Julie Adams, Suntron Corp., Steven Davidson, Northrop Grumman

Increased wiring density, performance, reliability issues, and migration to lead free processes impart numerous challenges to the design and fabrication of high performance interconnects and PCBs. Issues related to reliability and performance, from the woven glass cloth to embedded components, drive board design and assembly considerations.

Novel ESD Protection Scheme for Testing High Voltage LDMOS
Kaushal Kannan, The University of Alabama, Tuscaloosa (Sukeshwar Kannan, Bruce C. Kim, Friedrich Taenzler, Richard Antley, Ken Moushegian)

Making New from Old
Nick Renaud-Bezot, AT&S (Mark Beesley)

UV Stabilization of i-line Photoresist and ARC Layer
Zeliha Yilmaz, Tubitak Bilgem (Murat Pak , Sema Amrahor Alyas , Aylin Ersoy)

Exhibit Hall Open: 9-5:30pm
Break in Exhibit Hall: 9:15-10am

2D Critical Dimension Optimization of Sub-micron Patterns using an Experimantal Methodology
Murat Pak, TUBITAK (Aylin Ersoy, Zeliha Yilmaz)

European Perspectives II

Chairs: Ivan Ndip, Fraunhofer IZM; Gabriel Pares, CEA LETI

In this session, reliable methods for measuring wafer stiffness, for electrolytic deposition of solder bumps, heat dissipation and chip stacking are presented. Innovative printing processes are also discussed.

Ultra thin chips stacking on tsv silicon interposer using back-to-face technology
Gabriel PARES, CEA-Leti (F. Schnegg, A. Attard, D. Cruau, F. De Crecy, A. Nahari, R. Anciant, G. Klug, H. Luesebrink, K. Martinschitz, C. Karoui, G. Simon)

Method to measure wafer stiffness in Fan-Out Wafer Level Package
Jorge Manuel Soares Teixeira, NANIUM, S.A.

Electrolytic Deposition of Fine Pitch Sn/Cu Solder Bumps for Flip Chip Packaging
Stephen Kenny, Atotech Germany (Kai Matejat, Frank Hilbert, Sven Lamprecht)

Exhibit Hall Open: 9-5:30pm
Break in Exhibit Hall: 9:15-10am

Stacking aspects in the view of scaling
Joeri De Vos, IMEC (Kenneth June Rebibis, Eric Beyne)

Aerosol-Jet Printing for Functionalization of Prototyping Materials for Electronic Applications
Johannes Hoerber, University of Erlangen-Nuremberg, Institute for Factory Automation and Production Systems (Christian Goth, Joerg Franke)

Formulation of percolating thermal underfills by hierarchical self-assembly of micro- and nanoparticles by centrifugal forces and capillary-bridging
Thomas Brunschwiler, IBM Research - Zurich (Gerd Schlottig, Songbo Ni, Yu Liu, Javier V. Goicochea, Jonas Zarcher, Heiko Wolf)

Keynote: 11:45am-12:30pm
Mehran Mehregany, Ph.D., Case Western University
Title: Wireless Health: Remaking of Medicine by Pervasive Technologies

Lunch Break in Exhibit Hall: 12:30pm-1:30pm


Wednesday, September 12, 2012 | Afternoon Sessions: 1:45 PM - 5:40 PM

Break in Exhibit Hall: 3:00pm-4:00pm
Exhibitor "Power Hour" Session on Packaging Solutions
Chair: Mumtaz Bora, Peregrine Semiconductors

2.5D/3D Packaging Track
Modeling, Design and Reliability Track
Next Generation
Materials Track
Assembly and
Packaging Track
Technologies Track

Packaging & System-Integration: A Global Perspective Track

Glass Interposers

Chairs: Venky Sundaram, Georgia Tech; Ravi Shenoy, Qualcomm

This session focuses on glass interposer technologies and applications in 2.5D and 3D packaging as a lower cost and lower loss alternative to silicon interposers. Papers will discuss different issues related to design, thin glass wafers and panels, fine pitch through via formation and metallization in glass, electrical performance benefits and reliability of vias in glass, and 2.5D and 3D applications for glass interposers.

Glass Wafers as support carriers for wafer thinning processes
Aric Shorey, Corning, Inc (Windsor Thomas)

Development of Through Glass Vias (TGV) for 3DS-IC Integration
Aric Shorey, Corning, Incorporated (Windsor Thomas, Scott Pollard)

Characterization of Interconnects and RF Components on Glass Interposers
Dr. Ivan Ndip, Fraunhofer IZM (Michael Toepper, Kai Loebbicke, Abdurrahman Oez, Stephan Guttowski, Herbert Reichl, Klaus-Dieter Lang)

Break in Exhibit Hall: 3-4:00pm

Advanced 3D Glass Microfabrication for IC Packaging Applications
Jeb H Flemming, 3D Glass Solutions (Kevin Dunn, Carrie Schmidt, James Gouker, Roger Cook)

Formation of Through-Glass-Via (TGV) by Photo-Chemical Etching with High Selectivity
Zingway Pei, Graduate Institute of Optoelectronic Engineering, National Chung Hsing University, Electronics and Optoelectronics Research Laboratories (EOL), Industrial Technology Research Institute (ITRI) (Jui-Po Sun, Hsin-Chen Lai, Pei-Jer Tzeng, Cha-Hsin Lin, Tzu-Kun Ku, Ming-Jer Kao)

A wafer-level system integration technology incorporates heterogeneous devices
Hiroshi Yamada, Toshiba Corporation, Corporate R&D Center, Electron Devices Laboratory (Yutaka Onozuka, Atsuko Iida, Kazuhiko Itaya, Hideyuki Funaki)

Package Reliability Testing

Chairs: Adam Schubring, Kyocera America; Akhlaq Rahman, Thin Film Technology Corp.

This session focuses on several reliability characterization techniques and testing results on electronic package. Discussions will vary from environmental effects to different material effects as well as mechanical stress on package. Evolution of different reliability test techniques along with test standards will also be discussed.

Isothermal Aging Effects on the Thermal Reliability Performance of Lead-Free Solder Joints
Zhou Hai, Auburn University (Jiawei Zhang, Sivasubramanian Thirugnanasambandam, John L. Evans, M. J. Bozack)

Thermal Characterization and Simulation of a fcBGA-H device
Eric Ouyang, StatsChipPAC (Jimmy He, MyoungSu Chae, SeonMo Gu, YongHyuk Jeong, Kyungmoon Kim, Gwang Kim, Billy Ahn)

Mechanical Stress Analysis and Evaluation of Hybrid Land Grid Array Attached Large Form Factor Organic Modules
Ying Yu, IBM Corporation (John Torok)

Break in Exhibit Hall: 3-4pm

Package Reliability Drop Shock and Temperature Cycling Testing Evolution, Challenges, and Trends
Michael Ferrara, RF Micro Devices, Inc.

Superior Drop Test Performance of BGA Assembly Using SAC105Ti Solder Sphere
Ning-Cheng Lee, Indium Corporation (Weiping Liu, Indium Corporation and Simin Bagheri, Polina Snugovesky, Jason Bragg, Russell Brush, and Blake Harper, Celestica International Inc.)

Solution for HVM TSV Etch Process
Rajiv Roy, Rudolph Technologies, Inc. (Matt Wilson, Product Manager)

Thermal Management

Chairs: Tom Tarter, Package Science Services, Bernie Siegal, Thermal Engineering Associates

Heat dissipated by electronic components, boards and systems has to be appropriately and timely dissipated to allow and ensure for expected operation and reliability of electronic equipment. In this session, topics presented range from validation procedures and all the way to the introduction of novel cooling techniques of various components and systems from the world of micro-electronics.

Accurate prediction of thermal resistance of fet by detailed modeling of heat generation and backend stackup
Qun Wan, RF Micro Devices (Don Willis, Daniel Jin)

Design Optimization of Micro-channel Heat Exchanger embedded in LTCC
Aparna Aravelli, University of Miami, FL (Singiresu S Rao, Hari K Adluru)

Thermal Solution of Mobile Application Processor - CANCELLED BY SPEAKER
Heung Kyu (Henri) Kwon, Samsung Electronics Co. (Jae Choon Kim, Jichhul Kim, Eun Seok Cho)

Break in Exhibit Hall: 3-4pm

Stacked Chip Thermal Model Validation using Thermal Test Chips
Thomas Tarter, Package Science Services LLC (Bernie Siegal, Thermal Engineering Associates, President)

Influence of thermal ageing on Void Content and shear strength for selected lead free Die-Attach
Kenny C. Otiaba, University of Greenwich (N. Raju, R.S. Bhatti, S. Mallik, P. K. Bernasko)

Flip Chip & Wafer Bumping

Chairs: Lyndon Larson, Dow Corning; Ron Jensen, Honeywell International

The continuing trend toward higher interconnect density, smaller bump geometries, and new lead-free materials presents challenges and reliability concerns for wafer bumping and flip chip assembly processes. This session highlights new developments that address electromigration and other metallization challenges as well as new materials for these applications.

Electromigration Performance of Flip-Chips with Lead-Free Solder Bumps between 30µm and 60µm Diameter
Rainer Dohle, Micro Systems Engineering GmbH (Stefan Haerter (University of Erlangen-Nuremberg, FAPS), Andreas Wirth (MSE), Joerg Gossler (MSE), Marek Gorywoda (University of Applied Sciences Hof), Andreas Reinhardt (FAPS), Joerg Franke (FAPS))

Optimization of Ag Composition in Cu Pillar Bumps with Sn-xAg Solders
Moon Gi Cho, Samsung Electronics Co., Ltd (Hwan Sik Lim, Sun Hee Park, Yong Hwan Kwon, Jaesik Chung, Jinho Choi, and Eun-Chul Ahn)

Assessment of XRF Technique as a Method to Measure Percent Ag in SnAg Solders for Flip Chip Applications
Chia-Hsin Shih, Jennifer Schuler, STATSChipPAC, IBM (Charles L Arvin, KyungMoon Kim, Eric Perfecto)

Break in Exhibit Hall: 3-4pm

The Distribution and Transport of Alpha Activity in Tin
Brett M. Clark, Honeywell International 

Printed Electronics & Additive Manufacturing

Chairs: John Bolger, US Department of Defense; Andy Tseng, ASE US

This session will cover a variety of topics of interest, from processing schemes for complex structures to characterization of novel materials.

Development of Silver Nanoparticle Ink for Printed Electronics
Yiliang Wu, Xerox Research Centre of Canada (Ping Liu, Tony Wiggelsworth)

High yield embedding of 30µm thin chips in a flexible PCB using a photopatternable polyimide based Ultra-Thin Chip Package (UTCP)
Tom Sterken, IMEC-UGent/CMST (Maaike Op de Beeck, Filip Vermeiren, Tom Torfs, Liang Wang, Swarnakamal Priyabadini, Kristof Dhaenens, Dieter Cuypers,  Jan Vanfleteren)

Additive Manufacturing of Fine Lines and Embedded Electronics for use in Chip Packaging and Microelectronic Systems
Scott Lauer, Advantech US, Inc (Pierluigi Benci, Compunetix; John Mazurowski, Penn State Electro-Optics Center; Whit Little, Advantech US, Inc.)

Break in Exhibit Hall: 3-4pm

Rediscovering Multilayer Rigid-Flex with Z-interconnect Technology
Rabindra Das, Endicott Interconnect Technologies, Inc. (Frank D. Egitto, John M. Lauffer, and Voya R. Markovich)

Development of Printed Power Packaging for a High Voltage SiC Module
Douglas C Hopkins, NC State University (Haotao KE)

AM Electronic Packaging
Ricardo Rodriguez, University of Texas, El Paso (Xudong Chen, nScrypt, Kenneth Church Ph.D., UTEP)

Japan Perspective II

Chairs: Bill Ishii, Torrey Hills Technologies; Kishio Yokouchi, Fujitsu Interconnect Technologies

This session focuses on various 2.5D / 3D, interposer, and material technologies, as well as design developments in Japan for advanced packaging architechtures.

Study of warpage and mechanical stress of 2.5D package interposers during chip and interposer mount process
Takashi Hisada , IBM Japan, Ltd. (Yasuharu Yamada, Junko Asai, Toyohiro Aoki)

Handling technology for 0.075-square mm powder IC chip
Hideyuki Noda, Hitachi, Ltd., Central Research Laboratory

Full Integration and Electrical Characterization of 3D Silicon Interposer Demonstrator incorporating high density TSVs and interconnects
Ken Miyairi, SHINKO ELECTRIC INDUSTRIES CO., LTD. (Masahiro Sunohara, Jean Charbonnier, Myriam Assous, Jean-Philippe Bally, Robert Cuchet, Helene Feldis, Gilles Simon and Mitsutoshi Higashi)

Break in Exhibit Hall: 3-4pm

New Build-up Insulation Material Based on Cyclo-Olefin Polymer for High Performance IC Packages
Yohei Tateishi, Zeon Corporation (Makoto Fujimura, Toshihiko Jimbo, Takashi Iga)

Scallop Free Si Etching and Low Cost Integration Technologies for 2.5D Si Interposer
Yasuhiro Morikawa , ULVAC, Inc. (Takahide Murayama, Toshiyuki Sakuishi, Manabu Yoshii and Koukou Suu)

Thermomechanical Design for Fine Pitch 3D-IC Packages
Akihiro Horibe, ASET (Sayuri Kohara, Kuniaki Sueoka, Keiji Matsumoto, Yasumitsu Orii, Fumiaki Yamada)

Thinner and Miniaturization Embedded Device Package, MCeP, for PoP and Module Application
Kouichi Tanaka , Shinko Electric Industries Co., LTD. (Nobuyuki Kurashima, Hajime Iizuka, Kiyoshi Ooi, Yoshihiro Machida, Satoshi Shiraki, Tetsuya Koyama)

GBC Marketing Forum: 5:45pm-6:45pm
GBC Networking Reception: 6:45pm-7:45pm


Thursday, September 13, 2012 | Morning Program: 8:00 AM - 12:00 PM

Registration: 7:00am-4:00pm
Exhibit Hall Open: 9:00am-12:00pm

3D Keynote: 8:00am-8:45am
Subu Iyer, IBM Fellow, IBM Systems and Technology Group
Title: Three-Dimensional Integration - A Systems' Perspective to Orthogonal Scaling

3D Keynote: 8:45am-9:30am
Rao Tummala, Director, Georgia Tech 3D Systems Packaging Research Center
Title: Inorganic-organic Packaging as the Basis for Smart Systems Packaging Revolution

Break in Exhibit Hall: 9:30am-10:45am
Exhibitor "Power Hour" on 3D IC/Packaging Solutions
Chair: Anwar Mohammad, Huawei Technologiess

3D Panel Discussion: 10:45am-12:00pm
Are Supply Chains Ready for 3D Integration Manufacturing?

Moderator: John Lau, Industrial Technology Research Institute (ITRI)
Panelists: Jeff Brighton, Texas Instruments; Nagesh Vodrahalli, Altera; Ron Huemoller, Amkor Technology; Rao Tummala, Georgia Tech, Subu Iyer, IBM

Lunch on Own: 12:00pm-1:00pm


Thursday, September 13, 2012 | Afternoon Sessions: 1:00 PM - 4:15 PM

2.5D/3D Packaging Track
Modeling, Design and Reliability Track
Next Generation
Materials Track
Assembly and
Packaging Track
Technologies Track

Packaging & System-Integration: A Global Perspective Track

3D Thermal/Mechanical

Chairs: Robert Darveaux, Amkor; Alex Bailey, Northrop Grumman

This session addresses a variety of critical topics in 3D thermal / mechanical engineering for both portable product and infrastructure applications. New insights into thermal stress analysis, solder joint ductility, copper pillar electromigration, and PoP warpage will be gained.

Electromigration Performance of Fine Pitch Copper Pillar Interconnections
Ahmer Syed, Amkor Technology, Inc. (Christopher J. Berry, Karthikeyan Dhandapani, Patrick Thompson, Seung-Hyun Chae)

Modeling in the Cloud: Web Hosted CPI Modeling for Fabless Design Houses and OSATs Method for Mechanical Stress Simulation Across the Chip & Package Domains in 3D IC's
Mark Nakamoto, Qualcomm (Karthikeyan Dhandapani, Wei Zhao, Ahmer Syed, Wei Lin, Riko Radojcic)

PoP package warpage contributors' characterization and impact analysis
Shengmin Wen, Amkor Technology Inc (Wei Lin, Akito Yoshida)

Thermal Stress and Creep Strain Analyses of a 3D IC Integration SiP with Passive Interposer for Network System Application
John H Lau, ITRI (Sheng-Tsai Wu, John H. Lau*, Heng-Chieh Chien, and Ra-Min Tain, L. Li, P. Su, J. Xue, M. Brillhart)

Break in Foyer: 2:40-3:00pm

Solder Joint Ductility
Robert Darveaux, Amkor (Michael Johnson)

Microwave and RF Applications

Chairs: Christopher Pan, Qualcomm; Jeremy Rodgers, Department of Defense

The RF and Microwave Application section has an array of papers that introduces new interconnect materials, and design and manufacturing techniques for applications at PCB and package levels to meeting the rising challenges in the fields of RF, Microwave, and high data rate digital communication.

3D Electromagnetic Modeling of Through Silicon Vias and Interposers in Electronic Packaging
Darryl Kostka, CST of America (Antonio Ciccomancini Scogna)

A Practical Approach to Analyze Copper Surface Roughness Effects with Applications to Stripline Structures
Xichen Guo, University of Houston (Ji Chen, David Jackson, University of Houston; Marina Y. Koledintsevat, James Drewniak, EMC Laboratory, Christopher Pan, FutureWei Technologies)

Influence of Different Packaging and Footprint Technique for Microwave Absorptive Bessel Filter's™ Performance
Akhlaq Rahman, Thin Film Technology Corporation

Investigation of Polyimide Based Coverlays on Handheld Device Antennas
Deepukumar Nair, DuPont (Glenn E Oliver, James Parisi)

Break in Foyer: 2:40-3:00pm

Virtual Ground Fence: A Simple Method for Protection against High Frequency Simultaneous Switching Noise
Jesse Bowman, San Diego State University (A. Ege Engin)

Automotive, Industrial & Harsh Environment Electronics Applications

Chairs: Larry Zawicki, Honeywell FM&T; Kevin McGrath, Northrop Grumman

This session will provide insight into the challenges related to high power and harsh environmental requirements driving the automotive, industrial and other areas where novel materials and processes are being pursued.

Dicing Development for low-k Copper Wafers using Nickel-Palladium-Gold Bond Pads for Automotive Application
Tu Anh Tran, Freescale Semiconductor (Varughese Mathew, Wen Shi Koh, K. Y. Yow, Y. K. Au)

Characterization of Over Pad Metallization (OPM) for high temperature reliability
Varughese Mathew, Freescale Semiconductor,Inc. (Tu Anh Tran)

Packaging of High Frequency, High Temperature Silicon Carbide (SiC) Multichip Power Module (MCPM) Bi-Directional Battery Chargers for Next Generation Hybrid Electric Vehicles
Z. Cole, Arkansas Power Electronics International, Inc. (B. Passmore, B. Whitaker, A. Barkley, T. McNutt, and A.B. Lostetter)

Evaluation of Thin-film High Voltage Capacitors for Hybrid Electric Vehicle Inverter Applications
M. Ray Fairchild, Delphi Corporation (Carl W. Berlin - Delphi, D.H.R. Sarma, Ph.D - Delphi, Ralph S. Taylor - Delphi)

Break in Foyer: 2:40-3:00pm

High Temperature Packaging for SiC Power Transistors
K. Brinkfeldt, Swerea IVF (T. Aklint, P. Johander, D. Andersson)

Moisture (and other contaminant) control for electronics packaging Samuel Incorvia, Multisorb Technologies (Ken Credle)

Think Thin: Thin IC Packaging For Mobile Devices

Chairs: Bet Keser, Qualcomm; Rich Rice, ASE US

Form factor is now a critical selling point for mobile and handheld devices in this day of exploding consumer demand, while the functionality of these devices continues to escalate. IC companies are now pressured more than ever to bring forth thinner packages which combine more functions than ever before. The objective of the "Think Thin" session will be to explore new and alternative technologies that enable packaging to meet the form factor requirements for today, as well as for the future, and will explore the technical issues and challenges that must be overcome.

Novel Ultra-Compact Quad-Band System-in-Package (SiP) Module with IC Embedded in Substrate Based on SESUB Technology
Volodymyr Sieroshtan, EPCOS AG (TDK-EPC) (Georgiy Sevskiy, Petro Komakha, Oleg Aleksieiev, Andriy Burygin, Oleg Chayka, Oleksandr Ruban, Mykola Shevelov, Kozo Kato, Akio Horibe, Hideaki Fujioka, Klaus Ruffing, Patric Heide, Martin Vossiek)

Going Thin - Potential Challenges Faced By The Industry
Sachin Deo, Micron Technology

Fine Pitch Copper Interconnects for Next Generation Package-on-Package (PoP)
Ilyas Mohammed, Invensas, Inc.

Embedded Die Substrates for Power Applications
Bernd K Appelt, ASE Group (Bruce Su, Uno Yen, Dora Lee, Kay Essig)

Break in Foyer: 2:40-3:00pm

Thin Substrates Bursting into the Market
Bernd K Appelt, ASE Group (Bruce Su, Dora Lee, Kidd Lee and Uno Yen)

Pushing the 3rd Dimension - Floppy Wafers, Die and Packages? Stress Induced Chip Package Interactions on Thin Mobile Devices
Mark Nakamoto, Qualcomm (Riko Radojcic Wei Zhao)

Thin PoP : Warpage control for Thinner PoP package in mobile applications
Yuka Tamadate, Shinko Electric Industries Co.,LTD., Seiji Sato, Hitomi Imai, Kota Takeda, Takeshi Meguro and Takashi Ozawa

Packaging for Light and MEMS

Chairs: Iris Labadie, Kyocera America; Marc Papageorge, Semiconductor Outsourcing Solutions

New lighting devices and MEMS are changing the industry. High brightness LEDs are overtaking all other device types for illumination applications. In this session, various types of LED, MEMS & sensor devices will be introduced. Materials, fabrication processes, evaluations, and reliabilities for the devices will also be discussed.

Highly Flexible Die Attach Adhesives for MEMS Microphone Packages
Dr. Tobias Koeniger, DELO Industrial Adhesives

A Low Firing Temperature Copper Conductor for use on an Aluminum Metal Compatible Dielectric in LED Thermal Substrate Applications
Samson Shahbazi, Heraeus Precious Metals North America Conshohocken LLC (Steve Grabey, and Ryan Persons)

Multiple gas sensing device based on nano-porous structure of zeolite coated with nile red dye
Son Nguyen, Temple University (Z. Joan Delalic, David M. Kargbo, Joel B. Sheffield)

Development of Synergistic opto-electronic sensing platform based on zinc oxide semiconducting nanopackage
Anurag Gupta, The University of Alabama-Tuscaloosa (Mitchell Spryn, Sukeshwar Kannan, Bruce Kim, Eugene Edwards, Christina Brantley, Paul Ruffin)

Break in Foyer: 2:40-3:00pm

ACES characterization of damping in micro-beam resonators
Jason Parker, Worcester Polytechnic Institute (Xiuping Chen, Vu Nguyen, Ryszard Pryputniewicz)


Taiwan Perspective

Chairs: Rajen Chanchani, Consultant; Sam Gu, Qualcomm

This session focuses on recent advanced package technology progress in Taiwan including 2.5D (large Si interposer) demonstration, electrical characterization of TSV, pre-mold substrate and board level optical interconnect.

Large Size Silicon Interposer and 3D IC Integration for System-in-Packaging (SiP)
John H. Lau, ITRI (John Lau, Pei-Jer Tzeng, Chau-Jie Zhan, Ching-Kuan Lee, and Ming-Ji Dai,Li Li, Peng Su, Jie Xue, and Mark Buillhart )

GHz High Frequency TSV for 2.5D IC Packaging
Chi-Han Chen, Advanced Semiconductor Engineering (ASE), Inc. (Chang-Ying Hung, Pao-Nan Lee, Meng-Jen Wang, Chih-Pin Hung, Ho-Ming Tong, ASE, Inc.; Kuan-Chung Lu, Tzyy-Sheng Horng, National Sun Yat-Sen University)

Electrical Performance of Through-Silicon Vias (TSVs) for High-Frequency 3D IC Integration Applications
Jui-Feng Hung, Industrial Technology Research Institute (John H. Lau, Peng-Shu Chen, Sheng-Che Hung, Shih-Hsien Wu, Shinn-Juh Lai, Ming-Lin Li, Shyh-Shyuan Sheu, Zhe-Hui Lin, Chih-Sheng Lin, Wei-Chung Lo)

Embossed Laminate Optical Layers On Printed Circuit Boards
Jonas Tsai, University of California Irvine (G.P. Li, Mark Bachman)




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