KESTER

   Platinum Premier Sponsor:

   Gold Premier Sponsor:
   Silver Premier Sponsor:
Natel - Premier Sponsor, Platinum
Heraeus Materials Technology - Premier Sponsor, Gold
Metalor - Premier Sponsor, Silver

IMAPS 2013 - Orlando
46th International Symposium on Microelectronics
Bringing Together The Entire Microelectronics Supply Chain!

September 30 - October 3, 2013
Rosen Centre Hotel
Orlando, Florida, USA

www.imaps2013.org

Conference:
October 1-3, 2013

Exhibition:
October 1-2, 2013:
Professional Development Courses:
September 30, 2013 &
October 3, 2013
(Morning 1/2 Day Only)

IMAPS 2013 - Orlando



Early Registration and Hotel Deadline: September 6, 2013


Technical Program

Monday, September 30, 2013

Professional Development Courses (PDCs)
8:00 AM - 5:00PM
(SALON ROOMS, Rosen Centre Hotel, Orlando, Florida)

PDC Morning Coffee Break in Salon Foyer: 10:00-10:15am
PDC Lunch in Salon 11-12: 12:00-1:00pm
PDC Afternoon Coffee Break in Salon Foyer: 3:00-3:15pm

PDC Coffee Breaks & Lunch sponsored by:
Heraeus Materials Technology - Premier Sponsor, Gold

 

Welcome Reception | 5:00 PM - 7:30 PM
(JR. BALLROOM F, Rosen Centre Hotel, Orlando, Florida)

Welcome Reception Sponsored by:

   Platinum Premier Sponsor:

   Gold Premier Sponsor:
   Silver Premier Sponsor:
Natel - Premier Sponsor, Platinum
Heraeus Materials Technology - Premier Sponsor, Gold
Metalor - Premier Sponsor, Silver
Featuring Natel's First Annual Supplier of the Year Awards

 

Schedule

INTERPOSERS & 2.5/3D PACKAGING

(SALON ROOM 3)

MODELING, DESIGN, TEST & REL

(SALON ROOM 5)

MATERIALS & PROCESSES

(SALON ROOM 1)

ADVANCED PACKAGING & ASSEMBLY

(SALON ROOM 6)

ADVANCED & EMERGING TECHNOLOGIES

(SALON ROOM 2)

SPECIAL SESSIONS ON PACKAGING & SYSTEM-INTEGRATION

(SALON ROOM 4)

Tuesday, October 1, 2013

8:00 AM -
11:15 AM

TSV Materials & Processes
Chairs: Gabriel Pares, CEA; Sesh Ramaswami, Applied Materials

TSV is one of the key technologies for 3D. Significant improvements have already been achieved on the materials and processes involved for its fabrication. However there still a lot to do to make it reliable and ready for high volume production.

Design & Analysis for Reliability
Chairs: Stevan Hunter, ON Semiconductor; Gopal Jha, Avago Technologies

High reliability is increasingly expected in microelectronic products. This session examines a variety of methods for improving device, assembly and packaging reliability by design.

Advanced Materials & Novel Assembly Processes
Chairs: Erica Folk, Northrop Grumman; Venky Sundaram, Georgia Tech PRC

Novel packaging materials will be introduced in conjunction with packaging assembly technologies. Various organic, inorganic and metallic materials are selected for the applications of 3D integration, packaging assembly, and die attachment.

Pb-Free Solder & ROHS
Chairs: John Bolger, Department of Defense; John Pan, Cal Poly State University

The continuing challenges of implementing lead-free solder will be examined in this session, as industry continues to evaluate options to improve the reliability of lead-free solder joints.

Medical Device Packaging
Chairs: Sean Ferrian, Ferrian Sales & Associates; Ying Yu, IBM Systems & Technology Group

This session will highlight materials, processes, and characterization methods for packaging biomedical devices and microfluidics to enable novel diagnostics and treatments.

European Perspective on Packaging Trends
Chairs: Andre Rouzaud, CEA LETI; Martin Schneider-Ramelow, Fraunhofer IZM

From key enabling technologies to advanced SiP and hybrid system integration: This session will give an insight on different novel technologies and materials required to fullfil the promise for the next generation of future systems.

8:00 AM -
8:25 AM

FEATURED SPEAKER:
Alternative technology concepts for low-cost and high-speed 2D and 3D interconnect manufacturing
Fred Roozeboom, Eindhoven Univ of Technology (M. Smets, B. Kniknie, M. Hoppenbrouwers, TNO; G. Dingemans, W. Keuning, W.M.M. Kessels, Eindhoven University of Technology; R. Pohl, A.J. Huis in't Veld, University of Twente)

Using Physics of Failure to Predict System Level Reliability for Avionic Electronics
Greg Caswell, DfR Solutions

Development of Laser and Photo-Definable Toughened Benzocyclobutene Dielectric Materials for 3D-TSV Integration
Zidong Wang, Dow Electronic Materials (Greg Prokopowicz, Kevin Wang, Joe Lachowski, Zhifeng Bai, Ray Thibault, Eric Huenger, Scott Kisting, Chris Tucker, Matt Bishop, Lynne Mills, Dave Louks, Michael Gallagher)

Effects of Minor Alloying Additive on the Shear Strength of Sn-58Bi Solder Joint
Omid Mokhtari, Joining and Welding Research Institute, Osaka University (Hiroshi Nishikawa)

CANCELLED BY AUTHOR

FEATURED SPEAKER
How are CCD, CMOS AND A-SI Reshaping the Medical Imaging Industry?
Christophe Fitamant, Yole Developpment

FEATURED SPEAKER
Assembly and Packaging Enabling System Integration
Klaus Pressel, Infineon Technologies

8:25 AM -
8:50 AM

Optimizing TSV Liner Step Coverage
Vijayalakshmi Seshachalam, GLOBALFOUNDRIES Inc.

CANCELLED BY AUTHOR

Solder Joint Reliability Study for Wafer Level Packages on Flexible and Rigid Boards
Gary Gu, RF Micro Devices Inc (Daniel Jin, Jon Chadwick)

Small-chip Attachment on Copper Leadframe with Sintered Nanosilver Paste
Hanguang Zheng, Virginia Tech (Jesus Calata, Guo-Quan Lu, Khai Ngo, Luu Nguyen)

Effects of Sb and Zn Addition on Impact Resistance Improvement of Sn-Bi Solder Joints
Keishiro Okamoto, Fujitsu Laboratories Ltd. (Toshiya Akamatsu, Seiki Sakuyama, Keisuke Uenishi)

Biomedical Sensor Packaging Failures: Regulations are not Design Standards
Colin Drummond, Case Western Reserve University

Smart Power Module Molding Advances:
Evaluating High Temperature Suitability of Molding Compounds

Karl-F. Becker, Fraunhofer IZM (T. Thomas, J. Bauer, L.-H. Daus, R. Kahle, T. Braun,
R. Aschenbrenner, M. Schneider-Ramelow, K.-D. Lang)

8:50 AM -
9:15 AM

Monitoring of Wet Etch for Wafer Thinning and Via Reveal process
Chuannan Bai, ECI Technology (Eugene Shalyt, Guang Liang, Peter Bratin)

Ag-Wire and Ag Alloy Wire Relaibility and Molding Compound
Aya Mizushima, Hitachi chemical (Yoshinori Endo, Hidenori Abe, Shinichiro Kato, Kazuhiro Ikemura, Naoki Sadayori)

Influence of the organic vehicle and inorganic additives on the properties of thick film pastes for AlN
Richard Schmidt, Fraunhofer IKTS (Marco Wenzel, Kathrin Reinhardt, Markus Eberstein, Lars Rebenklau)

Effect of Fe Content on the Interfacial Reliability of SnAgCu/Fe-Ni Solder Joint
Zhi-Quan Liu, Institute of Metal Research, Chinese Academy of Sciences

CANCELLED BY AUTHOR

Evaluation of Epoxy Flux for Use in Hearing Aid SMD Assemblies
Susie Krzmarzick, Starkey Hearing Technologies (John Dzarnoski)

Ultrasonically Enabled Low Temperature Electroless Plating for Advanced Electronic Manufacture
Dr Andrew J Cobley, Coventry University (Graves J E, Kassim A, Mkhlef B, Abbas B)

9:15 AM -
9:40 AM

2.5 / 3D
Packaging Technology Solution for High Frequency Device

Yasuhiro Morikawa, ULVAC,Inc. (T. Murayama1, A. Suzuki, T. Sakuishi, Y. Nakamuta and K. Suu)

Moisture Reliability Improvement of a High Performance Depletion Mode 0.15 um Gate PHEMT Process
J. K. Abrokwah, Avago Technologies (John Stanback, Molly Johnson, Chi L. Jiaa)

Better, Faster and Cheaper Precision Cleaning:
Advanced CO2 Cleaning Technology

David Jackson, CleanLogix LLC

Effect of ENEPIG Surface Finish on the Vibration Reliability of Solder Interconnects
Sandeep Menon, CALCE, University of Maryland (Adam Pearl, Michael Osterman, Michael Pecht)

Anti-Counterfeit, Advanced Microelectronics Packaging Solutions for Miniaturized Medical Devices
Rabindra Das, Endicott Interconnect Technologies, Inc. (Frank D. Egitto, How Lin)

Hybrid In-Mould Integration
Teemu Alajoki, VTT (Matti Koponen, Arttu Huttunen, Markus Tuomikoski, Mikko Heikkinen, Antti Keranen, Kimmo Keranen, Jukka-Tapani Makinen, Tuomo Jaakola, Janne Aikio, Kari Ronka)

COFFEE BREAK IN SALON FOYER: 9:40 AM - 10:00 AM

IMAPS Cafés sponsored by:

LORD - IMAPS Cafe Sponsor

10:00 AM -
10:25 AM

Application of Low-K Liner for Stress and Capacitance Control in Cu-TSV
Chuan Seng Tan, Nanyang Technological University (Lin Zhang, Hongyu Li, WooSik Yoo)

LORD SolderBraceTM for improved reliability and throughput in WLCSP
George Sears, LORD Corporation

Copper Wirebond Compatibility with Organic and Inorganic Ions Present in Mold Compounds
Varughese Mathew, Freescale Semiconductor, Inc. (Sheila Chopin, Leo Higgins, Yingrui Zhang)

Thermal Cycling Reliability of Alternative Low-Silver Tin-based Solders
Elviz George, CALCE, University of Maryland (Michael Osterman, Michael Pecht, Richard Coyle, Richard Parker, Elizabeth Benedetto)

Non-hermetic Micropackage for Chronic Implantable MEMS Systems.
Wen H. Ko, Case Western Reserve Univerasity (Peng Wang, Shem Lachhman, Di Sun, and C. Zorman)

Excimer Laser Machining of Fired LTCC for Selectively Metalized Open Micro-channel Structures 
Dilshani Rathnayake-Arachchige, Loughborough University (Paul Conway, David Hutt)

10:25 AM -
10:50 AM

Electrografted insulator layer as copper diffusion barrier for TSV interposers
Vincent Mevellec, Alchimer (F. Raynal, D. Suhr, T. Dequivre, L. Religieux)

Moisture and Hydrogen Release in Optoelectronics Hermetic Packages.
Marwan Albarghouti, Semtech (Nayla ElDahdah, Goran Perosevic, Swati Jain)

A non-TSV 1000+ IO Package on Package Solution for wide IO applications
Laura Mirkarimi, Invensas Corp (Rajesh Katkar, Ron Zhang, Rey Co, Zhijun Zhao)

Voiding and Reliability of Assembly of BGA with SAC and 57Bi42Sn1Ag Alloys
Ning-Cheng Lee, Indium Corporation (Yan Liu)

 

An Overview of Isotropic Conductive Adhesives Filled with Metal-coated Polymer Spheres
Hoang-Vu Nguyen, IMST, Vestfold University (Knut E. Aasmundtveit , IMST, Vestfold University; Helge Kristiansen, Conpart AS; Susanne Helland, Tore Helland, Mosaic Solutions AS)

10:50 AM -
11:15 AM

Analysis of Strain/Stress in Electroless Copper Films
Tobias Bernhard, Atotech Deutschland GmbH (Simon Bamberg, Frank Bruening, Ralf Bruening, Christoph Genzel, Laurence Gregoriades, Tanu Sharma)

 

 

Thermal Cycle Consideration in Applying Lead-Free TFBGA Simulation to a Design
Yi-Chuan Tsai, National Sun Yat-Sen University

 

A friction based approach for modeling wire bonding
Simon Althoff, University of Paderborn (Walter Sextro, Tobias Hemsel, Jan Neuhaus)


Tuesday, October 1, 2013 | Opening Ceremonies: Annual Business Meeting, Awards Ceremony, Keynote
11:00 AM - 5:00 PM: Exhibit Hall Opens (GRAND BALLROOM)
11:25 AM - 11:40 AM: Annual Business Meeting (JR. BALLROOM F)
11:40 AM - 12:00 PM: IMAPS Society Awards Ceremony (JR. BALLROOM F)

Daniel C. Hughes, Jr. Award: Sam Forman
William D. Ashman Award:
John Lau
John A. Wagnon, Jr., Technical Achievement Award:
Michael Osterman
IMAPS Fellow of the Society:
Jin Yu; Matt Nowak; Adam Schubring; Shi-Wei "Ricky" Lee
Outstanding Educator Award:
Douglas Hopkins
Sidney J. Stein International Award:
Nihal Sinnadurai; Delip "Doug" Bokil
Corporate Recognition Award:
Sikama International
President's Awards:
Colin Johnston; Rajen Chanchani; Peter Elenius

Outstanding Papers - IMAPS 2012:
Zach Cole, Arkansas Power Electronics International
Packaging of High Frequency, High Temperature Silicon Carbide (SiC) Multichip Power Module (MCPM) Bi-Directional Battery Chargers for Next Generation Hybrid Electric Vehicles

Yiliang Wu, Xerox Research Centre of Canada
Development of Silver Nanoparticle Ink for Printed Electronics

Best Paper - IMAPS 2012:
Thomas Brunschwiler, IBM Research
Formulation of percolating thermal underfills by hierarchical self-assembly of micro- and nanoparticles by centrifugal forces and capillary-bridging

Come say Thank You to those who contributed so much to IMAPS over many years.

 

12:00 PM - 12:45 PM | KEYNOTE: (JR. BALLROOM F)
Next Generation of Electronic Systems - Challenges and Solutions for System Integration Technologies

The use of micro-level integration technologies to manufacture high-end electronic systems has increased dramatically around the world, the potential for applications being almost unlimited. To enable a smart planet, driven partly by the internet of things, next generation of electronic systems are expected to be more energy efficient, highly miniaturized and multifunctional with embedded computing, communication and sensing functionalities. In order to achieve this goal, novel heterogeneous system integration technologies and design methodologies are needed.

In this talk, some of the key system integration technologies required for the development of next generation electronic systems will be discussed. The focus will be on 3D wafer level packaging, panel level packaging and on interposer technologies. An overview of innovative electrical, thermal and thermo-mechanical design approaches will also be given.

 

Keynote: Klaus-Dieter Lang

Prof. Dr. -Ing. Dr. sc. techn. Klaus-Dieter Lang - Klaus-Dieter Lang is a Professor with the School of Electrical Engineering and Computer Sciences at the Technical University Berlin, Germany, where he leads research activities in the area of Nano Interconnect Technologies. He is also the Director of the Fraunhofer Institute for Reliability and Microintegration, IZM, Berlin.

Professor Lang began his career as a Research Engineer at Humboldt University Berlin, where he spent 10 years (1981 to 1991) working in the areas of Microelectronic Assembly, Packaging and Quality Assurance. In 1991, he moved to SLV Hannover to build up a Department for Microelectronic and Optic Components Manufacturing. He joined Fraunhofer IZM 20 years ago and was initially responsible for R&D activities in the area of Chip Interconnection Technologies. From 2001 to 2005 he coordinated Fraunhofer IZM's Lab on Microsystem Engineering in Berlin-Adlershof, and from 2003 to 2005 he was the Head of the Department of Photonic and Power System Assembly. In 2006, he was appointed as the Deputy Director of Fraunhofer IZM, a position he held till 2010. Since 2011 he has been the Director of the Institute.

Professor Lang Chairs the German Chapter of IEEE-CPMT and he is a member of numerous scientific boards and conference committees. He is the author and co-author of 3 books and more than 130 publications in the field of Wire Bonding Technologies, Microelectronic Packaging, Microsystems Technologies and Chip-on-Board Technologies. He studied Electrical Engineering at the Humboldt University Berlin, and holds a Master's degree and two Doctorate degrees.

 

12:45 PM - 2:00 PM: Lunch Break  (Food not provided by IMAPS Today)


Tuesday, October 1 | 1:30pm - 4:30pm in the Exhibit Hall (GRAND BALLROOM)
Student/University Poster Session
Chairs: Venky Sundaram, Georgia Tech University; Tom Weller, University of South Florida; Ege Engin, San Diego State University; Mike Newton, Newton Cyberfacturing
One-on-One Interactive Forum. This is your chance for detailed interaction with student authors whose work is too good to miss.

Self-packaged High-Temperature Sensors for Harsh-Environment Applications
Haitao Cheng, University of Central Florida (Xinhua Ren, Siamak Ebadi, Yaohan Chen, Linan An, Xun Gong)

The Path Forward: Silicon Optical Modulator for CMOS ICs
Kaikai Xu, University of California, Irvine

Non-contact microwave characterization of printed resistors
Maria F. Cordoba-Erazo, University of South Florida (Thomas M. Weller)

Through Silicon Via (TSV) Arrays for High Frequency Signal Transmission in 3D Integrated Circuits
Min Xu, CNSE, University at Albany (Robert Geer, University at Albany; Pavel Kabos, Thomas Wallis, NIST)

Silver Oxalate: Towards a New Solder Material for Highly Dissipative Electronic Assemblies
K. Kiryukhina, CNES (H. Le Trong, P. Tailhades, J. Lacaze, F. Courtade, S. Dareys, O. Vendier, L. Raynaud)

Study of Wirebonding on Thin Al Pads with Various Size Probe Marks
Shashi Sharma, Brigham Young University (Stevan Hunter, ON Semiconductor; Andrew Forhan, University of Colorado;  Prakash Subedi, Dustin Whittaker, Brigham Young University)

Design for Solder Joint Fatigue Life of BGA Package Subject to Mechanical Environment
Jia-Shen Lan, National Sun Yat-sen University (Mei-Ling Wu)

Excimer Laser Machining of Fired LTCC for Selectively Metalized Open Micro-channel Structures 
Dilshani Rathnayake-Arachchige, Loughborough University (Paul Conway, David Hutt)

Reliabilities and Strength of Al 718 For Thermoelectric Generator Assembly
Victor Wolemiwa, University of Idaho (Dominic Nwoke)

Modeling of Failure in Aluminum Alloy Braze for a High Temperature Thermoelectric Assembly
Shams Arifeen, University of Idaho (Gabriel Potirniche, Aicha Elshabini, Fred Barlow)

Modeling and Reliability Analysis of TSVs for High Frequency Applications
Kaushal Kannan, City College of New York (Sukeshwar Kannan, Bruce Kim)

Droplet-on-Demand Inkjet-filled TSVs as a Pathway to Cost-efficient Chip Stacking
Jacob Sadie, University of California, Berkeley (Niels Quack, Ming Wu, Vivek Subramanian)

Thermal Cycle Consideration in Applying Lead-Free TFBGA Simulation to a Design
Yi-Chuan Tsai, National Sun Yat-Sen University

Effect of ENEPIG Surface Finish on the Vibration Reliability of Solder Interconnects
Sandeep Menon, CALCE, University of Maryland (Adam Pearl, Michael Osterman, Michael Pecht)

Thermal Cycling Reliability of Alternative Low-Silver Tin-based Solders
Elviz George, CALCE, University of Maryland (Michael Osterman, Michael Pecht, Richard Coyle, Richard Parker, Elizabeth Benedetto)

Conceptual Development Using 3D Printing Technologies for 8kV SiC Power Module Package
Haotao Ke, North Carolina State University (Douglas Hopkins)

A Switched-Line Microwave Phase Shifter Fabricated with Additive Manufacturing
Jonathan O'Brien, University of South Florida (Mike Newton, Thomas Weller, Daniel Silva, Eduardo Rojas)

Chip Design of an 1 V RF Receiver Front-End for 5.8-GHz DSRC Applications
Wen Cheng Lai, National Taiwan University of Science and Technology (Jhin-Fang Huang, Yong-Jhen Jiangn)

Stitch Bond Process of Pd-Coated Cu Wire: Experimental and Numerical Studies of Process Parameters and Materials
Alireza Rezvani, University of Waterloo (Michael Mayer, Ivy Qin, Jon Brunner)

 

Schedule

INTERPOSERS & 2.5/3D PACKAGING

(SALON ROOM 3)

MODELING, DESIGN, TEST & REL

(SALON ROOM 5)

MATERIALS & PROCESSES

(SALON ROOM 1)

ADVANCED PACKAGING & ASSEMBLY

(SALON ROOM 6)

ADVANCED & EMERGING TECHNOLOGIES

(SALON ROOM 2)

SPECIAL SESSIONS ON PACKAGING & SYSTEM-INTEGRATION

(SALON ROOM 4)

Tuesday, October 1, 2013

2:00 PM -
6:35 PM

Advanced Platform Integration
Chairs: Vidhya Ramachandran, Qualcomm; Kyu-oh Lee, Intel

This session addresses diverse platform integration schemes using 2.5 and 3D technologies. The papers address effective methodologies for design to electrical characterization with product applications as final target. Technology engineers and product managers will benefit from the breadth of technologies covered in the papers.

Modeling and Design for SI and Reliability
Chairs: Chris Pan, Qualcomm; Judy Priest, Cisco

Advanced modeling and simulation techniques are used to analyze and optimize electrical performance and reliability in silicon, substrates, packages, and L1/L2 assembly. Some measurement correlation may be discussed, along with printed circuit board effects.

Polymers, Underfill, Encapsulants and Adhesives
Chairs: Jeff Gotro,Innocentrix; Lyndon Larson, Dow Corning

In this session, we focus on some of the advances from the polymeric materials side; introducing novel adhesives, flux, and underfill technologies for use in a wide range of applications including molding, SMT, 2.5D and 3D assembly processes.

Wirebonding & Stud Bumping
Chairs: Dan Evans, Palomar Technologies; Lee Levine, Process Solutions Consulting

This session covers non-destructive testing challenges and methods of wires and bond pads, Pd-Coated Copper wire process window optimization, Copper wedge bonding, Al and Silver based wires as alternatives to copper, plus hybrid wire bond capabilities.

Emerging Technologies
Chairs: Susan Bagen, Endicott Interconnect; Igor Prikhodko, Analog Devices

In this session, novel structural materials will be introduced in conjunction with emerging applications. Specifically, applications in nanotechnology, MEMS sensors, counterfeit technologies, high-density data storages will be presented. Engineers will find this session helpful to explore alternative design choices for selecting technologies and materials for next generation products.

Asian Perspective on Electronic Packaging and System Integration
Chairs: Tae-Kyu Lee, Cisco; Woongsun Lee, SK Hynix

This special session covers the Asian perspective on electronic packaging. 3D, new material and process, and MCP, variety of packagaes are discussed in this session and distinguished speakers will present leading edge technologies of electronic packaging in Asia.

2:00 PM - 2:25 PM

Enabling a Manufacturable 3D Technologies and Ecosystem Using 28nm FPGA with Stack Silicon Interconnect Technology
Woon-Seong, Kwon, Xilinx (Myongseob Kim, Jonathan Chang, Suresh Ramalingam, Liam Madden, Xilinx; Genie Tsai, Stephen Tseng, J.Y. Lai, Terren Lu, Steve Chiu, SPIL)

Flip-Chip Packages with Periphery Cu Pillar Bumps as Wirebond Replacement - Design, Modeling & Characterization
Zhe Li, Altera Corporation (Yee Huan Yew, Siow Chek Tan, Hui Lee Teng)

A Novel High Thermal Conductive Underfill for Flip Chip Application
Wusheng Yin, YINCAE Advanced Materials, LLC (Mary Liu)

Non-Destructive Top Layer Bond Pad Cross Section
Terence Collier, CVInc (Indira Gubeljic)

DNA Marking:
Implementation of a Proactive Counterfeit Risk Mitigation Solution

Janice Meraglia, Applied DNA Sciences

FEATURED SPEAKER
Thin-Wafer Handling (with a Heat-Spreader Wafer) for 3D IC Integration
John Lau, ITRI (Chun-Hsien Chien, Hsiang-Hung Chang, Wen-Li Tsai)

2:25 PM - 2:50 PM

DIMM-in-a-Package (DIAP) Signal Integrity for High-Performance On-Board Memory Applications
Zhuowen Sun, Invensas (Kevin Chen, Richard Crisp)

Package Technology Selection of 28nm High Power FPGA with Pb-Free Bumps: Flip Chip Molded BGA Versus Traditional Bare Die Package
Corey Reichman, Amkor Technology (Intel Corp - Michael Lyakas, Aaron Elberg, Romina Mimi Ocampo, Altaf Hasan, DierdreHale & Amkor - Miguel Jimarez, Fred Hamilton, Joon Dong Kim)

An overview of molded underfill in flip chip packaging applications
Fernando Roa, Amkor Technology

Stitch Bond Process of Pd-Coated Cu Wire: Experimental and Numerical Studies of Process Parameters and Materials
Alireza Rezvani, University of Waterloo (Michael Mayer, Ivy Qin, Jon Brunner)

Transferable Redistribution Layers (TRDL)
David Herndon, Harris Corporation (Suzanne Dunphy, Thomas Reed)

Electroless Ni Plating Solutions for Reproducible Black Pad Analyses
Jin Yu, Korea Advanced Institute of Science and Technology (KAIST) (K.H. Kim , Carnegie Mellon University)

2:50 PM - 3:15 PM

High Speed Signal Transmission using Through-Si Vias and Coplanar Waveguides in a 3D IC Test Structure
Min Xu, CNSE, University at Albany (Robert Geer, University at Albany; Pavel Kabos, Thomas Wallis, NIST)

Modeling and Reliability Analysis of TSVs for High Frequency Applications
Kaushal Kannan, City College of New York (Sukeshwar Kannan, Bruce Kim)

Packaging Materials for 2.5/3D Technology
Brian Schmaltz, NAMICS Corporation

Cu Heavy Wirebonding for High Power Device Interconnection
Baik-Woo Lee, Samsung Advanced Institute of Technology

CANCELLED BY AUTHOR

Implementing Inductor Function with Vibrating Capacitor Structures
Thomas Marinis, Draper Laboratory (Joseph Soucy

Scaling Challenges of Semiconductor Packaging in the Era of Big Data
Yasumitsu Orii, IBM Research Tokyo

DESSERT "HAPPY HOUR" &
COFFEE BREAK IN EXHIBIT HALL (GRAND BALLROOM): 3:15 PM - 4:30 PM

IMAPS Cafés sponsored by:
LORD - IMAPS Cafe Sponsor
Dessert "Happy Hour" Sponsor:
Palomar Technologies:  Dessert Station Sponsor

 

4:30 PM - 4:55 PM

Electrical Characterization of TSVs with Varying Process Knobs and Temporary Bond/Adhesive System Robustness Studies for 2.5D/3D Manufacturing
Niranjan Kumar, Applied Materials (Sesh Ramaswami, Arvind Sundarrajan, CH Toh, Aksel Kitowski, Anthony C-T Chan, David Erickson, Jay Vijayen, Minrui Yu, Uday Mahajan)

Design for Solder Joint Fatigue Life of BGA Package Subject to Mechanical Environment
Jia-Shen Lan, National Sun Yat-sen University (Mei-Ling Wu)

Solder Joint Encapsulant Adhesive - LGA High Reliability And Low Cost Assembly Solution
Wusheng Yin, YINCAE Advanced Materials, LLC (Mary Liu)

Multipurpose Wire Bonding - Bumps, Wires, Combination Interconnects, and Operation Efficiency
Daniel Evans, Palomar Technologies (David Rasmussen)

Embedded Photonics Interconnect Eco-system for Data Center Applications
Richard Pitwon, Xyratex Technology Ltd (Alex Worrall, Kai Wang)

High Thermal Conductive Inter Chip Fill for 3D-IC through Pre-applied Joining Process
Yasuhiro Kawase, Mitsubishi Chemical Corporation (Ikemoto, M. Sugiyama, M.Yamazaki, H. Kiritani, F. Mizutani, K. Matsumoto, A. Horibe, H.Mori, Y.Orii)

4:55 PM - 5:20 PM

Polymer Based Interposer Providing ESD and Thermal Robustness
Karen Shrier, Electronic Polymers Newco Inc.

Warpage Characterization and Improvements for IC Packages with Coreless Substrate
Bora Baloglu , Amkor Technology (Wei Lin, Danny Brady, Ken Stratton, Miguel Jimarez)

Adhesion and Cure Mechanism Studies for
Advanced Lidded Flipchip Applications

Larson, Lyndon, Dow Corning Corporation (Kristen Steinbrecher, James Tonge)

Automated Wirebond Pull Testing - Parallelogram of Forces-Real time Application
Richard C. Garcia, Crane Aerospace (Josef Sedlmair, F&K Delvotec)

Decision Making Model for the Emerging Nanotechnologies
Kewal Verma, BCA International (Audre Dixon)

Development of Organic Multi Chip Package for High Performance Application
Noriyoshi Shimizu, Shinko Electric Industries Co., LTD.

5:20 PM - 5:45 PM

 

 

 

Thick Copper and Aluminium Wire Bonding Technology for High Power Laser Devices
Kong Weng Lee, JDS Uniphase (Jay Skidmore, Lei Xu)

Ultra-Thin Zirconia Ceramic Membranes for Electronic Applications
John Olenick, ENrG, Inc.

Thermally Activated Bumping Process of Sn3.0Ag0.5Cu Solder for Low-Cost Interposer
Kwang-Seong Choi, ETRI (Haksun Lee, Hyun-Cheol Bae, Yong-Sung Eom)

5:45 PM - 6:10 PM

 

 

 

Study of Wirebonding on Thin Al Pads with Various Size Probe Marks
Shashi Sharma, Brigham Young University (Stevan Hunter, ON Semiconductor; Andrew Forhan, University of Colorado; Prakash Subedi, Dustin Whittaker, Brigham Young University)

A Study on Prevalent Factors Behind Efficiency Deterioration of a Typical Low Power Solar Panel
Virgil Ganescu, Education Affiliates

Low Temperature Si-Si, SiO2-SiO2 Covalent Bonding with Thin Siloxane Layer
Jeong-Yub Lee, Samsung Advanced Institute of Technology

6:10 PM - 6:35 PM

 

 

 

High Speed Aluminum Wirebonding for Molded Packages
Luu Nguyen, Texas Instruments Inc.

CANCELLED BY AUTHOR

 

 

 

Schedule

INTERPOSERS & 2.5/3D PACKAGING

(SALON ROOM 3)

MODELING, DESIGN, TEST & REL

(SALON ROOM 5)

MATERIALS & PROCESSES

(SALON ROOM 1)

ADVANCED PACKAGING & ASSEMBLY

(SALON ROOM 6)

ADVANCED & EMERGING TECHNOLOGIES

(SALON ROOM 2)

SPECIAL SESSIONS ON PACKAGING & SYSTEM-INTEGRATION

(SALON ROOM 4)

Wednesday, October 2, 2013

8:00 AM -
11:15 AM

 

Packaging Transitions: 2.5D and 3D Interconnect Technologies from Wire Bond to RDL to TSV Chairs: Cristina Chu, TEL NEXX; Greg Caswell, DfR Solutions

The transition from packaging today as we know it to true 3D interconnects involves many hybrid solutions as the industry inches towards TSVs. This session will focus on creative implementations of packaging to efficiently push the boundaries of RDLs, bumping and interposers, among other applications, to cost effectively address the challenges delivering the greatest electronic efficiency at the lowest prices.
Thermal and Thermo-Mechanical Modeling
Chairs: David Saums, DS&A LLC; Mary Cristina Ruales Ortega, University System Ana G. Mendez

This session focuses on thermal and thermo-mechanical modeling. A variety of topics will highlight recent advances within these areas.
Substrate Materials I
Chairs: Michael Folk, Northrop Grumman Corp.; Jeff Hartman, Northrop Grumman Corp.

Improved substrates and associated processes are required to improve performance, reliability and lower cost of ownership. In this session the properties and processes for advancing substrates will be presented.
Flip Chip Bumping
Chairs: Andy Strandjord, Pac Tech USA; Nick Renaud-Bezot, AT&S

Solder bumping is a reliable interconnect technology that is directly compatible with many of the latest semiconductor technologies, including: 2D, 3D, organic packages, and ultra thin packages. Continued reliability testing, process development, and materials development are essential to ensure that solder bumping is a long-term interconnect solution as these new semiconductor technologies evolve.
New Concepts, Interconnects & Processes for High Performance Packaging
Chairs: Benson Chan, Endicott Interconnect; Ron Lasky, Indium Corporation

In this session, novel concepts, interconnects and processes for next high performance packaging will be presented.
Power Packaging I
Chairs: Mark Hoffmeyer, IBM Corporation; Doug Hopkins, North Carolina State University

This session focuses predominantly on power packaging systems, electrical design, modeling, and the deployment of advanced power packaging applications.

8:00 AM - 8:25 AM

Cost Comparison of 2.5D/3D Packaging to other Packaging Technologies
Chet Palesko, SavanSys Solutions LLC (E. Jan Vardaman, TechSearch International, Inc.; Alan Palesko, SavanSys Solutions LLC)
Interactions between Variable Frequency Microwave Underfill Processing and High Performance Packaging Materials
Mamadou Diobet Diop, Universite de Sherbrooke (Dominique Drouin, Universite de Sherbrookek; Marie-Claude Paquet, IBM Canada)
Effects of Copper Pattern Density and Orientation on the Modulus of BGA Substrates
Burton Carpenter, Freescale Semiconductor, Inc (Betty Yeung, Freescale Semiconductor, Inc; Yuan Yuan)
Development of an Ultra Thin Die-to-Wafer Flip Chip Stacking Process for 2.5D Integration
Gabriel Pares, CEA-Leti (A. Attard, F. Dosseul, G. Klug, G. Simon)
Si Vapor Chamber Integrated with Through Silicon Via for 3D Packaging
Jun Taniguchi, Fujitsu Laboratories LTD. (Takeshi Shioga,Yoshihiro Mizuno)
8:25 AM - 8:50 AM
Redistribution Layers (RDLs) for 3D IC Integration
John Lau, ITRI (Pei-Jer Tzeng, Ching-Kuan Lee)
Heatsink Induced Thermo-mechanical Strain in QFN Devices
Gerard McVicker, IBM Research (Vijay Khanna, Sri M. Sri-Jayantha)
A photo-desmear method for via residue removal using a VUV light source
Tomoyuki Habu, Ushio Inc. (Shintaro Yabu, Kenichi Hirose, Hiroki Horibe, Ushio, Inc.; Toru Fujinami, Ushio America; Naoki Kitano, Eiji Ozawa, Intel K.K.; Sanchali Bhattacharjee, Ebrahim Andideh, Daniel Sobieski, Intel Corp.)

Long-term Electromigration Study of Lead-Free Flip-Chips with Solder Bumps with 50 µm or 60 µm Diameter Employing ENIG Surface Finish on Both Chip and Substrate Side
Marek Gorywoda, University of Applied Sciences Hof (Rainer Dohle, Andreas Wirth, Jörg Goßler, Micro Systems Engineering GmbH; Stefan Härter, Jörg Franke, University of Erlangen-Nuremberg)

Inspection and Metrology Solutions for Cu Pillar and TSV High-Volume Manufacturing
Rajiv Roy, Rudolph Technologies (Matt Wilson, Darren James)
8:50 AM - 9:15 AM
A Wide I/O Memory-on-Logic Product Prototype Enabled by Through Silicon Stacking Technology
V. Ramachandran, Qualcomm Technologies, Inc. (D. W. Kim, S. Gu, R. Lindley, B. Henderson, U. Ray, R. Radojcic, M. Nowak, A. Gunterus, A. Cassier, Qualcomm Technologies, Inc.; Sharon Chen, M.F. Chen, C.H. Wu, S.P.Jeng, C.H. Yu, Taiwan Semiconductor Manufacturing Company, Ltd.)

Fatigue Life Analysis of Sn96.5Ag3.0Cu0.5 Solder Thermal Interface Material of a Chip-Heat Sink Assembly in Microelectronic Applications
Mathias Ekpu, University of Greenwich

CANCELLED BY AUTHOR

Method to Measure the Effects on Surface Roughness on the High Frequency Transmission Line
Toshiki Iwai, Fujitsu Laboratories Ltd. (Daisuke Mizutani, Motoaki Tani)

3D Integration of System-in-Package (SiP) Using Organic Interposers: Toward SiP-Interposer-SiP for High-End Electronics
Rabindra Das, Endicott Interconnect Technologies, Inc. (Frank Egitto, Steven Rosser, Erich Kopp, Barry Bonitz)

Multi Beam Low-K Grooving Evaluation of Various Removal Principals
Lonny Plummer, Advanced Laser Separation International (ALSI) N.V. (Jeroen van Borkulo, Henry de Jonge)

COFFEE BREAK IN EXHIBIT HALL (GRAND BALLROOM): 9:15 AM - 10:00 AM
(Exhibit Hall Open (GRAND BALLROOM): 9:00 AM - 7:30 PM)

IMAPS Cafés sponsored by:
LORD - IMAPS Cafe Sponsor

10:00 AM - 10:25 AM
3D RCP Package Stacking: Side Connect, An Emerging Technology for System Integration and Volumetric Efficiency
Michael Vincent, Freescale Semiconductor, Inc. (Doug Mitchell, Jason Wright, Alan Magnus, WengFoong Yap, Jinbang Tang, Scott Hayes)

Thermally and Electrically Enhanced Wirebond BGA
Burton Carpenter, Freescale Semiconductor, Inc (Boon Yew Low, Leo Higgins III, Sriram Neelakantan, Robert Wenzel, Daniel Boyne)

Organic Chip Scale Package (CSP) Development for Flip Chip Applications
Tomoyuki Yamada, Kyocera SLC Technologies (Masahiro Fukui, Kenji Terada, Masaaki Harazono, Teruya Fijisaki, Kyocera SLC Technologies ; Tomoyuki
Yamada, Kyocera; Jean Audet,
Sushumna Iruvanti, Yi Pan, Scott Moore, Brian Sundlof, Charlie Reynolds, IBM Corporation)
Stencil Printing Process Guidelines for 0.3mm Pitch Chip Scale Packages
Mark Whitmore, DEK Printing Machines Ltd (Jeff Schake, Clive Ashmore)
Advanced Thermal Simulation Model for Power MOSFETs
Jens Ejury, Infineon Technologies N.A. Corp
10:25 AM - 10:50 AM
3D Integrated Packaging Approach for High Performance Processor-Memory Module
Stephen Polzer, Mayo Clinic (W. L. Wilkins, J. L. Fasig, M. J. Degerstrom, B. K. Gilbert, E. S. Daniel)
Accurate Finite Element Analysis of Embedded Wafer Level Packaging by Thermomechanical Characterization of Materials and ICs Piezoresistive Stress Sensors
Sinh Vuhoang, Ecole Nationale Superieure des Mines de Saint-Eienne (ENSM-SE) (J.Mazuir, M.Bella, C.Bouvier, G.Pares, K.Martinschitz, H.Wiesbauer, C.Rivero, A. Planchais, M. Saadaoui)
RF Capacitor Material for Use in PCBs
Jin-Hyun Hwang, Oak-Mitsui Technologies, LLC (John Andresakis, Ethan Feinberg, Bob Carter, Yuji Kageyama, Fujio Kuwako)

Improving WLCSP Reliability Through Solder Joint Geometry Optimization
Boyd Rogers, Deca Technologies (Chris Scanlan)

Z-Axis Interconnection: A Versatile Technology Solution for High Performance Electronics
Rabindra Das, Endicott Interconnect Technologies, Inc. (J. M. Lauffer, F.D. Egitto)
A Highly Integrated GaAs-based Module for DC-DC Regulators
Greg J. Miller, Sarda Technologies (Bogdan Duduman, Bill Batchelor)
10:50 AM - 11:15 AM
Next-Generation Lead-Free Solder Plating Products for High Speed Bumping, Capping and Micro-Capping Applications
Jonathan Prange, The Dow Chemical Company (Julia Woertink, Yi Qin, Pedro Lopez Montesinos, Inho Lee, Yil-Hak Lee, Masaaki Imanari, Jianwei Dong, Jeff Calvert)
Evaluation of Thermal Performance for a New Ventilated Heat Sink Module
Shiang-Jiun Lin, National Kaohsiung University of Applied Sciences (Yen-Wei Chen)
Characterization of CVD Diamond for Thermal Management Applications
Brooke Locklin, Element Six (Richard Balmer, Thomas Obeloer)
Isothermal Fatigue Tests of Sn63-Pb37,Sn62-Pb36-Ag2 and Sn42-Bi58 Solder Joints
Eliane M Grigoletto, UNISAL College (Itamar Ferreira)

 

 

 

11:20 AM - 12:05 PM | KEYNOTE: (JR. BALLROOM F)
Progress in Developing an Open Supply Chain for 2.5D/3D Market Enablement

An open supply chain requires close collaboration, early investment, and focus on the ultimate goal of yield and cost to enable markets. An open supply chain is more complex to develop but will provide the end-customer with the most flexibility and transparency and enables use of expertise in each stage of the supply chain. An open supply chain also requires high levels of sharing, not typical in our industry. Significant progress has been made in test chip development, TSVs, interposers, test strategy, yield, and cost. Data and remaining challenges will be presented in each of these areas. The relationship between memory architecture and cost will also be discussed.

 

Keynote: David McCann

David McCann is Vice President of Packaging at GLOBALFOUNDRIES in Malta, New York. In this role, David is responsible for Packaging R+D, interconnect development, and back-end strategy and implementation. David started at GLOBALFOUNDRIES in 2011.

Prior to GLOBALFOUNDRIES, David worked at Amkor Technology for 11 years, in product group and development roles. He also led cross-functional teams including networking product strategy and mobile product development.

David has supported the Electronic Component and Technology Conference for more than 10 years. He was General Chair in 2012.

David McCann received his Masters in Engineering Management from the Santa Clara University in 1985 and his BS in Ceramic Engineering from the University of Illinois in 1981.


12:15 PM - 1:30 PM: Lunch in Exhibit Hall (GRAND BALLROOM)
(Lunch Provided by IMAPS & Sponsors)
 

Exhibit Hall Lunch sponsored by:
Applied Materials: Exhibit Hall Lunch & Reception

 

Wednesday, October 2, 2013 - (JR BALLROOM G)
GLOBAL BUSINESS COUNCIL (GBC) Keynote Luncheon & Market Forecasting Analyst Session

Complimentary for all to attend, thanks to our Sponsor: Sikama
Limited Seating - 75 Seats Available
(first come first served - email bschieman@imaps.org to reserve your seat)

12:30 PM: Welcome Message, GBC Objectives and Agenda Review - Lee Smith, Plexus Corp.

GBC Lunch Sponsored by:

Sikama - GBC Sponsor

12:40 PM - 1:00 PM: GBC Luncheon & Keynote Speaker: The Microelectronics Industry in Brazil
Claudius Feger, IBM Research - Brazil
feger@us.ibm.com

As Brazil's middle class has increased by 35 million people, electronics imports have skyrocketed - resulting in a narrowing of Brazil's trade balance, which in January 2013 turned negative. To address this trend, the Brazilian government made the development of a local microelectronics industry an economic priority. Previously, the government focused on developing IC design skills and the creation of design houses, of which 22 were established to-date. However, the success of these has been limited, mostly because of difficulties in attracting industrial projects and thus over half of the existing design houses are not for profit.

With the announcement in late in 2012 of the creation of SIX Semicondutores, an IDM which once completed, will be the most advanced, commercial chip manufacturer in Latin America, the Brazilian microelectronics industry started a new chapter. SIX Semi will be using IBM 130 and 90 nm technology to provide advanced mixed signal / hybrid semiconductor devices and products for the medical devices, smart card, sensor, energy management and similar markets. In doing so, Brazil hopes to start making a dent in the import of about US$4 - 5 billion annual imports of ICs.

Another focus area is electronic packaging. But even after the announcement in 2012 of HT Micron, (a joint venture between the Brazilian Altus and the Korean Hana Micron), this area will remain poorly served in Brazil, because HT Micron will focus exclusively on the highly competitive memory packaging segment.

Over the years the Brazilian government has instituted several laws and regulations to support the formation of an electronics industry with Brazilian content. This spans efforts from creating academic programs and research institutions to laws requiring industrial research investments to direct investments by the Brazilian development bank in industries. However many hurdles remain.

This talk will describe successes and hurdles in the development of a successful microelectronics ecosystem in Brazil and will provide an up-to-date picture of this important emerging market.

1:00 PM - 2:00 PM: Industry Analyst & Panel Discussion
"Addressing Major Changes in the Supply and Demand for Advanced Packaging Technologies"

1:00 PM - 1:20PM: "Demand Outlook for 2.5 / 3D and Wafer Level Packaging"
Yole Developpment - Christophe Fitamant, Sales and Marketing Director

Wafer level packaging market is started to gain more and more significance in the semiconductor industry, showing a great potential for future growth. By 2017, the total number of wafers which will be manufactured using packaging technologies (bumping, TSV, RDL, etc.) is expected to reach 23% of the total IC semiconductor industry.

If historically, the wafer level packaging was mostly supported by flip-chip wafer bumping using electroplated gold and solder bumps, today the industry is benefiting from a large variety of different packaging technologies and platforms: WL Optics, 3D WLP, WLCSP (fan-in), Fan-out WLP, Embedded Dies, 2.5D and 3DIC and Flip Chip.

It is a real opportunity for the entire supply chain to work together and further consolidate and strengthen the system value-chain in order to fully take advantage of the benefits and advantages these packaging technologies bring.

In this talk, Yole Développement will look at the current status of the 3D Packaging industry, provide technical trends for 2.5 & 3D, Fan-In and Fan Out, Embedded Chip in Substrate packaging technologies as well as discuss further trends and forecasts projections for the next 5 years, highlighting the driving applications and their expected evolution.

1:20 PM - 1:40 PM: "Supply Chain Implications for Advanced Packaging"
Gartner Dataquest - Mark Stromberg, Senior Director

Advanced packaging markets have been the major driver for back-end processing in recent years. Several device makers have stated that between the 30 and 20nm nodes essentially all their products will move to flip-chip and wafer-level type processes. This has, and will continue to, introduce new materials, production processes and equipment into the packaging space.

While advanced packaging has been a major growth segment, there are some competitive processes, particularly for the 3D Through Silicon Via (TSV) market that have shown some promise. TSV has been discussed as a major industry initiative for more than 5 years, but has yet to launch into mainstream markets and has been limited to very high end final electronic products such a file servers. Reasons for this include production costs and device yield concerns.

This discussion will be focused on the forecasts for bumping processes and 3D technologies. Technical, yield and cost issues for these advanced processes will also be presented. Gartner's most recent forecast for WLP equipment markets will be included in this presentation. Forecasts for the general packaging and test, WLP and TSV markets are also going to be reviewed during this talk.

1:40 PM - 2:00 PM: Panel Format with Audience Questions & Answers
Moderator - Lee Smith


Schedule

INTERPOSERS & 2.5/3D PACKAGING

(SALON ROOM 3)

MODELING, DESIGN, TEST & REL

(SALON ROOM 5)

MATERIALS & PROCESSES

(SALON ROOM 1)

ADVANCED PACKAGING & ASSEMBLY

(SALON ROOM 6)

ADVANCED & EMERGING TECHNOLOGIES

(SALON ROOM 2)

SPECIAL SESSIONS ON PACKAGING & SYSTEM-INTEGRATION

(SALON ROOM 4)

Wednesday, October 2, 2013

2:00 PM -
6:05 PM

Glass Interposers
Chairs: Steve Annas, Triton Micro Tech; Aric Shorey, Corning Inc.

As we rapidly increase requirements on packaging & interconnect performance, we approach the limits of today's technology, thus the need increases for a greater number of components in smaller packages using Silicon and Glass (TGV) emerging as the need for 2.5D & 3D passive Interposers grow to better support this next generation assembly.

Testing Methods and Process for Improved Reliability
Chairs: Mike Ferrara, RF Micro Devices; Akhlaq Rahman, Thin Film Corp.

In this session, novel characterization methods will be introduced as well as unique approaches to new material sets providing improved reliability.
Substrate Materials II (Ceramic & LTCC)
Chairs: Dan Krueger, Honeywell FM&T; Ken Peterson, Sandia National Labs.

New and evolving applications, designs, and characterization of ceramic and low temperature cofired ceramic (LTCC) packaging solutions are provided in this session. Radio Frequency (RF), microfluidics, high power applications are all explored in this diverse session exploring the versatility of ceramic and LTCC substrate systems.
MEMS & Sensor Packaging
Chairs: Matt Apanius, SMART Commercialization Center for Microsystems; Ron Jensen, Honeywell

Packaging plays a critical role in the robustness associated with MEMS and sensor performance. As the applications tend to be quite varied, the interfaces between the sensor, package, electronics, and media need to be well-defined. Unique solutions for MEMS and sensor packaging interfaces will be presented in this session.
Think Thin: Thin IC Packaging For Mobile Devices
Chairs: Rich Rice, ASE; Jason Cho, ASE; Milind Shah, Qualcomm

The objective of the "Think Thin" session is to address the numerous aspects of making IC packages "thinner". This session enables discussion and presentations on the latest materials, process, design, and emerging applications of "thin" packaging technology.
Power Packaging II
Chairs: Julie Adams, UBOTIC Company Ltd.; Mark Hoffmeyer, IBM Corporation

This session includes an array of topics spanning new materials, process advances reliability, circuit design, and application user considerations for optimized, state of the art power packaging applications.
2:00 PM - 2:25 PM
Thermal Characteristic and Performance of the Glass Interposer with TGV (Through-Glass Via)
Heng-Chieh Chien, Industrial Technology Research Institute (Chun-Hsien Chien, Ming-Ji Dai, Ra-Min Tain, Wei-Chung Lo, Yung-Jean Rachel Lu)
Advanced Warpage Characterization for FOWLP
Isabel Barros, Nanium, SA (Mario Ribeiro)
Plating Reliability and High Frequency Testing of DuPont™ GreenTape™ 9K7 LTCC
Allan Beikmohamadi, DuPont (Mike Champ, Patricia Graddy, Beth Hughes, Deepukumar Nair, Jim Parisi, Mike Smith, Steve Stewart)
A Current-Controlled PCB Integrated MEMS Tilt Mirror
Robert Dean, Auburn University (Colin Stevens, John Tatarchuk)
Active and Passive Component Embedding Into Low-cost Plastic Substrates Aimed at Smart System Applications
Maarten Cauwe, IMEC-Cmst (Bjorn Vandecasteele, Johan De Baets, Jeroen van den Brand, Roel Kusters, Ashok Sridhar)
Electromigration in Pb-Free Solder: A Power IC Perspective
Tom Wassick, IBM Systems and Technology Group
2:25 PM - 2:50 PM
Performance and Process Comparison between Glass and
Si Interposer for 3D-IC Integration

Chun-Hsien Chien, Industrial Technology Research Institute (Ching-Kuan Lee, Chang-Chih Liu, Hsun Yu, Peng-Shu Chen, Heng-Chieh Chien, Ming-Ji Dai, Yu-Min Lin, Shin-Yi Huang, Chia-Wen Fan, Jon-Shiou Peng, Chau-Jie Zhan, Cheng-Ta Ko, Shih-Hsien Wu, Ra-Min Tain, Wei-Chung Lo, Yung Jean Rachel Lu)
Low Loss Power Distribution Network Design in Low Temperature Co-Fired Ceramic Technology
Michael D. Glover, University of Arkansas (Michael C. Hamilton,
Emmanuel Decrossas,
Kaoru Maner, Alexander Pfeiffenberger, H. Alan Mantooth)
High and Moderate-Level Vacuum Packaging of Vibratory MEMS
Igor Prikhodko, University of California, Irvine (Brenton Simon, Gunjana Sharma, Sergei Zotov, Alexander Trusov, Andrei Shkel)
Modular Microsystems with Embedded Components
Christian Boehme, Fraunhofer IZM / TUB (Andreas Ostmann, Martin Schneider-Ramelow)
Conceptual Development Using 3D Printing Technologies for 8kV SiC Power Module Package
Haotao Ke, North Carolina State University (Douglas Hopkins)
2:50 PM - 3:15 PM
Glass Interposer Substrates: Fabrication, Characterization and Modeling
Aric Shorey, Corning Incorporated (John Keech, Garrett Piech, Scott Pollard, Satish Chaparala)

The Effectiveness of Screening Techniques for Revealing Cracks in High Volumetric Efficiency MLCCs
Alexander Teverovsky, Dell Services Federal Government, Inc.
CANCELLED BY AUTHOR

Thick Film Pastes for Nitride Ceramics for High Power Applications
Marco Wenzel, Fraunhofer IKTS (Richard Schmidt, Uwe Partsch, Markus Eberstein)
Microfluidic Device Packaging
Leland Spangler, Aspen Microsystems
Size Matters - Embedding as an Enabler of Next-Generation SiPs
Nick Renaud-Bezot, AT&S (Mark Beesley, Christian Galler)
Improving System Performance with eGaN® FETs in DC-DC Applications
David Reusch, Efficient Power Conversion (EPC) (Alex Lidow, Johan Strydom)

COFFEE BREAK IN EXHIBIT HALL (GRAND BALLROOM): 3:15 PM - 4:00 PM

IMAPS Cafés sponsored by:
LORD - IMAPS Cafe Sponsor

4:00 PM - 4:25 PM
Development of TGV Interposer for 3D IC
Shintaro Takahashi, Asahi Glass Co., Ltd. (Kohei Horiuchi, Kentaro Tatsukoshi, Motoshi Ono, Masaki Mikayama, Nobuhiko Imajo, Vern Stygar, Tim Mobley)
Dicing Development for Low-K Copper Wafers using
Nickel-Palladium-Gold Bond Pads for Automotive Application

Burt Carpenter, Freescale Semiconductor, Inc. (Tu Anh Tran, Wen Shi Koh, K. Y. Yow, Y. K. Au)
Low-Temperature Co-fired Ceramic (LTCC) Technology for Development of Sensors for Emerging Applications
Hansu Birol, Centro de Inovacoes CSEM Brasil (Sergio Lopera, Warner Bernardes Quintao, Erika Gyoervary, James Buntaine, Tiago Alves)
Void Formation and Bond Strength Investigated for Wafer-level Cu-Sn SLID Bonding
Astrid-Sofie B. Vardoy, SINTEF ICT (H.J. van de Wiel, Stian Martinsen, Marcel Kouters, Greg Hayes, Hartmut Fischer, Knut Aasmundtveit, Adriana Lapadatu, Maaike Taklo)
Novel back-side grinding and laser dicing process for Cu pillar generated low-k wafer
Yuka Tamadate, Shinko (Hideki Maruyama, Katsunori Aoki, Takashi Ozawa, Haruo Sorimachi)
Source-sense packages for HV MOSFETs
Anders Lind, Infineon Technologies North America Corp. (Jens Ejury)
4:25 PM - 4:50 PM
Challenges of Adhesion Promotion for the Metallization of Glass Interposers
Robin Taylor, Atotech Deutschland GmbH (Simon Bamberg, Michael Merschy, Tobias Bernhard, Frank Bruening)
Immersion Tin for QFN-Packages to Create a 3-D Solder Joint for Reliability Enhancement
Mustafa Oezkoek, Atotech (Hubertus Mertens, Jerome Bender, Atotech Deutschland GmbH)
 
Mechanical Stress Analyses of Packaged Pressure Sensors for Very High Temperatures
Roderich Zeiser, University of Freiburg - IMTEK (Suleman Ayub, Juergen Wilde)
High Bandwidth PoP
Jason Cho, ASE (US), Inc. (Mike Hung, Morris Cheng, Timmy Lin, Calvin Lee)
Integrated Current Sensing Technology for Synchronous Buck Converters
Evan Reutzel, Texas Instruments Inc. (Scott Ragona, Rengang Chen, David Jauregui)
4:50 PM - 5:15 PM
 
 

Packaging CMUTs for Gesture Sensing
Luu Nguyen, Texas Instruments Inc.

CANCELLED BY AUTHOR

5:15 PM - 5:40 PM
 
Improvement of Back-Side Cosmetic Defects And Wafer Strength
Erwin Cohen, IBM SRDC (Victoria L. Calero-DdelC, Irene Popova, Richard Indyk, Joe Sullivan, John Fitzsimmons; Aaron Bicknell, Lam Research)
 
 
 
5:40 PM - 6:05 PM
 
 
 
 
Reducing Package Thickness to Accommodate Next Generation Smartphone Designs
Brian Roggeman, Qualcomm Technologies, Inc (Rajneesh Kumar, Mark Schwarz)
 

EXHIBIT HALL RECEPTION (GRAND BALLROOM): 5:30 PM - 7:30 PM

Exhibit Hall Reception sponsored by:
Micross Components: CORPORATE Sponsor
Exhibit Hall Reception sponsored by:
Applied Materials: Exhibit Hall Lunch & Reception

 

 


Thursday, October 3, 2013

Professional Development Courses (PDCs)
8:00 AM - 12:00PM
(SALON ROOMS, Rosen Centre Hotel, Orlando, Florida)


Schedule

INTERPOSERS & 2.5/3D PACKAGING

Thursday, October 3, 2013

8:00 AM -
12:00 PM

An entire morning of the conference dedicated to 2.5D &
3D IC, Interposers, Packaging...

(JR. BALLROOM F)

3D KEYNOTE PRESENTATIONS:

8:00 AM - 8:45 AM
Micron's Hybrid Memory Cube - the New Standard for Memory Performance

Yole Développement research analysts project a $40B market for TSV-enabled 3D devices by 2017 -- nearly 10% of the global chip business. These projections rely heavily on leading technologies such as the Hybrid Memory Cube (HMC) which represents a fundamental change in memory construction and connectivity.

HMC is a three-dimensional structure with a logic device at its base and a plurality of DRAMs vertically stacked above it using through-silicon via (TSV) connections. In this talk, the HMC concept is analyzed, exploring how the DRAM functions are re-architected to deliver a scalable, energy efficient system architecture, delivering extremely high performance and resiliency. The presentation will also address how innovative and disruptive solutions such as HMC require equally innovative tools, ecosystems and go-to-market strategies.

3D Keynote: Scott Graham

Scott Graham - General Manager, Hybrid Memory Cube Technology
Micron Technology, Inc.

Mr. Graham joined Micron in 1994 as an applications engineer in the personal computing division. He has held various managerial positions within Micron and has spent the last 11 years in Micron's memory products division, working on technical marketing for DRAM and NAND memory products. In recent years, Mr. Graham has represented Micron in various organizations responsible for setting industry standards, holding numerous vice-chair, chair, and board-level positions.

Mr. Graham holds a Bachelor of Science in Electronic Engineering Technology from DeVry University and a micro-MBA certification from Boise State University.

8:45 AM - 9:30 AM
Overview of Critical 3D Integration Challenges to Bring Products to Market

The widespread adoption of 3D Integration is inevitable with many companies introducing products into manufacturing or beginning the latter stages of development [1-3]. In this talk, we will discuss three focus areas that need improvement and cost reduction in order to bring 3D integration into the mainstream.

A critical issue that CNSE is currently investigating is thin-wafer handling, which presents many problems in terms of process handling of thinned wafers, debonding from carrier wafers, cleaning, dicing, and shipping. Each of these process steps pose some risk of wafer breakage or defects that decrease process yield and increase final costs. This remains as a significant challenge for the up scaling and mass production of 3D integration products. These challenges and potential solutions will be discussed in this presentation.

The other area that is of high interest to the 3D community is the bonding method used to connect each layer of a 3D stack. Three types of bonding methods are examined: copper-to-copper (Cu-Cu) direct thermo-compression (TC) bonding, transient liquid phase bonding (Cu - Sn on Cu), and solder bonding. The benefits, cost, and technical obstacles of these techniques will be discussed.

Finally, important challenges for Assembly and Test ( with respect to OSATs) will be discussed. There is a significant gap between semiconductor manufacturing and OSATs with regards to 3D integration. Large Fabs have solved this issue in-house with fully integrated semiconductor and packaging solutions. However, the roadmap for the rest of the industry is unclear for packaging of 3D integrated die. This item will be discussed in terms of the expanding role of OSATs that will be required in order to successfully bring 3D integration products into the marketplace.

3D Keynote: Douglas Coolbaugh

Douglas Coolbaugh - Derivatives and 3DI Manager
College of Nanoscale Science and Engineering (CNSE) at Albany SUNY Nanofab

Douglas Coolbaugh received his PhD in Physical Chemistry from SUNY Binghamton, NY in 1987. Doug retired from IBM in 2010 after working 30 years in microelectronics development. Presently he is the Assistant VP of derivatives at the College of Nanoscale Science and Engineering.

9:30 AM - 10:15 AM
Contributing to 3D Interconnect (3DIC): One Toolmakers Approach to Meeting the Challenge

For the last five of six years, identifying the requirements and metrics to meet 3D Interconnect high volume manufacturing (HVM) readiness has been a moving target. Will 3DIC happen in the front end of the line, advanced packaging or somewhere in between? From a toolmakers perspective, it is easy to get confused. It is a management challenge to fund programs one year that are redefined the following year. Finding solutions that will facilitate the transition to 3DIC is our professional obligation as responsible equipment manufacturers and corporate citizens.

At TEL NEXX, we see cost effective solutions as the most significant challenge to 3DIC implementation. During this talk, I will share two of the approaches we used at TEL NEXX to identify and test proposed 3DIC solutions. The first method has been to collaborate with our suppliers transparently in order to speed up development lifecycles and minimize scale up costs. The second method has been to explore alternative solutions outside of the traditional unit process flows in search of disruptive technologies. These strategies helped us offer our customers a path to progress towards 3DIC HVM readiness.

3D Keynote: Tom Walsh

Tom Walsh - President
TEL NEXX at Tokyo Electron

Dr. Tom Walsh is President of TEL NEXX at Tokyo Electron, a leading worldwide semiconductor equipment provider focused on building advanced packaging tools. Walsh led teams of semiconductor professionals to successfully deliver game changing technologies to the market, including the growth and eventual sale of NEXX Systems to Tokyo Electron for Advanced Packaging Deposition (2012), the development of the Novellus Sabre Plating system for Copper Interconnect (1998) and the commercialization of the IBM Atomic Force Microscope (1993). Over the past 25 years, Walsh held roles from scientist to corporate executive at IBM, Novellus and NEXX Systems. He holds a Ph.D. in analytical chemistry from Purdue University and an MBA from the Stern Business School at NYU.



10:15 AM - 10:30 AM: Coffee Break In Ballroom Foyer
IMAPS Cafés sponsored by:
LORD - IMAPS Cafe Sponsor


10:30 AM - 12:00 PM
3D IC PANEL DISCUSSION:

What are preventing 3D IC integrations from High Volume Manufacturing?

(JR. BALLROOM F)


Moderator: John H. Lau, ITRI, Taiwan

3D IC integration with through-silicon via (TSV) technology provides the opportunity for the shortest chip-to-chip and the smallest pad size and pitch interconnects. Compared with other interconnection technologies, the advantages of 3D IC integration include better electrical performance, lower power consumption, wider data width and thus bandwidth, higher density, smaller form factor and lighter weight. What are preventing 3D IC integrations from High Volume Manufacturing? In this panel, the challenges on costs, business models, value chains, power distribution networks, floorplanning constraints, stacking solutions, tests, standards, ecosystem, temporary bonding and de-bonding of 3D IC integration will be discussed and some solutions are provided.


"Challenges of Implementation of 3D Integration into Application Environment"

Challenges for volume production in 3D integration are, for examples extended standards, flexible production lines, value chain oriented test procedures and the exchange of application experience. With improvement of these emphases we will overcome today's major barrier, the expenses of implementation and products.

3D Panel: Klaus-Dieter Lang

Prof. Dr. -Ing. Dr. sc. techn. Klaus-Dieter Lang - Klaus-Dieter Lang is a Professor with the School of Electrical Engineering and Computer Sciences at the Technical University Berlin, Germany, where he leads research activities in the area of Nano Interconnect Technologies. He is also the Director of the Fraunhofer Institute for Reliability and Microintegration, IZM, Berlin.

Professor Lang began his career as a Research Engineer at Humboldt University Berlin, where he spent 10 years (1981 to 1991) working in the areas of Microelectronic Assembly, Packaging and Quality Assurance. In 1991, he moved to SLV Hannover to build up a Department for Microelectronic and Optic Components Manufacturing. He joined Fraunhofer IZM 20 years ago and was initially responsible for R&D activities in the area of Chip Interconnection Technologies. From 2001 to 2005 he coordinated Fraunhofer IZM's Lab on Microsystem Engineering in Berlin-Adlershof, and from 2003 to 2005 he was the Head of the Department of Photonic and Power System Assembly. In 2006, he was appointed as the Deputy Director of Fraunhofer IZM, a position he held till 2010. Since 2011 he has been the Director of the Institute.

Professor Lang Chairs the German Chapter of IEEE-CPMT and he is a member of numerous scientific boards and conference committees. He is the author and co-author of 3 books and more than 130 publications in the field of Wire Bonding Technologies, Microelectronic Packaging, Microsystems Technologies and Chip-on-Board Technologies. He studied Electrical Engineering at the Humboldt University Berlin, and holds a Master's degree and two Doctorate degrees.

 

"TSV [R]evolution: 2.5D Interposers, 3D Memory Stacks, 3D Logic on Logic"
Adoption of TSVs in high volume applications such as wireless mobile depends on balancing value propositions more heavily weighted by cost considerations. Direct 3D TSV logic on logic stacking must also solve several key technical challenges before it will be ready for product applications, including 3D power distribution networks, floorplanning constraints, and mechanical stress management.

3D Panel: Matt Nowak

Matt Nowak is Senior Director of Engineering in the VLSI Technology Group of Qualcomm Technologies, Inc. His responsibilities include leadership of Advanced Technology Initiatives such as Through Silicon Stacking, Advanced Memory technology, Design for Silicon, Spintronics, and “More than Moore” initiatives. He manages a combination of internal advanced development teams, supplier JDPs, and consortia and university projects.

Matt has over 30 years of semiconductor industry experience in a variety of technical, management, and business roles including wafer fab processes and devices, CMOS ASIC technology, compound semiconductor RF devices, package design and assembly, IC design tools and methodologies, technology transfer, foundry interfacing, and advanced technology. Prior to joining Qualcomm in 2004, Matt worked for the Semiconductor Development group of Unisys/Burroughs Corporation and for the Research Laboratory of Varian Associates. He holds BS and Masters degrees in electrical engineering from Cornell University and has carried out graduate studies at Stanford University and UC San Diego. Matt is a Senior Member of the IEEE with 26 granted US patents and numerous publications and conference presentations.

 

"Challenges of 2.5D and 3D Architectures"
2.5D and 3D architectures face a variety of challenges, most notably those around business model and ecosystem development. This panelist will focus on how Micron is addressing these challenges through the development of innovative solutions along with an ecosystem of OEMs, enablers and advanced toolset providers for their Hybrid Memory Cube.

3D Panel: Scott Graham

Scott Graham - General Manager, Hybrid Memory Cube Technology
Micron Technology, Inc.

Mr. Graham joined Micron in 1994 as an applications engineer in the personal computing division. He has held various managerial positions within Micron and has spent the last 11 years in Micron's memory products division, working on technical marketing for DRAM and NAND memory products. In recent years, Mr. Graham has represented Micron in various organizations responsible for setting industry standards, holding numerous vice-chair, chair, and board-level positions.

Mr. Graham holds a Bachelor of Science in Electronic Engineering Technology from DeVry University and a micro-MBA certification from Boise State University.

"Temporary Bonding and Debonding Challenges"
There are several techniques to do temporary bonding/debonding, which have to be evaluated to suit a specific 3D IC process flow. With each of these techniques, a complex set of manufacturable processes/materials and equipment have to be developed. It is apparent that a large scale manufacturing requires collaboration of process, materials and equipment developers with OSATs and IDMs.

3D Panel: Rajen Chanchani

Rajen Chanchani - Consultant (Formerly with Sandia National Laboratory).

Rajen Chanchani is currently a Consultant in electronic integration technologies. Prior Rajen was managing various advanced packaging and integration technologies for 32 years at Sandia National Laboratories, and at AT&T Bell Laboratories. He received his Ph.D. and M.S. in Materials Science & Engineering from the University of Florida and B. Tech. from the Indian Institute of Technology, Kanpur, India. Rajen is an IEEE Fellow, International Microelectronic and Packaging Society (IMAPS) Fellow. Rajen is also a recipient of William D. Ashman Award for his contribution to advance packaging technologies. Rajen is currently First Past-President of IMAPS.

Rajen has an extensive experience in 3D Integration technologies, micro-systems packaging, wafer-level packaging, chip-scale-packaging, multi-chip modules, thin and thick-film, chip-on-board, flip-chip, MEMS packaging and surface mount technologies and modeling & simulation.

"Status of TSV Manufacturing - Reality Check"
How far we've come, where we are, and how much further do we need to go before HVM for 2.5/3D products?” These questions will be discussed and some answers will be provided.

3D Panel: Rich Rice

Rich Rice - Sr. VP of Sales
ASE (US), Inc.

Rich Rice currently serves as Senior Vice President of Sales for ASE (U.S.) Inc., with responsibilities within the North America region. Previously, he held various engineering and business development positions at Amkor Technology and National Semiconductor Corporation. Mr. Rice serves in advisory roles for MEPTEC as well as the IMAPS Global Business Council. He holds a BS degree in Agricultural Engineering from the University of Illinois.

12:00 PM - 1:00 PM: Lunch Break (Attendees on their own for lunch) 

 

Schedule

INTERPOSERS & 2.5/3D PACKAGING

(SALON ROOM 3)

MODELING, DESIGN, TEST & REL

(SALON ROOM 5)

MATERIALS & PROCESSES

(SALON ROOM 1)

ADVANCED PACKAGING & ASSEMBLY

(SALON ROOM 6)

ADVANCED & EMERGING TECHNOLOGIES

(SALON ROOM 2)

SPECIAL SESSIONS ON PACKAGING & SYSTEM-INTEGRATION

(SALON ROOM 4)

Thursday, October 3, 2013

1:00 PM -
4:10 PM

Technologies and Methods for 2.5/3D Packaging and Integration
Chairs: Anwar Mohammed, John Hunt, ASE US

This session covers some emerging developments in enabling the manufacturing of 2.5/3D products. The papers cover some interesting and pertinent topics like the move of the BEOL processes towards the front end, stacking high speed memory, underfill effectiveness, reduction stepper challenges, litho optimization, IPDs and POP reliability.

RF and Microwave Packaging
Chairs: Xiaoguang "Leo" Liu, University of California, Davis; Fred Barlow, University of Idaho

RF and microwave applications present unique packaging challenges. This session brings together a wide range of papers on various topics including packaging for RF-MEMS, RFIC, and antennas.

Bonding Materials and Processes
Chairs: Maria Durham, Indium Corporation; Klaus-Dieter Lang, Fraunhofer IZM

Novel bonding materials and processes will be introduced in this session for overcoming the continuing challenges with the bonding materials and the bonding processes in various types of applications.

LED and Optoelectronics Packaging
Chair: Martin Schneider-Ramelow, Fraunhofer IZM

This session will address packaging of high bandwidth optical interconnects and modules. The performance of various LED modules will also be discussed from a reliability viewpoint.

Printed Electronics & Additive Manufacturing
Chairs: Mike Newton, Newton Cyberfacturing; Yiliang Wu,
Xerox Research Centre of Canada

Terms like the next industrial revolution have been used to describe the rapid advances in the 3D printing technology. With the convergence of additive manufacturing and printed electronics there are opportunities in the development of the next generation electronic packaging where the printed circuit board evolves into a printed circuit structure where the final produst is the package.

Electronic Packaging for Harsh Environment Applications
Chairs: Aicha Elshabini, University of Idaho; Tom Buschor, Harris Corporation

Extreme environment entail high temperature, extreme humidity levels, stress, and vibrations. This session addresses these issues in particular modeling and analysis of failure and design for reliability through thermal and power cycling and materials and devices selection.
1:00 PM - 1:25 PM
Lithography Process Optimization for 3D and 2.5D Applications
Doug Shelton, Canon U.S.A., Inc. (Tomii Kume)
Chip Design of an 1 V RF Receiver Front-End for 5.8-GHz DSRC Applications
Wen Cheng Lai, National Taiwan University of Science and Technology (Jhin-Fang Huang, Yong-Jhen Jiangn)
Silver Oxalate: Towards a New Solder Material for Highly Dissipative Electronic Assemblies
K. Kiryukhina, CNES (H. Le Trong, P. Tailhades, J. Lacaze, F. Courtade, S. Dareys, O. Vendier, L. Raynaud)
Packaging of 1.3 Tbs Full Duplex Optical Interconnect
Shuki Benjamin, Compass-EOS (Kobi Hasharoni
Michael Mesh)
FEATURED SPEAKER
3D Additive Construction using Regolith
Robert Mueller, NASA Kennedy Space Center

CANCELLED BY AUTHOR - GOVT SHUTDOWN

Advanced Devices and Packaging for Harsh Environment Operation
Aicha Elshabini, University of Idaho (Sharmin Islam, Pin-Jen Wang)
1:25 PM - 1:50 PM
Integrated Passive Devices and TSV, a Disruptive Technology for Miniaturization
Catherine Bunel, IPDIA (S. Borel, A.Lefevre, CEA-Leti, MINATEC; F. Voiron, J-R. Tenailleau, IPDIA)
RF Device Integration on Glass Interposer toward 3D-IPAC Packages
Yoichiro Sato, Asahi Glass Company (Vijay Sukumaran, Gary Menezes, Bruce Chou, Junki Min, Motoshi Ono, Choukri Karoui, Franck Dosseul, Christian Nopper, Madhavan Swaminathan, Venky Sundaram, Rao Tummala)
Preparation of a Wafer-Level Hemispherical Micro Polymer Lens Array with Improved Performance Using a Low Cost Glass Mold
Jintang SHANG, Southeast University, P.R. China (Shunjin QIN)

CANCELLED BY AUTHOR

A Switched-Line Microwave Phase Shifter Fabricated with Additive Manufacturing
Jonathan O'Brien, University of South Florida (Mike Newton, Thomas Weller, Daniel Silva, Eduardo Rojas)
1:50 PM - 2:15 PM
Frontend-ization of the Back-End
Rajiv Roy, Rudolph Technologies
RF MEMS DPDT Switch Using Novel Simulated Seesaw Design
Mohammed Al-Amin, Anglia Ruskin University (Sufian Yousef, Barry Morris)
Five-Layer Cu-Coated Zn/Al Clad Solder for Die Attachment
Takuto Yamaguchi, Hitachi, Ltd. (Osamu Ikeda, Shohei Hata, Yuichi Oda, Kazuma Kuroki)
Compact Photonic Package for High-Power E-band (60-90 GHz) Photoreceiver Modules
Tolga Tekin, Fraunhofer IZM (Vitaly Rymanov, University Duisburg-Essen; Merih Palandoken, Sebastian Duelme, Andreas Stohr)

CANCELLED BY AUTHOR

Fully 3D Printed 2.4 GHz Bluetooth/Wi-Fi Antenna
Paul Deffenbaugh, University of Texas at El Paso (Kenneth Church, The University of Texas El Paso; Josh Goldfarb, Xudong Chen, nScrypt, Inc.)
Modeling of Failure in Aluminum Alloy Braze for a High Temperature Thermoelectric Assembly
Shams Arifeen, University of Idaho (Gabriel Potirniche, Aicha Elshabini, Fred Barlow)

 

COFFEE BREAK IN SALON FOYER: 2:15 PM - 2:30 PM

IMAPS Cafés sponsored by:
LORD - IMAPS Cafe Sponsor

2:30 PM - 2:55 PM
Stacking of known good rebuilt wafers for high performance memory and SiP
Pascal Couderc, 3D PLUS (Jerome Noiray, Christian Val)
A Novel Epoxy Flux On Solder Paste For Assembling Thermally Warped POP
Ning-Cheng Lee, Indium Corporation (Ming Hu, Lee Kresge)
A Solder Joint Reliability Model for the Philips Lumileds LUXEON Rebel LED Carrier Using Physics of Failure Methodology
Greg Caswell, DfR Solutions (Rudi Hechfellner, Michiel Kruger, Tewe Heemstra, Philips Lumileds; Nathan Blattau, Gregg Kittlesen, Vikrant More,
DfR Solutions, LLC)
Multi-layer PC Boards Fabricated using Aerosol-Jet Printing
John Bolger, Department of Defense

CANCELLED BY AUTHOR - GOVT SHUTDOWN

2:55 PM - 3:20 PM
A Study on the Effectiveness of Underfill in the HBM with TSV
Woong Sun Lee, SK hynix (Ho Young Son, Jin Soo Lee, Chul Gun Yoon, Min Suk Suh, Nam Seong Kim)
Production Proven, High Precision Temporary Bond/De-bond Process
Blake Dronen, 3M Company (Kazuta Saito, B.K. Wang)
The Effects of Humidity and Temperature Aging Test on Flexible Packaging LED Module
ChunjinHang, Harbin Institute of Technology

CANCELLED BY AUTHOR

3:20 PM - 3:45 PM
Improved Compensation for a Reduction Stepper to Meet the Challenges for Advanced Packaging Applications
James Webb, Rudolph Technologies (Elvino Da Silveira, Steve Gardner, Frank Namgung)
Droplet-on-Demand Inkjet-filled TSVs as a Pathway to Cost-efficient Chip Stacking
Jacob Sadie, University of California, Berkeley (Niels Quack, Ming Wu, Vivek Subramanian)
Effect of Voiding in Solder Joints on Thermal Performance of the LED
Jianbiao Pan, California Polytechnic State University
Non-contact microwave characterization of printed resistors
Maria F. Cordoba-Erazo, University of South Florida (Thomas M. Weller)
3:45 PM - 4:10 PM
Microstructure and Fracture Property of Cu/In/Cu Joints in 3D Package
Yanhong Tian, Harbin Institute of Technology

CANCELLED BY AUTHOR

Transient Thermal Analysis as In-Situ Test Method for Reliability of High Power LEDs During Temperature Cycle Tests
Gordon Elger, Technical University of Applied Science; Shri Vishnu Kandaswamy, University of Freiburg (Robert Derix, Philips Technologie GmbH; Joergen Wilde, University of Freiburg)

 

.

 

Hotel Reservations (Hotel Deadline: September 6, 2013)
Reservations must be made directly with the:

Rosen Centre Hotel
9840 International Dr
Orlando, FL 32819 USA

$154+taxes - single/double (Additional Person $20)

Phone Reservations: 1-800-204-7234 -- Mention IMAPS 46th Annual Symposium on Microelectronics when calling.

IMAPS cannot guarantee room availability and/or rates after the published hotel deadline. Book your rooms directly with the hotel before the deadline noted above.


Walt Disney World Advance Purchase Tickets

Walt Disney World - Discounted Advance Purchase Tickets

IMAPS has teamed up with Disney for a special offer for those attending IMAPS 2013 in Orlando. Have a little fun while visiting Orlando for our 46th Sympsoium...

If you're planning a trip to Walt Disney World® Resort during your participation at IMAPS 2013 Orlando in September-October 2013, please visit www.mydisneymeetings.com/imps13/ for information about ordering tickets in advance, at the special conference rate!

 


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