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IMAPS 2014 - San Diego
The Future of Packaging!
www.imaps2014.org

IMAPS 2014 - San Diego

Conference:
October 14-16, 2014
Exhibition:
October 14-15, 2014
Professional Development Courses:
October 13 & 16, 2014

Professional Development Courses (PDCs)


Early Registration and Hotel Deadline: September 12, 2014

 

NEW PDC FORMAT - Monday & Thursday Courses:
Monday, October 13: full-day courses, running 10:00 am - 6:00 pm;
Monday, Half-day courses running 10:00am - 1:45pm & 2:15 pm - 6:00 pm

All Thursday, October 16 are half-day, running 8:00 am - 12:00 pm

MONDAY FULL-DAY PDCs: (10am-6pm)
- Introduction to 3D Printed Power Electronics & Wide Bandgap Power Semiconductor Packaging;
- Introduction to the Design and Fabrication of RF, High Speed and Microwave Hybrids, MCM's and Modules;
- Introduction to Microelectronics Packaging;
- Polymer Challenges in Electronic Packaging Including 2.5D and 3D Integration;
- Technology of Screen Printing;
- Wire Bonding

MONDAY MORNING HALF-DAY PDCs: (10am-1:45pm)
- ENIG - Electroless Nickel & Immersion Gold Plating for Electronics: From the Plating Solutions to the Equipment;
- High-Temperature Electronics;
- MEMS and nanoMEMS Devices and Applications;
- Package level integration : 2-D, 2.5-D and 3-D, Impact on Mobile Systems - CANCELLED

MONDAY AFTERNOON HALF-DAY PDCs: (2:15pm-6pm)
- Low-Temperature Electronics - CANCELLED;
- Package on Package Technology - What It Is, What Works, What Doesn't Work;
- Thermal And Mechanical Simulation Techniques For IC Package Yield, Reliability And Performance

THURSDAY HALF-DAY PDCs: (8am-12pm)
- Chip Packaging Processes and Materials;
- Fundamentals of Microelectronics Packaging;
- IC Fabrication and Electronic Packaging;
- Interposers - Silicon, Organic and Glass;
- Packaging and Testing of Implanted Medical Devices;
- Understanding the Common Failure Modes from a Physics of Failure Perspective

Get off line and learn Face to Face...Sign up for a PDC!

PDCs (Professional Development Course) are a big part of the Annual IMAPS Symposium each year. Why not plan to take a course on Monday or a Thursday AM session and take advantage of the rich learning opportunities available at the IMAPS symposium. This year the Monday courses are going to have a delayed start kicking off at 10 AM and running till 6 PM with a working lunch. It's something new and we hope you like it. This new time slot will give the locals a chance to beat the traffic and a little extra time for the out of town folks to get organized and prepare for a full day of learning.

PDCs create a unique environment whereby students can personally interact with the instructors, and with each other in the classroom and over lunch. It's mentally stimulating and the new found professional connections will prove to be valuable in the long run. Learning on line is fine, but it cannot duplicate eight hours spent immersed in a specific topic, led by an industry expert in the field and surrounded by like minded professionals. My father used to say, "it's not what you say but how you say it." So much of what we learn is contained in the tone of voice and non-verbal cues. PDCs provide that learning environment that's just not available on line.

This year we've put together another impressive assortment course options Our goal is to make the IMAPS PDCs the premier learning experience; so we ask that you take time to fill out the evaluation form that accompanies each course and give us your feedback on this or any other aspects of the PDCs. Read through the course descriptions on line and pick the course that best suits your company and career objectives. Every PDC includes a full set of comprehensive course notes. Class sizes typically range from eight to twenty students and there is always ample time for questions. We hope you will consider joining us in San Diego for a learning experience like no other.

Education is a lifelong pursuit, don't miss out on this opportunity!
Tom Green and James McEwen
IMAPS 2014 PDC Co-Chairs

 

Your PDC Registration Fee Includes:

  • "Working Lunch" (box lunch in PDC room) on the day of your course (Monday full-day & Morning PDCs only)
  • Refreshment breaks
  • Hard-copy workbook of course materials (no electronic copies provided)
  • Attendee list following your course

Monday PDC Lunch sponsored by:
Heraeus Materials Technology - Premier Sponsor, Gold

PDCs under SESSIONS
during IMAPS 2014 Online Registration

PDC Cancellation policy: IMAPS reserves the right to cancel a course if the number of attendees is not sufficient.
You can transfer to a different course or we will refund you the corresponding amount.


Monday, October 13, 2014

Full-Day PDCs run 10:00 am - 6:00 pm
MORNING Half-Day PDCs run 10:00 am - 1:45 pm

AFTERNOON Half-Day PDCs run 2:15 pm - 6:00 pm

PDC "Working Lunch" for Full & Morning Classes: 12:00-1:00pm
(Pickup box lunch & return to room)
PDC Afternoon Coffee Break in Foyer: 3:30-3:45pm

PDC Coffee Breaks & Lunch sponsored by:
Heraeus Materials Technology - Premier Sponsor, Gold

MONDAY FULL-DAY PDCs: (10am-6pm)
- Introduction to 3D Printed Power Electronics & Wide Bandgap Power Semiconductor Packaging;
- Introduction to the Design and Fabrication of RF, High Speed and Microwave Hybrids, MCM's and Modules;
- Introduction to Microelectronics Packaging;
- Polymer Challenges in Electronic Packaging Including 2.5D and 3D Integration;
- Technology of Screen Printing;
- Wire Bonding

M1: Introduction to 3D Printed Power Electronics & Wide Bandgap
Power Semiconductor Packaging

PDC Instructor: Douglas C Hopkins, North Carolina State University
$600 (on/before 9/12/2014); $700 (after 9/12/2014)

Course Description: Power densities and switching speeds in power electronics applications have increased well over ten fold in the last three years. With the advent of post-silicon power devices, i.e. SiC, GaN and GaAs, voltages and current densities are at unprecedented levels. The greatest change is in switching speeds that approach gigahertz. All this, and operating temperatures are pushing above 250C.

This course is an excerpt from a 45-hour university graduate course that introduces the evolving characteristics of the post-silicon devices; new "energy electronics" packaging materials; and new 3D printed power-packaging technologies. This daylong course presents a comprehensive approach from defining the new challenges facing power packaging to new packaging techniques for working at higher temperatures.

Half the course details more traditional power packaging techniques, such as directed-bonded-metal (Al - DBA and Cu - DBC) and limitations on their applicability to the new higher temperatures and speeds. The other half shows how microelectronics packaging technologies, such as 3D printing, and stack die and stacked boards, can be used in power applications for point of load converters, etc.

Who Should Attend? This course is focused toward packaging design engineers that must integrate power into digital and datacomm systems, or must create next-generation power modules.

Dr. Douglas Hopkins is Professor and Director of the Laboratory for "Packaging Research in Electronic Energy Systems" as part of the NSF-funded FREEDM Systems Center at North Carolina State University in Raleigh, NC. He was formerly with SUNY Buffalo as Director of the "Electronic Power and Energy Research Lab". He received his Ph.D. from Virginia Tech, worked for GE's and Carrier's R&D Centers, and held visiting positions at several national labs. He is an IEEE senior member and IMAPS fellow. He is a founding member of IMAPS Subcommittee on Power Packaging, now chairs the technical subcommittee on Electronic Energy Packaging in IEEE-CPMT and member of the IEEE-PELS technical committee on Emerging Technologies. He has authored over 100 journal and conference publications, received three ISHM/IMAPS awards.


M2: Introduction to the Design and Fabrication of RF, High Speed
and Microwave Hybrids, MCM's and Modules

PDC Instructor: Tom Terlizzi, GM Systems llC/Agile Microwave Technology Inc.
$600 (on/before 9/12/2014); $700 (after 9/12/2014)

Course Description: The course presents electrical and physical design, manufacturing, materials, quality and reliability information in terms understandable to engineering and non-engineering personnel. RF Packaging history, characteristics and drivers will be outlined. Types of packages (IC, chip scale, MEMS, Hybrid, MCM, Flip Chip, BGA, Aluminum and Kovar housings) and substrates (Thick and thin film, HTCC, LTCC ceramic, organic) and critical differences among them and their High Frequency applications (Microstrip, Stripline, Coplanar will be discussed. RF and Microwave layout and the commonly used design tools and software will be outlined. The course will look at the design selection to meet use and application environments. Step-by-step manufacturing flow for different packages and products will be presented as an example to understand the complexity of processes, materials and equipment involved in their manufacture. RF & Microwave packaging concepts will be introduced and the tradeoffs of different interconnect methodology (connectors, wire bonds, ribbon bonds, AuSi & AuSn eutectic, soft solder and epoxy. Materials selection with respect to thermal resistance will be discussed. Finite Element and reliability software will be discussed to insure the design will perform to specification. Quality and reliability issues related to RF packaging and their present and future solutions will be outlined.

Who Should Attend? It will help the attendees to understand the application and assembly of RF and Microwave microelectronic package technology on the next level interconnect and the service environment that microelectronic packages must protect its components. Personnel (Design engineers and process engineers) entering the RF microelectronic packaging field will have a critical look at the electrical design, physical design, layout quality, reliability and material issues related to the development and manufacture of microwave modules. Non-technical personnel will learn the material and manufacturing intricacies of RF and Microwave microelectronic packages and the associated buzzwords used to describe them.

Tom Terlizzi is VP at GM Systems, a Management and Technology consulting firm, providing Microelectronic Business & Technology plans, , Marketing & Sales strategy, Product development for microelectronic projects and business proposal support. He has designed and developed Power management systems, Single board computers, microelectronic circuits, hybrids, COB modules, ICs, RF modules, for over 30 years for military, aerospace, telecom and consumer markets as a VP/GM, Director of marketing, Chief Engineer, Operations/Engineering manager at Aeroflex, Norden/UTC, G.I. Microelectronics and Grumman. He spearheaded acquisitions of several high tech companies,ISO9000/Mil-PRF-38534 quality certifications. He received a BEE from CCNY, a MSEE from NYU-Poly & has published several articles, papers and tutorials at international conferences, edited books on electronic packaging, consulted for the DoD on advanced RF electronic packaging. Tom was the Metro ISHM Chapter President in 1983 and in his free time also writes a Blog for EDN Magazine Online - Looking @ electronics.

M3: Introduction to Microelectronics Packaging
PDC Instructor: Thomas J Green, TJ Green Associates LLC
$600 (on/before 9/12/2014); $700 (after 9/12/2014)

Course Description: The instructor begins by broadly describing packaging terminology and reviews the alphabet soup of acronyms used throughout the electronics industry; terms such as: DIP, LCC, QFN, Hybrids, BGA, CSP, Flip Chip, 3D, TSV, WLP etc. The technology is then broken down by industry segments, beginning with high volume commercial packaging technology used in cell phones, tablets and handheld wireless devices, automotive, telecom and then progressing onto specialized packaging for low volume complex devices used in military/space/medical products as well as, RF microwave circuits, optoelectronics, LEDs and next generation packaging of MEMS and sensors. Lots of pictures, short video clips and pass around samples, along with simple explanations will help the attendee understand the technology drivers and key aspects of microelectronic packaging technology in a fun and interactive way. Besides a good overview the student will understand the basics of how to assemble and package single and multi-chip microcircuits, with a focus on the materials and processes and the associated equipment sets needed to support the industry. Wafer processes, probing and dicing, substrate selection, interposers, die attach using solders and epoxy, AU/Al/Cu wirebond processes, underfills, encapsulations, dam and fill, glob tops, transfer molding and hermetic packaging are all be reviewed with an eye on the important technical issues and industry drivers. Current hot topics and future industry trends will finish out the day and there will be plenty of time for questions.

Who Should Attend? This overview course is intended for those unfamiliar with microelectronics packaging technology. People in sales, purchasing, program management, new engineers, managers, equipment/material suppliers, people new to this industry or anyone looking to get a broad industry overview and review of the industry drivers, history and future trends are welcome to attend.

Mr. Thomas Green is the principle at TJ Green Associates LLC (www.tjgreenllc.com) a veteran owned small business focused on training and consulting for military, space and medical microelectronic devices. He teaches a variety of public courses around the globe and in plant at major corporations and consults for a variety of medical device companies. He has thirty two years of experience in microelectronics working at positions in industry, academia and government. Tom has demonstrated expertise in die attach, wirebond, visual inspection, hermetic seal and leak testing processes. He has gained valuable experience over the past ten years in packaging and testing of devices for use as Class III medical implants and is often called on as an expert witness for hermeticity related failures. Tom is an active IMAPS member and Society Fellow. He has a B.S. in Materials Engineering from Lehigh University and a Masters from the University of Utah.

M4: Polymer Challenges in Electronic Packaging Including 2.5D and 3D Integration
PDC Instructor: Jeffrey Gotro, InnoCentrix, LLC
$600 (on/before 9/12/2014); $700 (after 9/12/2014)

Course Description: The course will provide an overview of polymers and the important structure-property-process-performance relationships for electronic packaging.  The main learning objectives will be: 1) learn how polymers are used in electronic packaging including die attach adhesives, underfills, mold compounds and substrate materials, 2) gain insights on how polymers are used in 2.5D and 3D packaging, 3) learn the key polymer challenges and processes for 2.5D and 3D packaging, 4) learn how to use polymer testing methods to gain insight into the key material properties relevant to electronic packaging, and 5) develop a foundation in rheology and rheological issues in electronic packaging.  Participants are invited to bring problems for discussion.

Who Should Attend? Packaging engineers involved in the development, production, and reliability testing of electronic packages would benefit. Those interested in gaining a basic understanding of the role of polymers and polymer-based materials used in electronic packaging will also find this PDC valuable.

Dr. Jeff Gotro has over thirty years' experience in polymers for electronic applications and composites having held scientific and leadership positions at IBM, AlliedSignal, Honeywell, and Ablestik Laboratories. Jeff is an expert in thermosetting polymers used in electronic packaging and has received invitations to speak at prestigious Gordon Research Conferences (Thermosetting Polymers and Composites). He has presented numerous invited lectures and short courses at technical meetings, has over 60 technical publications and 21 patents/patent applications.   Jeff was an Adjunct Professor at Syracuse University in the Dept. of Chemical Engineering and Materials Science from 1986-1993.  Jeff is a member of the Product Development and Management Association (PDMA), American Chemical Society (ACS), the Institute for Management Consultants (IMC), the Forensic Expert Witness Association (FEWA), and the International Microelectronics Assembly and Packaging Society (IMAPS).

M5: Technology of Screen Printing
PDC Instructors: Art Dobie, Sefar Inc.; David Malanga, Heraeus, Inc., Thick Film Division
$600 (on/before 9/12/2014); $700 (after 9/12/2014)

Course Description: Screen printing continues to offer innovative and cost effective solutions to the increasing demands for higher circuit densities. This course is intended to increase the understanding of the screen printing process, thereby improving production yield and print quality.

Presented are some of the latest advancements in composition, screens, and printing technology that enable screen printing to meet future circuit density requirements as well as the definition required for microwave circuitry. The advantages of screen printing, an additive deposition process, are described and compared to alternative more costly and "less-green" subtractive deposition technologies. This course is applications-oriented in terms of how to optimize the screen printing process; how to use and specify screen correctly; rheology properties that affect print results; minimizing printing defects and trouble-shooting problems related to screens, inks and the printing process itself.

Who Should Attend? This course is targeted for production and process engineers, plant and production managers, supervisors, and all others interested in learning how to optimize and increase the use of the screen printing process.

Art Dobie is Technical Marketing Manager for Sefar, Inc. He has been with Sefar 33 years since receiving his BS in Screen Printing Technology in 1980 from California University of Pennsylvania. Art has co-instructed the IMAPS "Technology of Screen Printing" PDC since its inception in 1991. He has delivered numerous technical presentations to screen-printing professionals at local, national and international level symposia. Mr. Dobie is a Life Member and Fellow of the Society of IMAPS, and received the 2006 IMAPS Technical Achievement Award for outstanding technical contributions to screen printing technology relating to microelectronics. In 1998, Art Dobie was inducted into the SGIA's Academy of Screen Printing Technology and is a co-recipient of the SGIA's 2010 David Swormstedt, Sr. Memorial Award.

David Malanga is currently Business Unit Manager Americas at Heraeus Precious Metals North America LLC, Thick Film Materials Division in West Conshohocken, PA.. David has over 20 years of experience at Heraeus working in R&D, formulating thick film and LTCC materials, Technical Service solving processing and application problems directly with customers, and as manager of the Sales Department. David has a B.S. and M.S. in Ceramic Science and Engineering from Rutgers University. David has published various articles on thick film resistors, conductors, LTCC materials, and component metallizations worldwide. He is a Life member and Fellow of the Society of IMAPS and has held both local and national positions in the organization.

M6: Wire Bonding
PDC Instructor: Lee Levin, Process Solutions Consulting, Inc.
$600 (on/before 9/12/2014); $700 (after 9/12/2014)

Course Description: Wire Bonding is a welding process that is the dominant chip interconnection method. More than 15 trillion wires are bonded annually. The majority use gold wire, however, copper wire is experiencing rapid growth in market share. Copper provides benefits in cost, improved conductivity and stiffness. However, it is significantly harder than gold and achieving a robust, reliable process is a challenge. Gold, with defect rates in high-volume lead-frame applications below 10ppm, presents a significant barrier to entry but copper is meeting the challenge. Today more than 1 billion smart phones are produced, each having at least one stacked die package. Stacked dies are used to produce Systems In Package (SIPs) that enable the advanced features consumers demand.

The flexibility, reliability and yield of wire bonding make it a process worthy of careful study. Today's wire bonding equipment is capable of producing 24 wires/second (48 welds) with bond placement accuracy of ±2.0µm. During the descent of the tool the bond head has an acceleration of >300g. Achieving highly repeatable bonds with the stated bond placement accuracy and yet accelerating at 300g requires exceptional engineering design. The wire bonder is one of the worlds most advanced machines requiring high speed pattern recognition, ultra-light, stiff sub-assemblies (imagine trying to achieve the same speed and accuracy with a graphite fishing rod), and feed forward control systems. The course will cover:

-Introduction
- A snapshot of some microelectronic packages
- Size of the market
- Cost of a wire bond
- Ultrasonic Welding
- Intermetallics
- Bond Testing
- Copper wire bonding
- Looping and Ball Formation
- Wire
- Fine Pitch Bonding
- Plating
- Wire Bond variations (ball bumping)

 

Who Should Attend? Engineers in R&D, QA, QC, manufacturing, process development, and advanced technicians. It is assumed that participants have some familiarity with wire bonding and general device assembly technologies.

Lee Levine is a consultant for Process Solutions Consulting, Inc. where he provides process engineering consultation, SEM/EDS analysis, and wire bond training. Lee's previous experience includes 20 years as Principal and Staff Metallurgical Process Engineer at Kulicke & Soffa and Distinguished Member of the Technical Staff at Agere Systems. He has been awarded 4 patents, published more than 70 technical papers, and in 1999 won the John A. Wagnon Technical Achievement award from the International Microelectronics Assembly and Packaging Society (IMAPs). Major innovations include copper ball bonding, loop shapes for thin, small outline packages (TSOP and TSSOP, and CSPs) and introduction of DOE and statistical techniques for understanding semiconductor assembly processes. He is an IMAPs Fellow and a senior member of IEEE. He is a Contributing Editor for TAP Times, an online packaging newsletter. Lee is a graduate of Lehigh University, Bethlehem, Pa where he earned a degree in Metallurgy and Materials Engineering.

 

MONDAY MORNING HALF-DAY PDCs: (10am-1:45pm)
- ENIG - Electroless Nickel & Immersion Gold Plating for Electronics: From the Plating Solutions to the Equipment;
- High-Temperature Electronics;
- MEMS and nanoMEMS Devices and Applications;
- Package level integration : 2-D, 2.5-D and 3-D, Impact on Mobile Systems - CANCELLED

MA1: ENIG - Electroless Nickel & Immersion Gold Plating for Electronics:
From the Plating Solutions to the Equipment

PDC Instructor: Fred Mueller, General Magnaplate Corp.
$400 (on/before 9/12/2014); $500 (after 9/12/2014)

Course Description: Provide a thorough overview of the use of electroless nickel and immersion gold and other precious metals used for a variety of applications in the field of electronics; Review the engineering differences and troubleshooting problems associated with the ENIG plating process; Presents methods for controlling the properties of plating solutions to maximize the deposits properties, including Laboratory Controls Electroless Nickel/Immersion Gold, Solderability and Solder Joint Reliability as Functions of Process Control - What lack of ENIG process controls can result in black pad?

Who Should Attend? This course is intended as an introductory to intermediate level course for process engineers, quality engineers, and managers responsible for Plating for Electronics.

Mr. Fred Mueller is a consultant and serves as a national certified instructor for the American Electroplaters and Surface Finishing Society (AESF). He has over twenty-five years of experience in the plating industry in printed circuits and plating for electronics. He is currently the National Quality Manager at General Magnaplate, Linden, NJ. As a Chemist, Fred has conducted experiments and presented technical papers at SurFin on various topics in electroplating. He is very active in the AESF Foundation currently serving as Vice President on the National Board.

MA2: High-Temperature Electronics
PDC Instructor: Randall Kirschman, Consultant
$400 (on/before 9/12/2014); $500 (after 9/12/2014)

Course Description: High-Temperature Electronics is a valuable option for improving overall system performance: increased efficiency, decreased size and weight, simplified maintenance and improved reliability.

The focus of this course is semiconductor electronics at high temperatures: device behavior, applications, advantages and drawbacks, technical issues, and present situation. Basic materials characteristics related to electronics at high temperatures, and passive electronic component behavior, are included. The temperature range covered in this course extends from +125C upward, as high as 1000C. Depending on the temperature range, HTE semiconductor devices may be based on Si, SiGe, GaAs, SiC, GaN, C (diamond) and other materials.

Course Objectives: Provide an overview of situations where the technologies of electronics and high temperatures are brought together. Provide an overview of the applications for high temperature electronics. Survey the relationships between fundamental phenomena, materials behavior, and device and system characteristics and performance at high temperatures. Overview the behavior of materials and components used in electronics at high temperatures: metals, ceramics, plastics, passive components, semiconductor materials and devices, and electronic circuits and assemblies. Provide practical information on materials, devices, circuits and techniques for those involved in high-temperature electronics.

Who Should Attend? Engineers and technical persons involved in developing electronics for high temperatures; also project managers and students who want an introduction and overview of the subject.

Dr. Randall Kirschman is an internationally recognized authority on extreme-temperature electronics. He has been consulting to industry, government and academe since 1980 on microelectronic materials and fabrication technology, and electronics for extreme temperatures. Before going into business for himself, he managed the processing laboratory at the R&D Center at a division of Eaton Corporation, where he was responsible for the fabrication of thin-film hybrids. Before that, he was a staff member of the Jet Propulsion Laboratory, performing research on semiconductor materials and devices. During 1990-91 he was a Visiting Senior Research Fellow at the Institute of Cryogenics, University of Southampton, England. Between 1998-2005, he was a member of the Physics Department at Oxford University. He edited the 1999 IEEE Press/Wiley book High-Temperature Electronics. He completed his undergraduate studies at the University of California, and earned his Ph.D. in Physics and Electrical Engineering at the California Institute of Technology in 1972.

MA3: MEMS and nanoMEMS Devices and Applications
PDC Instructor: Slobodan Petrovic, Oregon Institute of Technology
$400 (on/before 9/12/2014); $500 (after 9/12/2014)

Course Description: This full day course will explore futuristic concepts that combine MEMS and nanoscience. The merging of nanoscience and microelectromechanical systems presents an opportunity for development of next generation technologies for use in computers, wireless communication, biomedicine, and a variety of sensors.

The course will start by providing an overview of the MEMS principles of operation, fabrication methods, and in particular the materials used in building MEMS structures. Variety of MEMS devices will be discussed while a particular emphasis will be placed on MEMS in wireless communication; and sensors and actuators used in industrial, medical, and automotive applications.

The introduction to nanoscience will start by evaluating how size can influence the properties of nanoscale systems. The nanomaterial synthesis and characterization methods will be explored next. The highly speculative discussion will offer a possibility for using nanoscale phenomena for technological purposes related to MEMS. The emphasis will be placed on merging the nanoscience with MEMS fabrication principles, design considerations, integration aspects, and packaging.
In the third section, the integration of power supplies and energy storage devices with MEMS and nanoMEMS devices will be discussed. These devices will be the key in the packaging and for autonomous function of future devices. The general concept of nanoscience for energy will be discussed, in particular nanoscale batteries, fuel cells, hydrogen production, solar cells, and biological materials for energy production.

Who Should Attend? The course is open to anyone with general understanding of the physics, chemistry, and material science. The participants will have the opportunity to explore highly speculative, futuristic concepts and develop visionary views of the technological possibilities. The course is open to participants with no prior MEMS, nantotechnology, or power sources knowledge and would provide a reasonably broad general introduction into all three areas of technology.

Dr. Slobodan Petrovic is an associate professor at the Oregon Institute of Technology in Portland, OR. His research interests are in the areas of MEMS fuel cells, sensor media compatibility, hydrogen generation and storage, and dye-sensitized solar cells. Prior to that, he was at the Arizona State University, where he taught courses in MEMS, Sensors, and alternative energy. Dr. Petrovic also held appointments at Clear Edge Power as a Vice President of Engineering; at Neah Power Systems as Director of Systems Integration; and Motorola, Inc. as a Reliability Manager. Dr. Petrovic has over 25 years of experience in MEMS, sensors, energy systems; fuel cells and batteries; and electrochemical solar cells. He has over 50 journal publications and conference proceedings; 2 book contributions and 24 pending or issued patents.

MA4: Package Level Integration: 2-D, 2.5-D and 3-D, Impact on Mobile Systems
PDC Instructor: Dev Gupta, APSTL
$400 (on/before 9/12/2014); $500 (after 9/12/2014)

CANCELLED BY THE INSTRUCTOR

 

 

MONDAY AFTERNOON HALF-DAY PDCs: (2:15pm-6pm)
CANCELLED;
- Package on Package Technology - What It Is, What Works, What Doesn't Work;
- Thermal And Mechanical Simulation Techniques For IC Package Yield, Reliability And Performance

MP1: Low-Temperature Electronics
PDC Instructor: Randall Kirschman, Consultant
$400 (on/before 9/12/2014); $500 (after 9/12/2014)

CANCELLED

MP2: Package on Package Technology - What It Is, What Works, What Doesn't Work
PDC Instructor: Ning-Cheng Lee, Indium Corporation
$400 (on/before 9/12/2014); $500 (after 9/12/2014)

Course Description: This course covers Package on Package (PoP) Technology, including trends, designs, material selection, processes, and reliability. The approaches of enhancing the reliability will be discussed in details, including effect of fluxes, solder alloy types, processes, profiles, via designs, and ball sizes. Being the solution with the highest potential, epoxy flux will be introduced and will be compared with other solutions. Finally, head in pillow control at reflow soldering, particularly at PoP will be instructed. The control includes considerations on materials, processes, and designs.

Course Content:

1. Trends
2. Designs
3. Processes
3-1.General Processes.
3-2. Rework of PoP.
3-3. Processes - Selection of Dip Transfer Fluxes and Solder Pastes for PoP Assembly
3-4. Processes - Low Volume PoP Assembly Process Development
3-5. Processes - Design for Efficient PoP Underfilling
3-6. Processes - Comparison of Various Polymeric Reinforcement Approaches for PoP/CSP
4. Reliability - One-Pass vs Two-Pass
5. Reliability - Effect of SOP & Material on Yield & Drop Test Performance
6. Reliability - Effect of Materials & Profiles
7. Reliability - Materials Selection & Parameter Optimization
8. Reliability - Mixed Alloy
9. Reliability - Effect of Coplanarity and Design
10. Reliability - Effect of Ball Size, Via Size, Alloy Type on Stack-up Height & Reliability
11. Reliability - Opens/Head-in-Pillow - The Primary Failure Mode of PoP


Who Should Attend? Anyone who cares about successful implementation of package on package technology, and like to know how to achieve it should take this course.

Ning-Cheng Lee is the Vice President of Technology of Indium Corporation of America. He has been with Indium since 1986. Prior to joining Indium, he was with Morton Chemical and SCM. He has more than 20 years of experience in the development of fluxes and solder pastes for SMT industries, plus experience in underfills and adhesives. He received his PhD in polymer science from University of Akron in 1981, and BS in chemistry from National Taiwan University in 1973. Ning-Cheng is the author of "Reflow Soldering Processes and Troubleshooting: SMT, BGA, CSP, and Flip Chip Technologies", and co-author of "Electronics Manufacturing with Lead-Free, Halogen-Free, and Conductive-Adhesive Materials". He was honored as 2002 Member of Distinction from SMTA, 2003 Lead Free Co-Operation Award from Soldertec, 2006 Exceptional Technical Achievement Award from CPMT, 2007 Distinguished Lecturer from CPMT, 2009 Distinguished Author from SMTA, and 2010 Electronics Manufacturing Technology Award from CPMT.

MP3: Thermal and Mechanical Simulation Techniques for IC Package Yield,
Reliability and Performance

PDC Instructor: Kamal Karimanal, Cielution LLC
$400 (on/before 9/12/2014); $500 (after 9/12/2014)

Course Description: The industry is becoming increasingly aware of the fact that thermal and mechanical factors related to packaging and assembly are crucial hurdles to the enablement of next generation IC and photonic products. These challenges are pervasively felt at all stages of the product development cycle starting from Layout, IC design, power management, assembly processing strategy, package design, and testing. Due to the need to narrow down from a myriad of costly choices even prior to test chip or prototype development, engineering simulation is an important tool at the disposal of the engineer. As a result, engineers from all IC design and packaging background are interested in utilizing thermal and mechanical simulation.

This is an introductory course on thermal and mechanical simulation techniques pertaining to assembly and packaging designed for engineering professionals involved in the enablement of monolithic IC products as well as TSV based 3D stacked SOCs.

Following are the course contents:

- Direct Thermal Modeling Techniques: Steady-State, Transient, tips for non-thermal engineer.
- Compact Thermal Modeling: Applicability of traditional CTM, Novel CTM techniques.
- Overview of mechanical challenges to packaging and assembly: warpage, assembly Yield, CPI effects on Yield & reliability
- Wafer warpage estimation: applicability of Stoney formula, simulation and measurement techniques
- Assembly process modeling techniques: CTE, Reference temperature, Element Birth & Death.
- The concept of Global/Local Modeling: Lumped modeling techniques.
- Mechanical Risk Indicators: Warpage, Stress, Stress Intensity Factors and Energy Release rate.
- Chip level mobility/stress distribution: Contributions from package, TSV and devices.

Who Should Attend? Any Engineering professional involved in the enablement of next generation IC and SOC products with interest in the Thermal and mechanical challenges.

Kamal Karimanal is the Founder of Cielution LLC, which is an Engineering simulation software and services company serving the electronics supply chain. Dr. Karimanal has served in several engineering simulation focused roles at IERC, Fluent Inc., ANSYS Inc., Globalfoundries, and Juniper Networks. Dr. Karimanal has contributed to several detailed and compact modeling methodologies which are being widely used by the electronics industry today. He has written several conference and journal papers and online application notes. Dr. Karimanal received his Ph. D in Mechanical Engineering from The University of Texas at Austin.

 



Thursday, October 16, 2014
All Thursday PDCs are Half-Day Courses (4-hours): 8:00 am - 12:00 pm
10:15 AM - 10:30 AM: Coffee Break in Foyer

THURSDAY HALF-DAY PDCs: (8am-12pm)
- Chip Packaging Processes and Materials;
- Fundamentals of Microelectronics Packaging;
- IC Fabrication and Electronic Packaging;
- Interposers - Silicon, Organic and Glass;
- Packaging and Testing of Implanted Medical Devices;
- Understanding the Common Failure Modes from a Physics of Failure Perspective



T1: Chip Packaging Processes and Materials
PDC Instructor: Syed Sajid Ahmad, North Dakota State University/CNSE
$400 (on/before 9/12/2014); $500 (after 9/12/2014)

Course Description: Myriad of package types require the use of some common and uncommon processes and materials for their manufacture. The course will provide an overview of prevalent processes and materials for conventional and advanced packaging and review their impact on the integrity of finished products. Course will also discuss the quality and reliability metrics, testing methods, failure modes and their resolution.

Who Should Attend? Designers will learn about the assembly processes and their relation to design. Engineers will learn about processes outside their area of expertise. Non-engineering personnel will get introduced to the chip assembly world.

Syed Sajid Ahmad contributed to quality and reliability enhancement of assembly processes at Intel (1979-89), especially wire bond. Ahmad also contributed to packaging development at National Semiconductor (1990) and managed quality at GigaBit/TriQuint (1990-91). His major work at Micron Technology (1991-2003) involved the development and implementation of advanced packaging. At the Center for Nanoscale Science and Engineering, Ahmad's focus is on enhancing research and manufacturing capabilities at the center in the areas of thin film, thick film, chip scale packaging (CSP) and surface mount technology (SMT). Ahmad has 35 international publications and presentations and holds 54 patents.

T2: Fundamentals of Microelectronics Packaging
PDC Instructor: John Pan, Cal Poly State University
$400 (on/before 9/12/2014); $500 (after 9/12/2014)

Course Description: The objective of this course is to introduce materials, processes, and reliability of microelectronics and electronic packaging.

Course outline:

  • Introduction to Microelectronics Packaging
    • Electronics Packaging Hierarchy and Functions
    • Electronics Package Types
    • Electronics Packaging Trends
  • Microelectronics Packaging Materials and Processes
    • Die attachment
    • Wire bonding
    • Flip Chip
    • Encapsulation and Sealing
  • Organic PCB Materials & Processes
    • PCB Materials
    • Multi-layer PCB Fabrication Processes
    • High-density Interconnection
  • Electronics Assembly Processes
    • Surface Mount Assembly (stencil printing, pick and place, and solder reflow)
    • Soldering Basic (solder and solder paste, soldering wetting, solder phase diagrams, and soldering mechanism)
    • Reflow soldering and wave soldering
    • Lead-free solder joint reliability
  • Ceramics Substrate Materials & Processes
    • Ceramics Materials
    • LTCC
    • HTCC

At the end of this course, participants should be able to:

- Describe materials and fabrication processes of multi-layer printed circuit boards and high-density interconnections.
- Describe PCB assembly processes and soldering.
- Describe microelectronics and electronic packaging processes including die attachment, wire bonding, flip chip, and encapsulation.
- Evaluate different packaging substrate materials such as organic, ceramic, LTCC, and HTCC based on electrical, mechanical, and thermal performance as well as cost and reliability.

Who Should Attend? This course is designed for engineers and scientists in R&D, process/product development, and manufacturing who have little knowledge or want to broaden knowledge in materials and processes of microelectronics and electronic packaging.

Dr. John Pan is a professor in Industrial and Manufacturing Engineering Department at California Polytechnic State University, San Luis Obispo. His research interests include the materials, processes, and reliability of microelectronics packaging. He has authored or co-authored over 40 technical papers. He is a Fellow of IMAPS and a recipient of the 2011 IMAPS Outstanding Educator Award. He is currently the Editor-in-Chief of Journal of Microelectronics and Electronic Packaging and an Associate Editor of IEEE Transactions on Components, Packaging and Manufacturing Technology.

T3: IC Fabrication and Electronic Packaging
PDC Instructor: Aicha Elshabini, University of Idaho
$400 (on/before 9/12/2014); $500 (after 9/12/2014)

Course Description: This course serves as an introduction to the fabrication of microelectronic devices.  Topics include the basics of IC structures, clean room protocol, photolithography, film growth and deposition, as well as IC interconnect technologies.  The second portion aims at 1) technical drives and trends including performance, low and effective cost, 2) reliability and yield issues in wirebonding and flip chip bonding originating from chip-to-package, 3) mechanical, metallurgical, chemical failure mechanisms, 4) electrical design and performance analysis, 5) thermal management issues, 6) rework, fluxing, and curing underfill, 7) known a good die, and 8) aspects of electronic packaging to impact the performance of housed electronic devices within the package.

Course Contents: Semiconductor Substrates, Hot Processing, Ion Implantation, Thermal Oxidation, Rapid Thermal Processing, Optical Lithography, Photoresists, Lithographic Techniques, Plasmas, Etching, Evaporation, Sputtering, Chemical Vapor Deposition, Epitaxial Growth, Device Isolation Contacts and Metallization, CMOS and Transistor Technologies.  The second portion of the course aims at substrates (organic, metal, semiconductor,  and ceramic) design and fabrication, surface mount technology (SMT), passive component integration, multichip modules (system in a package & 3D packaging), and first level assembly, clean room protocol, electrical, mechanical, and thermal design, simulation, and process considerations

Distinguished Professor Aicha Elshabini, Ph.D., P.E., IEEE Fellow, IMAPS Fellow Academic Advisor of IMAPS, NSBE, and SWE. Elshabini graduated from Cairo University, Egypt, Communications and Electronics, B.Sc., ECE, 1968-1973, from Toledo University, Toledo, Ohio, Microelectronics, M.S.E.E., 1973-1975, and from Colorado University, Boulder, Colorado, Solid State Physics, Devices, and Optoelectronics, Ph. D., ECE, 1975-1978/1979.

International Society for Hybrid Microelectronics (ISHM), Currently named IMAPS, Fellow Member Elected (1993) for "Continuous Contribution to Microelectronics & Microelectronics Industries".IMAPS Publication Committee, Member 1990-2001, and Chair, 2001-2005. Founding Editor of the International Journal of Microcircuits and Electronic Packaging, IMAPS, 1991-2001.Academic Advisor for IMAPS, NSBE, and SWE (Society for Women Engineers).Elshabini was awarded the 1996 John A. Wagnon Technical Achievements Award from IMAPS. She was awarded the 2006 Daniel C. Hughes Memorial Award from IMAPS, and in 2007, the Outstanding Educator Award. With this third award from IMAPS Dr. Elshabini became the first woman to earn three top awards from IMAPS in its 40 year history.

T4: Interposers - Silicon, Organic and Glass
PDC Instructor: Venky Sundaram, Georgia Tech PRC
$400 (on/before 9/12/2014); $500 (after 9/12/2014)

Course Description: This course provides the most comprehensive summary of interposer technologies, market drivers, application examples and infrastructure evolution, covering silicon, organic and glass interposers. Interposers bridge the interconnect gap between back end of the line (BEOL)pitch and current organic BGA packages. Interposers started out as a 2.5D multi-die integration step towards full 3D IC stacking. However, they are now viewed as a system integration platform with pervasive applications in smart mobile, cloud computing and networking, photonics, analog/power, MEMS, sensors, RF/mm-wave, medical electronics and many other applications. In the past couple of years, the technology development and manufacturing infrastructure maturity has been progressing rapidly. This year's PDC by one of the top interposer experts in the world, includes significant new material covering the latest advances in 2.5D and 3D interposers. The course will address both fundamentals of interposer technology, as well as applications and supply chain infrastructure. An extensive review of three major interposer options being pursued, namely, silicon, organic and glass, will be provided. The course will be interactive and include audience Q&A and samples of latest interposer demonstrators will be passed around for a hands-on experience.

Who Should Attend? This is a must attend course for anyone interested in state-of-the-art interposer technologies. The course is especially valuable to semiconductor, electronics systems, and packaging industry personnel in engineering, management, corporate technology strategy, pathfinding and marketing teams.

Dr. Venky Sundaram is a Research Professor and manages the Industry Research Programs at the 3D Systems Packaging Research Center (PRC), Georgia Tech. He is the Program Director for the largest Low Cost Glass Interposer & Package (LGIP) industry consortium with more than 30 active global industry members. He is a globally recognized expert in 3D systems packaging, and has pioneered major technologies including embedded RF passives in organic substrates, chip-last die embedding and glass interposers. His research expertise is in the areas of System on a Package (SOP) technology, 3D packaging and integration, ultra-high density interposers, embedded components, bio-medical device packaging, LED packaging and systems integration research. He has mentored more than 15 PhD and MS students, and teaches a laboratory course every Fall on SOP Substrates, ECE/MSE 4755. He is a co-founder of Jacket Micro Devices, an RF/wireless start-up acquired by AVX. Dr. Sundaram has served as session chair at major global packaging conferences, serves on the Advanced Packaging Committee of SEMI, is the co-chairman of the IEEE CPMT Technical Committee on High Density Substrates, serves on the Editorial Advisory Board of Chip Scale Review magazine, and is in the Executive Council of IMAPS as Director of Education Programs. Dr. Sundaram has won several best paper awards and has 15+ patents and 150+ publications. He received his BS from IIT Mumbai, and MS and PhD in Materials Science and Engineering from Georgia Tech.


T5: Packaging and Testing of Implanted Medical Devices  
PDC Instructor: Thomas J Green, TJ Green Associates LLC
$400 (on/before 9/12/2014); $500 (after 9/12/2014)

Course Description: Hermetic and non-hermetic packaging and testing of microelectronics, sensors, MEMS, hybrids and microwave components for use as implanted Class II/III devices in vivo is of critical importance. Cost, reliability, small form factors, biocompatibility and patient safety are driving concerns. This course begins with an overview of traditional hermetic packaging and testing approaches that have been in use for over forty years. Most pacemakers, IPGs, cochlear implants in use today follow a prescribed and proven path of hermetic sealing and testing to assure product reliability and patient safety, which includes hermeticity testing in accordance with MIL-STD-883 Test Method 1014.

Today however, the research is directed at development of a non-hermetic package that is at least as good as the proven path. Packages made from polymeric materials require a different approach from a manufacturing and testing standpoint. The problem is now one of moisture diffusion through the barrier and package interfaces. Candidate materials such as parylene, PDMS, various ALD and CVD organic and inorganic coatings, LCP, silicones etc. are reviewed and application processes discussed. How to test and evaluate.

Who Should Attend? This course is intended as an introductory to intermediate level course for process engineers, designers, quality engineers, and managers responsible for package seal, hermeticity testing and for those responsible for evaluating non-hermetic packages.

Mr. Thomas Green is the principle at TJ Green Associates LLC (www.tjgreenllc.com) a veteran owned small business focused on training and consulting for military, space and medical microelectronic devices. He teaches a variety of public courses around the globe and in plant at major corporations and consults for a variety of medical device companies. He has thirty two years of experience in microelectronics working at positions in industry, academia and government. Tom has demonstrated expertise in die attach, wirebond, visual inspection, hermetic seal and leak testing processes. He has gained valuable experience over the past ten years in packaging and testing of devices for use as Class III medical implants and is often called on as an expert witness for hermeticity related failures. Tom is an active IMAPS member and Society Fellow. He has a B.S. in Materials Engineering from Lehigh University and a Masters from the University of Utah.

T6: Understanding the Common Failure Modes from a Physics of Failure Perspective
PDC Instructor: Greg Caswell, DfR Solutions
$400 (on/before 9/12/2014); $500 (after 9/12/2014)

Course Description: There are numerous failure modes and mechanisms that can impact a product. Understanding how they occur and how to obviate them during the design stage can vastly improve a product's ability to withstand the rigors of its intended environment.

This course will address the common failure modes associated with printed circuit boards, passive components, Integrated Circuits, High Brightness LEDs, QFNs, CSPs, PoP, and MEMs along with the effects of long term storage of components.
Physics of Failure (PoF) is a proactive science based philosophy that addresses material science, physics and chemistry and provides the basis for the student to develop an up-front understanding of failure modes/mechanisms. Knowing how things fail is equally important to understanding how and why things work by enabling engineers and designers to be knowledgeable about root causes of failures so that they can be designed out in new products.

PoF provides a scientific basis for evaluating usage life and hazard risks for new materials, structures and technologies when exposed to their actual operating conditions.

Examples of each failure mode/mechanism will be illustrated along with insight into methods for obviating them

Who Should Attend? Engineers or managers who would like to have a better understanding of Physics of Failure and the types of issues that can be encountered in circuit boards, passive components, ICs, LEDs, PoP packaging, MEMs, as well as the issues associated with solder wearout, long term storage reliability, tin whiskers, etc.

Greg Caswell is widely recognized as a pioneer in surface mount technology (SMT) and has 42 years of experience in the electronics industry. In his current position he is a Sr. Member of the Technical Staff for DfR Solutions. Greg has been involved with IMAPS in numerous capacities: 1984 Centex Chapter President, 1986 ISHM Vice President, 2001 President of the IMAPS, 1989-2000 ATW Chairman, 2008 GBC Chair, 2007 General chair for Symposium, and 2009-2012 Editor Advancing Microelectronics. He has received the IMAPS Technical Achievement (1986), Fellow of the Society (1993), and Daniel C Hughes Memorial Award (1995). He received his Bachelor of Science in Electrical Engineering from Rutgers University and also has a Bachelors in Management from St. Edwards University in Austin.

 

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PDC registration is listed under SESSIONS during the on-line registration process

 


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