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IMAPS 2015 - Orlando
Advanced Packaging & the Internet of Things: The Future of Our Industry

IMAPS 2015 - Orlando

October 27-29, 2015
October 27-28, 2015
Professional Development Courses &
Welcome Reception :
October 26, 2015
General Chair:
Urmi Ray
Qualcomm, Inc.
Technical Chair:
Erica Folk
Northrop Grumman Corp.

Technical Committee:
Technical Co-Chair - USA:
Dan Krueger
Honeywell FM&T
Technical Co-Chair - Europe:
Andre Rouzaud
Technical Co-Chair - Asia:
Woong-Sun Lee
SK Hynix, Inc.
Assistant Technical Co-Chair - USA:
Mary Cristina Ruales Ortega,
University of Missouri
Tim Mobley, Triton Micro Tech
Assistant Technical Co-Chairs - Europe:
Gabriel Parès, CEA LETI
Steffen Kroehnert, Nanium
Assistant Technical Co-Chairs - Asia:
Yu-Hua Chen, Unimicron
Won Kyoung Choi, Stats ChipPAC

Early Registration and Hotel Deadline: September 30, 2015

Professional Development Courses (PDCs - Short Courses)

Monday, October 26: full-day courses, running 10:00 am - 6:00 pm;
Monday, Half-day courses: 10:00am - 1:45pm & 2:15 pm - 6:00 pm

MONDAY FULL-DAY PDCs: (10am-6pm)
M1: Introduction to Microelectronics Packaging - Thomas J. Green, TJ Green Associates LLC
M2: Understanding the Wire Bonding Process - Lee Levine, Process Solutions Consulting
M3: Electrical Design and Fabrication Processes of Glass and Silicon Interposers - Ivan Ndip, Michael Toerrer, Fraunhofer IZM
M4: Polymers in Electronic Packaging - Jeff Gotro, InnoCentrix, LLC
M5: MEMS and the Internet of Things - Slobodan Petrovic, Oregon Institute of Technology

AM1: Emerging Challenges in Packaging - Raja Swaminathan, Intel Corporation
AM2: Improving Mechanical, Electrical, and Thermal Reliability of Electronics Assemblies - Tim Jensen, Indium Corporation
AM3: Introduction to the Design and Fabrication of RF, High Speed and Microwave hybrids, MCM’s and Modules - Tom Terlizzi, GM Systems LLC
AM4: Technology of Screen Printing - Art Dobie, Chromaline & David Malanga, Heraeus Electronics
CANCELLED -- AM5: ENIG - Controlling Electroless Nickel & Immersion Gold Plating for Electronics: From Plating Solutions and Equipment Maintenance to How to Audit Your Supplier - Fred Mueller, General Magnaplate Corp.

PM1: Introduction to Fan-Out Wafer Level Packaging - Beth Keser, Qualcomm Technologies, Inc.
PM2: Process Flows for Electronics Packaging – Technology Comparisons & Cost and Yield Analyses - Chet Palesko, SavanSys Solutions LLC & E. Jan Vardaman, TechSearch International, Inc.
PM3: Crash Course on Packaging Technologies and Thermal Design of ICs - Herman Chu, Juniper & Li Li, Cisco System
PM4: Reliability 360: How to Verify Design Robustness Early in the Process - Greg Caswell, DfR Solutions
PM5: Adhesion Science & Practice with an Emphasis on Temporary Bonding of Electronics (Wafers, Displays, Devices) - John Moore, Jared Pettit, Alman Law, Alex Brewer, Daetec, LLC



Get off line and learn Face to Face...Sign up for a PDC!

PDCs (Professional Development Course) are a big part of the Annual IMAPS Symposium each year. Why not plan to take a course on Monday before IMAPS 2015 kicks off and take advantage of the rich learning opportunities available at the IMAPS symposium. This year the Monday courses are going to have a delayed start kicking off at 10 AM and running till 6 PM with a working lunch. This new time slot will give the locals a chance to beat the traffic and a little extra time for the out of town folks to get organized and prepare for a full day of learning.

PDCs create a unique environment whereby students can personally interact with the instructors, and with each other in the classroom and over lunch. It's mentally stimulating and the new found professional connections will prove to be valuable in the long run. Learning on line is fine, but it cannot duplicate hours spent immersed in a specific topic, led by an industry expert in the field and surrounded by like-minded professionals.

This year we've put together another impressive assortment course options Our goal is to make the IMAPS PDCs the premier learning experience; so we ask that you take time to fill out the evaluation form that accompanies each course and give us your feedback on this or any other aspects of the PDCs. Read through the course descriptions on line and pick the course that best suits your company and career objectives. Every PDC includes a full set of comprehensive course notes. Class sizes typically range from five to thirty students and there is always ample time for questions. We hope you will consider joining us in Orlando for a learning experience like no other.

Education is a lifelong pursuit, don't miss out on this opportunity!
Tom Green, James McEwen, and Tom Terlizzi
IMAPS 2015 PDC Co-Chairs


Your PDC Registration Fee Includes:

  • "Working Lunch" (box lunch in PDC room) on the day of your course (Monday full-day & Morning PDCs only)
  • Refreshment breaks
  • Hard-copy workbook of course materials (no electronic copies provided)

Monday PDC Lunch sponsored by:
Heraeus Materials Technology - Premier Sponsor, Gold

during IMAPS 2015 Online Registration

PDC Cancellation policy: IMAPS reserves the right to cancel a course if the number of attendees is not sufficient.
You can transfer to a different course or we will refund you the corresponding amount.

Monday, October 26, 2015

Full-Day PDCs run 10:00 am - 6:00 pm
MORNING Half-Day PDCs run 10:00 am - 1:45 pm

AFTERNOON Half-Day PDCs run 2:15 pm - 6:00 pm

PDC "Working Lunch" for Full & Morning Classes: 12:00-1:00pm
(Pickup box lunch & return to room)
PDC Afternoon Coffee Break in Foyer: 3:30-3:45pm

PDC Coffee Breaks & Lunch sponsored by:
Heraeus Materials Technology - Premier Sponsor, Gold

MONDAY FULL-DAY PDCs: (10am-6pm)
M1: Introduction to Microelectronics Packaging - Thomas J. Green, TJ Green Associates LLC
M2: Understanding the Wire Bonding Process - Lee Levine, Process Solutions Consulting
M3: Electrical Design and Fabrication Processes of Glass and Silicon Interposers - Ivan Ndip, Michael Toerrer, Fraunhofer IZM
M4: Polymers in Electronic Packaging - Jeff Gotro, InnoCentrix, LLC
M5: MEMS and the Internet of Things - Slobodan Petrovic, Oregon Institute of Technology

M1: Introduction to Microelectronics Packaging
PDC Instructor: Thomas J. Green, TJ Green Associates LLC
$600 (on/before 9/30/2015); $700 (after 9/30/2015)

Course Description: The instructor begins by broadly describing packaging terminology and reviews the alphabet soup of acronyms used throughout the electronics industry; terms such as: DIP, LCC, QFN, Hybrids, BGA, CSP, Flip Chip, 3D, TSV, WLP,SIP etc. The technology is then broken down by industry segments, beginning with high volume commercial packaging technology used in cell phones, tablets and handheld wireless devices, automotive, telecom, Internet of Things (IoT) and then progressing onto specialized packaging for low volume complex devices used in military/space/medical products as well as, RF microwave circuits, optoelectronics, LEDs and next generation packaging of MEMS and sensors. Lots of pictures, short video clips and pass around samples, along with simple explanations will help the attendee understand the technology drivers and key aspects of microelectronic packaging technology in a fun and interactive way.

Besides a good overview the student will understand the basics of how to assemble and package single and multi-chip microcircuits, with a focus on the materials and processes and the associated equipment sets needed to support the industry. Wafer processes, probing and dicing, substrate selection, interposers, die attach using solders and epoxy, Au/Al/Cu wirebond processes,flip chips underfills, encapsulations, dam and fill, glob tops, transfer molding and hermetic packaging are all be reviewed with an eye on the important technical issues and industry drivers.

Advanced packaging concepts and emerging trends at the wafer level will also be addressed. In addition, fine pitch copper pillar processes, wafer level flip chip underfill, wafer capping of MEMS, 3D-IC TSV, 2.5D with silicon and glass interposers, Fan-In/Fan-Out WLP. Current hot topics and future industry trends will finish out the day and there will be plenty of time for questions.

Who Should Attend? This overview course is intended for those unfamiliar with microelectronics packaging technology. People in sales, purchasing, program management, new engineers, managers, equipment/material suppliers, people new to this industry or anyone looking to get a broad industry overview and review of the industry drivers, history and future trends are welcome to attend.

Mr. Thomas Green is the principle at TJ Green Associates LLC ( a veteran owned small business focused on training and consulting for military, space and medical microelectronic devices. He teaches a variety of microelectronics packaging courses around the globe and in plant at major corporations and consults for a variety companies in the military/industrial and medical device industries. He has thirty two years of experience in microelectronics working at positions in industry, academia and government. Tom has demonstrated expertise in die attach, wirebond, visual inspection, hermetic seal and leak testing processes. Tom is an active IMAPS member and Society Fellow. He has a B.S. in Materials Engineering from Lehigh University and a Masters from the University of Utah. Tom is the principal at TJ Green Associates LLC .

M2: Understanding the Wire Bonding Process
PDC Instructor: Lee Levine, Process Solutions Consulting
$600 (on/before 9/30/2015); $700 (after 9/30/2015)

Course Description: Wire Bonding is a welding process that is the dominant chip interconnection method. More than 15 trillion wires are bonded annually. In the past gold wire was predominant but this year copper and palladium coated copper wire will capture more than 51% of the total market. Copper provides benefits in cost, improved conductivity, stiffness and reliability. However, it is significantly harder than gold and achieving a robust, reliable process is a challenge. Wire bonding high-volume lead-frame often experiences defect rates below 10ppm, this presents a significant barrier to entry for any process competitor but copper is meeting the challenge.

The flexibility, reliability and yield of wire bonding make it a process worthy of careful study. Today’s wire bonding equipment is capable of producing 24 wires/second (48 welds) with bond placement accuracy of ±2.0µm. During the descent of the tool the bond head has an acceleration of >300g. Achieving highly repeatable bonds with the stated bond placement accuracy and yet accelerating at 300g requires exceptional engineering design. As a result the wire bonder has evolved into one of the worlds most advanced machines. It requires high speed pattern recognition, ultra-light (for speed and acceleration), stiff (for accuracy and repeatability) sub-assemblies (imagine trying to achieve the same speed and accuracy with a graphite fishing rod), and state-of-the-art control systems.

The course will cover:

• Introduction • A snapshot of some microelectronic packages • Size of the market • Cost of a wire bond • Ultrasonic Welding • Intermetallics • Bond Testing • Copper wire bonding • Looping and Ball Formation • Wire • Fine Pitch Bonding • Plating • Wire Bond variations (ball bumping)

Who Should Attend? Process and materials engineers, technicians, managers associated with and responsible for wire bond assembly.

Lee Levine is a consultant for Process Solutions Consulting, Inc. where he provides process engineering consultation, SEM/EDS analysis, and wire bond training. Lee’s previous experience includes 20 years as Principal and Staff Metallurgical Process Engineer at Kulicke & Soffa and Distinguished Member of the Technical Staff at Agere Systems. He has been awarded 4 patents, published more than 70 technical papers, and in 1999 won the John A. Wagnon Technical Achievement award from the International Microelectronics and Packaging Society (IMAPs). Major innovations include copper ball bonding, loop shapes for thin, small outline packages (TSOP and TSSOP, and CSPs) and introduction of DOE and statistical techniques for understanding semiconductor assembly processes. He is an IMAPS Fellow and a senior member of IEEE. He is a Contributing Editor for TAP Times, ( an online packaging newsletter.

M3: Electrical Design and Fabrication Processes of Glass and Silicon Interposers
PDC Instructors: Ivan Ndip & Michael Toepper, Fraunhofer IZM
$600 (on/before 9/30/2015); $700 (after 9/30/2015)

Course Description: Due to their multitude of advantages in advanced packaging and electronic system integration, glass and silicon interposers have received widespread attention from both academia and industry in recent years. However, in order to fully exploit the cost and performance advantages of these innovative technologies, a good understanding of their electrical design and fabrication processes is required.

The goal of this course is to provide and illustrate the fundamentals of efficient electrical design, and fabrication processes of glass and silicon interposers for applications ranging from 100 MHz right up to millimeter-wave frequencies. The properties of dielectric materials and packaging structures used for fabricating these interposers will first be presented. Their fabrication processes will then be extensively discussed. This will be followed by an illustration of the electrical design challenges of glass and silicon interposers. Convectional design techniques from academia and industry will be briefly discussed, and a holistic design approach will be presented. A comparative analysis between transmission lines in glass and silicon interposers as well as between Through Silicon Vias (TSVs) and Through Glass Vias (TGVs) will be given. Finally, examples of glass and silicon interposers designed, fabricated and characterized at Fraunhofer IZM will be presented.

Who Should Attend? Designers, researchers, managers and students involved in the process of electrical design, layout, processing, fabrication and/or system-integration of interposers and electronic packages.

Ivan Ndip received his M.Sc. and Ph.D. degrees in electrical engineering from the Technical University (TU) Berlin, Germany. In 2002, he joined Fraunhofer-IZM as a Research Engineer and worked on signal integrity modeling/design and on antenna design/integration. From 2005 to 2015 he was a Group Manager. Since 2014, he has been Head of the Department of RF & Smart Sensor Systems at IZM, where he leads R&D activities pursued in four Groups. Since 2008 Ivan has been teaching graduate courses at TU Berlin. He currently teaches EMC in RF/High-Speed Systems. He taught PDCs at the 43rd, 44th, 45th and 46th International Symposiums on Microelectronics in USA. He also taught PDCs at the ECTC conference from 2012 to 2014, and will be teaching a PDC at ECTC 2015 in San Diego, CA. Ivan has more than 130 publications in referred journals/conference proceedings, and has won many best-paper awards. He is a recipient of the Tiburtius-Prize, awarded yearly for outstanding Ph.D. dissertations in the State of Berlin, and also the recipient of the 2012 Fraunhofer-IZM Research-Award. He chairs the Signal/Power Integrity Committee at IMAPS. Ivan is a Senior Member of IEEE and Fellow of IMAPS.

Michael Toepper studied Chemistry (Diploma) and earned a PhD in Material Science. Since 1994 he is at the joint institutes Fraunhofer IZM and TU Berlin currently heading research projects in the area of WLP with a focus on polymeric materials. In 2006 he was a visiting professor at the University of Utah in Salt Lake City. Michael is the Technical Chair of IEEE-CPMT for WLP and was on the ECTC committee for emerging technologies for 5 years. He taught PDCs at the ECTC conference from 2012 to 2014, and will be teaching a PDC at ECTC 2015 in San Diego, CA. He has published 4 book chapters and is author and co-author of over 200 technical publications and conference presentations. Michael is a Senior Member of IEEE.

M4: Polymers in Electronic Packaging
PDC Instructor: Jeffrey Gotro, InnoCentrix, LLC
$600 (on/before 9/30/2015); $700 (after 9/30/2015)

Course Description: The course will provide an overview of polymers and the important structure-property-process-performance relationships for electronic packaging. The main learning objectives will be 1) understand how polymers are used in electronic packaging, 2) learn why specific chemistries are used depending on the application 3) learn the fundamentals of polymer characterization related to electronic packaging 4) develop a foundation in rheology and rheology issues in electronic packaging.

Topics to be covered are thermosetting polymers, curing mechanisms (heat and light cured), network formation, and an overview of key chemistries used (epoxies, acrylates, polyimides, bismaleimides, curing agents, and catalysts). The course will provide a more in-depth discussion of the chemistries, material properties, and process considerations for adhesives (both paste and film), capillary underfills, packaging substrate materials, encapsulants (mold compounds), and coatings. Characterization using thermal analysis will be covered allowing understanding of structure-property relationships. The final portion of the PDC will provide an introduction to rheological characterization methods (various types of rheometers and viscometers) and the properties of adhesives (shear thinning, viscosity, time dependence, and rheology changes during curing), underfills, and mold compounds. Participants are invited to bring problems for discussion.

Who Should Attend? Product development scientists, manufacturing engineers, and packaging engineers involved in the development, production, and reliability testing of electronic packages would benefit. Those interested in gaining a basic understanding of the role of polymers and polymer-based materials used in electronic packaging will also find this PDC valuable.

Dr. Jeff Gotro has over thirty two years of experience in polymers for electronic applications and composites having held scientific and leadership positions at IBM, AlliedSignal, Honeywell, and Ablestik Laboratories. Jeff is an expert in thermosetting polymers and has received invitations to speak at prestigious Gordon Research Conferences (Thermosetting Polymers and Composites). He has presented numerous invited lectures and short courses at technical meetings, has over 60 technical publications and 21 patents/patent applications. Jeff was an Adjunct Professor at Syracuse University in the Dept. of Chemical Engineering and Materials Science from 1986-1993. Jeff is a member of the American Chemical Society (ACS), the Institute for Management Consultants (IMC), the Forensic Expert Witness Association (FEWA), Society of Plastics Engineers, and the International Microelectronics Aseembly and Packaging Society (IMAPS). Jeff was awarded the IMAPS John A. Wagnon Jr. Technical Achievement Award in 2014 and elected as IMAPS Fellow.

M5: MEMS and the Internet of Things
PDC Instructor: Slobodan Petrovic, Oregon Institute of Technology
$600 (on/before 9/30/2015); $700 (after 9/30/2015)

Course Description: This is a full-day, 2-part course on MEMS and the Internet of Things: Principles, Applications, Power Supplies and Device Packaging. While the full-day course is recommended, the participants can sign-up for either of the sections as well. The first section of the course will give MEMS and nanoMEMS overview. The second section will cover: Internet of Things: MEMS opportunities and challenges.

This full day course will explore concepts that combine MEMS, nanoMEMS and the Internet of Things. Device packaging will be the constant theme throughout the course. The merging of nanoscience and microelectromechanical systems presents an opportunity for development of next generation technologies for use in computers, wireless communication, biomedicine, and a variety of sensors. These technologies will then have an enormous opportunity for growth as critical part of the concept called Internet of Things, where the Internet is connected to a physical world through omnipresent MEMS or nanoMEMS sensors. These sensors, electronics and software are part of the network of physical objects or "things". In principle, MEMS or nanoMEMS sensors detect the physical world, e.g., temperature, pressure, motion, sound, humidity, or chemical and biological inputs, and wirelessly connecting them to the Internet. The systems will also perform actions and MEMS actuators will provide control and actuation capabilities over the "thing" or objects.

The broad areas that the IoT will encompass are environmental monitoring and control, infrastructure management, manufacturing, energy management, medical and healthcare systems, building and home automation, transportation, and other large scale deployments. All these devices will create a cluster where every sensory change will be communicated to the application processor through the Internet using radio-frequency identification. The data is then processed and appropriate action is taken. The IoT is a major opportunity for MEMS. Billions of MEMS and nanoMEMS devices will be in the heart of this communication revolution that has already started and which value is expected to reach US$1 trillion by the end of the decade.

Part I: MEMS and nanoMEMS overview
The first part of the course will give an overview of MEMS and nanoMEMS principles of operation, materials, fabrication methods, and in particular the packaging used in building devices. Variety of MEMS devices will be discussed while a particular emphasis will be placed on MEMS sensors and actuators used in industrial, medical, and automotive applications. In this part, the nanomaterial synthesis and characterization methods will be explored and highly speculative discussion will offer a possibility for using nanoscale phenomena for technological purposes related to MEMS. The emphasis will be placed on merging the nanoscience with MEMS fabrication principles, design considerations, integration aspects, and packaging.

Part II: Internet of Things: MEMS opportunities and challenges
In the second section, the general concepts of the Internet of Things will be discussed first, followed by examples and case studies from many different MEMS device applications. MEMS requirements and challenges will be examined. Particular emphasis will be placed on the packaging of MEMS and nanoMEMS devices for IoT and on the integration of power supplies and energy storage devices. The opportunities for energy production and storage using nanoscience will be presented, in particular nanoscale batteries, fuel cells, hydrogen production, solar cells, and biological materials for energy production.

Who Should Attend? The course is open to anyone with general understanding of the physics, chemistry, and material science. The participants will have the opportunity to explore highly speculative, futuristic concepts and develop visionary views of the technological possibilities using micro and nano technology in the revolutionary concept of the Internet of Things. The course is open to participants with no prior MEMS, nantotechnology, or power sources knowledge and would provide a reasonably broad general introduction into all three areas of technology.

Dr. Slobodan Petrovic is an associate professor at the Oregon Institute of Technology in Portland, OR. His research interests are in the areas of MEMS fuel cells, sensor media compatibility, hydrogen generation and storage, and dye-sensitized solar cells. Prior to that, he was at the Arizona State University, where he taught courses in MEMS, Sensors, and alternative energy. Dr. Petrovic also held appointments at Clear Edge Power as a Vice President of Engineering; at Neah Power Systems as Director of Systems Integration; and Motorola, Inc. as a Reliability Manager. Dr. Petrovic has over 25 years of experience in MEMS, sensors, energy systems; fuel cells and batteries; and electrochemical solar cells. He has over 50 journal publications and conference proceedings; 2 book contributions and 24 pending or issued patents.



AM1: Emerging Challenges in Packaging - Raja Swaminathan, Intel Corporation
AM2: Improving Mechanical, Electrical, and Thermal Reliability of Electronics Assemblies - Tim Jensen, Indium Corporation
AM3: Introduction to the Design and Fabrication of RF, High Speed and Microwave hybrids, MCM’s and Modules - Tom Terlizzi, GM Systems LLC
AM4: Technology of Screen Printing - Art Dobie, Chromaline & David Malanga, Heraeus Electronics
CANCELLED -- AM5: ENIG - Controlling Electroless Nickel & Immersion Gold Plating for Electronics: From Plating Solutions and Equipment Maintenance to How to Audit Your Supplier - Fred Mueller, General Magnaplate Corp.

AM1: Emerging Challenges in Packaging
PDC Instructor: Raja Swaminathan, Intel Corporation
$400 (on/before 9/30/2015); $500 (after 9/30/2015)

Course Description: The course will begin with a broad description of electronic packaging types, functions, trends per industry to introduce the basic concepts of packaging. The first half of the course will focus on the key elements driving the definition of package architectures including form factor, z-height, cost, functional integration complexity, power delivery, high speed signaling and thermo-mechanical interactions with system, to name a few. The interactions between these elements towards enabling a successful package architecture for a given product will be reviewed with examples from different product segments (phones, tablets, PCs, servers etc.). The second half of the course will focus on the package, assembly, test and silicon integration and surface mount challenges towards enabling high volume manufacturing of the package architectures.

Who Should Attend? The attendees are expected to have an in depth understanding of the fundamentals of packaging.

Dr. Raja Swaminathan is an IEEE senior member and is a package architect at Intel for next generation server, client and SOC products. His primary expertise is on delivering integrated HVM friendly package architectures with optimized electrical, mechanical, thermal solutions. He is an ITRS author and iNEMI technical WG chair on packaging and design. He has also served on IEEE micro-electronics and magnetics technical committees. He has 13 patents and 18 peer reviewed publications and holds a Ph.D in Materials Science and Engineering from Carnegie Mellon University.

AM2: Improving Mechanical, Electrical, and Thermal Reliability of Electronics Assemblies
PDC Instructor: Tim Jensen, Indium Corporation
$400 (on/before 9/30/2015); $500 (after 9/30/2015)

Course Description: Electronics today have much more demands on them than they did just a few years ago. With legislative restrictions on materials, increasing needs in functionality, and the requirements to fit small form factors, there are many new challenges facing engineers. This course is designed to provide practical knowledge that can be applied to current processes to improve the overall reliability of the electronics assemblies. It will not focus on mathematical modeling but rather provide data and tools that can be used by process engineers and designers to make immediate changes to the process which will result in a higher reliability product.

Course Outline:
1. Mechanical Reliability
-Drop shock vs. thermal cycling vs. vibration
-Alloys and element addition impact
-Board and component finish impact
-Component and board warpage
-Increased solder volume

2. Electrical Reliability
-Cleaned vs. No-Clean fluxes
-SIR and Electromigration - Dendritic growth
-Impact of low stand-off components (i.e. QFNs)
-Creep corrosion
-Conformal coating
-Sn whiskering

3. Thermal Reliability
-Types of thermal interface materials
-Assessing thermal conductivity
-Bond line thickness
-Impact of pressure
-Pump-out considerations
-Solder joint thermal interfaces and voiding

Who Should Attend? Process engineers, quality engineers, design engineers, and engineering management

Tim Jensen is the product manager for Indium Corporation’s Engineered Solder Materials, the company’s most diverse product group. His product group encompasses solder preforms, wire, ribbon, and foil, and thermal interface materials, including gold-tin and tin-lead solder preforms, Solder Fortification® preforms, Heat-Spring® thermal interface materials, and indium-containing preforms. He is responsible for ensuring the product line best meets the needs of the customers. Tim joined Indium Corporation in 1997 and has held a number of positions, including senior technical support engineer, Pb-free programs manager, and, most recently, global product manager for PCB assembly materials. Tim has worked directly on hundreds of surface mount lines, and developed thousands of different products. Using that direct knowledge and expertise he worked closely with Indium Corporation’s technical service, sales, and research and development teams to develop cutting edge products that address the unique challenges faced by the electronics assembly industry. Tim has authored numerous technical papers on solders and soldering technology. Tim has a bachelor’s degree in chemical engineering from Clarkson University and has his MBA at Syracuse University. He lives in New Hartford, N.Y.

AM3: Introduction to the Design and Fabrication of RF, High Speed and Microwave hybrids, MCMs and Modules
PDC Instructor: Tom Terlizzi, GM Systems LLC
$400 (on/before 9/30/2015); $500 (after 9/30/2015)

Course Description: The course presents electrical/physical design, manufacturing, materials, quality and reliability information in terms understandable to engineering and non-engineering personnel. RF Packaging history, characteristics and drivers will be outlined. Types of packages (IC, chip scale, MMIC, MEMS, Hybrid, MCM, Flip Chip, BGA, Plastic, Aluminum and Kovar housings) and substrates (Thick and thin film, HTCC, LTCC ceramic, organic) and critical differences among them and their High Frequency applications (Microstrip, Stripline, Coplanar will be discussed. RF and Microwave layout and the commonly used design tools and software will be outlined. The course will look at the design selection to meet use and application environments. Step-by-step manufacturing flow for different packages and products will be presented as an example to understand the complexity of processes, materials and equipment involved in their manufacture. RF & Microwave packaging concepts will be introduced and the tradeoffs of different interconnect methodology (connectors, wire bonds, ribbon bonds, AuSi & AuSn eutectic, soft solder and epoxy. Materials selection with respect to thermal resistance will be discussed. Finite Element and reliability software will be discussed to insure the design will perform to specification. Quality and reliability issues related to RF packaging and their present and future solutions will be outlined.

Who Should Attend? It will help the attendees to understand the application and assembly of RF and Microwave microelectronic package technology on the next level interconnect and the service environment that microelectronic packages must protect its components. Personnel (Design engineers and process engineers) entering the RF microelectronic packaging field will have a critical look at the electrical design, physical design, layout quality, reliability and material issues related to the development and manufacture of microwave modules.

Tom Terlizzi is VP Business development at Agile Microwave Technology Inc. and has a consulting business, GM Systems LLC, in Microelectronic Design, Marketing/Sales, Technology strategy and Product development. He has designed and developed Power management systems, Single board computers, microelectronic circuits, hybrids, COB modules, ICs, RF and Microwave modules, for over 30 years for military, aerospace, telecom and consumer markets as a VP/GM, Director of Marketing, Chief Engineer, Operations/Engineering manager at Aeroflex, Norden/UTC, General Instrument (Microchip) and Grumman. He spearheaded acquisitions of several “high-tech” companies, ISO9000/Mil-PRF-38534 quality certifications. He received a BEE (CCNY), a MSEE (NYU-Poly) & has published several articles, papers and tutorials at international conferences, edited books on electronic packaging, consulted for the DoD on advanced RF electronic packaging, Metro ISHM Chapter President (1983). With TJ Green Associates has given a 3-Day seminar on Microwave Packaging Technology and also writes a Blog for EDN Magazine Online - Looking @ electronics. Tom has also co-chaired the New England IMAPs Symposium on RF and Microwave for the last two years.

AM4: Technology of Screen Printing
PDC Instructors: Art Dobie, Chromaline & David Malanga, Heraeus Precious Metals North America LLC
$400 (on/before 9/30/2015); $500 (after 9/30/2015)

Course Description: Screen printing continues to offer innovative and cost effective solutions to the increasing demands for higher circuit densities. This course is intended to increase the understanding of the screen printing process, thereby improving production yield and print quality.

Presented are some of the latest advancements in composition, screens, and printing technology that enable screen printing to meet future circuit density requirements as well as the definition required for microwave circuitry. The advantages of screen printing, an additive deposition process, are described and compared to alternative more costly and "less-green" subtractive deposition technologies. This course is applications-oriented in terms of how to optimize the screen printing process; how to use and specify screen correctly; rheology properties that affect print results; minimizing printing defects and trouble-shooting problems related to screens, inks and the printing process itself.

Who Should Attend? This course is specifically targeted for production and process engineers, plant and production managers, supervisors, and all others interested in learning how to optimize and increase the use of the screen printing process for material deposition.

Art Dobie is the Northeast Technical Rep for Chromaline, a Duluth MN chemical company specializing in emulsion and related chemicals used in screen printing applications. Art has been in the electronics screen printing industry for 34 years since receiving his BS in Screen Printing Technology in 1980 from California University of Pennsylvania, and has co-instructed the IMAPS "Technology of Screen Printing" PDC since its inception in 1991. He has delivered numerous technical presentations to screen-printing professionals at local, national and international level symposia. Mr. Dobie is a Life Member and Fellow of the Society of IMAPS, and received the 2006 IMAPS Technical Achievement Award for outstanding technical contributions to screen printing technology relating to microelectronics. In 1998, Art Dobie was inducted into the SGIA's Academy of Screen Printing Technology and is a co-recipient of the SGIA's 2010 David Swormstedt, Sr. Memorial Award.

David Malanga is currently Business Unit Manager Americas at Heraeus Precious Metals North America LLC, Thick Film Materials Division in West Conshohocken, PA.. David has over 20 years of experience at Heraeus working in R&D, formulating thick film and LTCC materials, Technical Service solving processing and application problems directly with customers, and as manager of the Sales Department. David has a B.S. and M.S. in Ceramic Science and Engineering from Rutgers University. David has published various articles on thick film resistors, conductors, LTCC materials, and component metallizations worldwide. He is a Life member and Fellow of the Society of IMAPS and has held both local and national positions in the organization.

AM5: ENIG - Controlling Electroless Nickel & Immersion Gold Plating for Electronics: From Plating Solutions and Equipment Maintenance to How to Audit Your Supplier
PDC Instructor: Fred Mueller, General Magnaplate Corp
$400 (on/before 9/30/2015); $500 (after 9/30/2015)


Course Description: Provide a thorough overview of the use of electroless nickel and immersion gold (ENIG) and other coating systems (ENEPIG, Immersion Silver, Immersion Tin) used for a variety of applications in the field of electronics; Review the engineering differences and troubleshooting problems associated with the ENIG and other plating process; Presents methods for controlling the properties of plating solutions to maximize the deposits properties, including Laboratory Controls for the Final Finishes (ENIG, ENEPIG, Immersion Silver and Immersion Tin) to maintain Solderability and Solder Joint Reliability as Functions of Process Control - What lack of ENIG process controls can result in black pad?


PM1: Introduction to Fan-Out Wafer Level Packaging - Beth Keser, Qualcomm Technologies, Inc.
PM2: Process Flows for Electronics Packaging – Technology Comparisons & Cost and Yield Analyses - Chet Palesko, SavanSys Solutions LLC & E. Jan Vardaman, TechSearch International, Inc.
PM3: Crash Course on Packaging Technologies and Thermal Design of ICs - Herman Chu, Juniper & Li Li, Cisco System
PM4: Reliability 360: How to Verify Design Robustness Early in the Process - Greg Caswell, DfR Solutions
PM5: Adhesion Science & Practice with an Emphasis on Temporary Bonding of Electronics (Wafers, Displays, Devices) - John Moore, Jared Pettit, Alman Law, Alex Brewer, Daetec, LLC

PM1: Introduction to Fan-Out Wafer Level Packaging
PDC Instructor: Beth Keser, Qualcomm Technologies, Inc.
$400 (on/before 9/30/2015); $500 (after 9/30/2015)

Course Description: Fan-out wafer level packaging (FO-WLP) technologies have been developed across the industry over the past 15 years and have been in high volume manufacturing for over 5 years. FO-WLP has matured enough that it has come to a crossroads where it has the potential to change the electronic packaging industry by eliminating wirebond and bump interconnections, substrates, leadframes, and the traditional flip chip or wirebond chip attach and underfill assembly technologies across multiple applications. This course will cover the advantages of FO-WLP, potential application spaces, package structures available in the industry, process flows, material challenges, design rule roadmap, reliability, and benchmarking.

1. Current Challenges in Packaging
2. Definitions and Advantages
3. Applications
4. Package Structures
5. Process
6. Material Challenges
7. Equipment Challenges
8. Design Rule Roadmap
9. Reliability
10. Benchmarking

Who Should Attend? Engineers and managers responsible for advanced packaging development, package characterization, package quality, package reliability and package design should attend this course. Materials suppliers and tool vendors supplying polymer dielectric materials, epoxy mold compounds, adhesive tapes, mold tools, flip chip bonders, bond/debond equipment and materials, and 300mm and panel bump and WLP tools are also encouraged to attend. Both newcomers and experienced practitioners are welcome.

Beth Keser has over 17 years’ experience in the semiconductor industry. Beth received her B.S. degree in Materials Science and Engineering from Cornell University and her Ph.D. in Materials Science and Engineering at the University of Illinois at Urbana-Champaign. Beth’s development of materials and packaging technologies for the semiconductor industry has resulted in 8 patents, 10 patents pending, and over 40 publications in this area. Currently, Beth is the Fan-Out Wafer Level Packaging Technology Manager at Qualcomm, San Diego.

Before joining Qualcomm in 2009, Beth Keser was instrumental in developing 2 packaging technologies during her career at Motorola and Freescale Semiconductor. Beth led the Wafer-Level Chip Scale packaging team at Motorola, which included directing the activities of process engineering, package characterization, package reliability, and mechanical modeling. In addition, Beth Keser was the lead technologist and manager of the Redistributed Chip Packaging Technology (RCP). Beth led the team that developed this technology for 6 years. Beth developed several process and material solutions for this new technology.

PM2: Process Flows for Electronics Packaging – Technology Comparisons & Cost and Yield Analyses
PDC Instructors: Chet Palesko, SavanSys Solutions LLC & E. Jan Vardaman, TechSearch International, Inc.
$400 (on/before 9/30/2015); $500 (after 9/30/2015)

Course Description: Choosing the right packaging technology and right supplier is crucial to product success. The growing complexity of the supply chain coupled with an increasing choice of technologies--wafer level packaging, fan-out wafer level packaging, interposer and 3D options, embedded die, etc.--make it impossible to optimize packaging choices without first understanding the cost drivers of your design and the capabilities of your supply chain.

The packaging technologies covered in this course are flip chip PBGA, wire bond PBGAs, interposer and 3D, wafer level packaging, fan-out wafer level packaging, and embedded die. The manufacturing process flow and cost and yield drivers for each technology will be analyzed, and actual cost comparisons will be presented.

This course will also examine how OEMs and suppliers can collaborate to develop a model which optimizes product manufacturing cost for IC packages. This modeling approach has been successfully used by a number of major OEMs and suppliers in North America, Europe, and Asia to match design technology choices with supplier competencies. Yields are improved and cost reduction is achieved across the entire supply chain.

Who Should Attend? This course is designed for anyone involved in packaging technology and selection, including system designers, package designers, procurement personnel, design managers, and product managers. This course is beneficial for those who want to better understand the actual costs and yields associated with different packaging technologies, as well as for those who require a more complete understanding of their supply chain.

Chet Palesko is currently President of SavanSys Solutions LLC. SavanSys provides cost modeling services and software to both suppliers and OEMs. Mr. Palesko has developed dozens of electronic manufacturing cost models for major telecommunication, computer, and aerospace companies. He spent 12 years at Mentor Graphics in a variety of roles including general management, engineering, marketing, and sales. In 1995, he co-founded Savantage Inc., where he led the global development and sales of SavanSys.

PM3: Crash Course on Packaging Technologies and Thermal Design of ICs
PDC Instructors: Herman Chu, Juniper & Li Li, Cisco Systems, Inc.
$400 (on/before 9/30/2015); $500 (after 9/30/2015)

Course Description: This course will provide an overview of various types of IC packages and their targeted applications, advantages and limitations. The constructions, materials and assembly processes associated with IC packages will be discussed in details. The attendees will also be introduced to the fundamental sciences of the different design parameters on thermal, electrical and thermo-mechanical reliability in understanding their influences on package selections. Typical failure modes associated with IC packages and identify the common stress drivers will be discussed through a few case studies. This course will also cover the latest developments in IC packaging technologies including advanced topics on 2.5D and 3D stacked packaging and future IC packaging trends. A special topic on data center, its impact on thermal design and IC component reliability, will also be included.

Since the power and power density have continued to increase as the performance of ICs rises, thermal design is an important part of the design for proper selection of the IC in meeting the target performance. As part of the thermal tutorial section, the entire heat dissipating path will be examined for the package in order to identify potential opportunities in enhancing thermal design to enable higher power and power density devices.

Herman Chu, now with Juniper, is classically trained in thermodynamics and heat transfer; BS and MSME from UCSD and USC, respectively. Professional background spans almost 30 years in heat transfer and electronic thermal management. Active in professional societies, like IMAPS and SEMI-THERM and participating in industry standards developments, such ASHRAE TC9.9 and ATIS STEP.

Dr. Li Li earned his ME M.S. and Ph.D. degrees from U. of. Ill at Urbana-Champaign. He’s a Distinguished Engineer at Cisco, where he leads an initiative on 3D IC integration and advanced packaging development. He has 20 years of industry experience (11 of those years at Cisco) in IC packaging design, technology development and qualification. He has published several book chapters and over 50 technical papers in the field of microelectronics packaging. He is on the Board of Governors of IEEE CPMT Society and chairs the Interconnection Committee for the IEEE Electronic Component Technology Conference (ECTC).

PM4: Reliability 360: How to Verify Design Robustness Early in the Process
PDC Instructor: Greg Caswell, DfR Solutions
$400 (on/before 9/30/2015); $500 (after 9/30/2015)

Course Description: In today’s fast-paced, highly competitive electronics market, producing reliable products is critical to a company’s success. Business case studies have consistently shown that performing comprehensive design reviews during product development is the only proven method for ensuring a reliable product.

Most companies have some type of design review process; but, some fairly straightforward enhancements can drive substantial product improvements.

Verifying design robustness early in the process is both effective and efficient and can easily be incorporated into existing design review processes.

This course will cover how to use a new or existing Design Review Process to truly Design for Reliability and verify robust design.

A 5 step execution plan with tailoring to different markets will be discussed:
1) Initial Reliability Assessment: Performed by Subject Matter Experts (SME)
2) Limited 1st Order Physics of Failure (PoF) Based Simulation Based on SME Identification of Critical Components: Algorithms (Coffin-Manson, Steinberg, etc.) Identified in Industry Standards (IPC SM-785, VITA 51.2, JESD47)
3) Comprehensive 1st Order PoF-Based Simulation: Automated Design Analysis
4) Full 3D FEA & Thermal Simulation
5) Test Plan Development & Execution The 5 steps will incorporate Physics of Failure, electrical, mechanical, thermal, testing, and manufacturability topics.

Who Should Attend? Engineers or managers who would like to have a greater understanding of what is involved in creating a reliable and robust design looking at the process from a reliability perspective.

Greg Caswell is widely recognized as a pioneer in surface mount technology (SMT) and has 42 years of experience in the electronics industry. In his current position he is a Sr. Member of the Technical Staff for DfR Solutions. Greg has been involved with IMAPS in numerous capacities: 1984 Centex Chapter President, 1986 ISHM Vice President, 2001 President of the IMAPS, 1989-2000 ATW Chairman, 2008 GBC Chair, 2007 General Chair for Symposium, and 2009-2012 Editor Advancing Microelectronics. He has received the IMAPS Technical Achievement (1986), Fellow of the Society (1993), and Daniel C Hughes Memorial Award (1995). He received his Bachelor of Science in Electrical Engineering from Rutgers University and also has a Bachelors in Management from St. Edwards University in Austin.

PM5: Adhesion Science & Practice with an Emphasis on Temporary Bonding of Electronics (Wafers, Displays, Devices)
PDC Instructor: John Moore, Daetec, LLC & Jared Pettit, Alman Law, Alex Brewer
$400 (on/before 9/30/2015); $500 (after 9/30/2015)

Course Description: Adhesion plays an important role in many technologies and industries, viz., automotive, thin films, optics, soldering, printing, medical, coatings, paint and so on. Adhering two materials requires several properties to be coordinated in the form of chemistry and mechanical processing to achieve a good bond. Understanding these factors and controlling them during manufacturing is important for success. Bond durability (exposure to process chemicals, moisture, corrosives, etc.) is valuable to sustain the life of the product. The following will be discussed: surface contamination and cleaning, material science, substrate physical-chemical condition, theories and mechanisms of adhesion, measurements as contact angle, wettability, adhesion tests on coatings or bonded films, interfacial interactions, surface modification, adhesion promoters, adhesion aspects of thin films, adhesive force measurement.

The class will be an application-oriented tutorial that focuses on substrates, films, testing, adhesive films & tapes, coating and bonding adhesives, with applications of temporarily bonding wafers, displays, and small die. Onsite demonstrations include substrate bonding and measurement of adhesion force using materials with various tensile and elastic properties. Separation of substrates will be defined by form and composition (rigid and flexible, organic and inorganic). Onsite equipment will be used in conjunction with class members creating temporary bonds on parts with challenging configurations.

Who Should Attend? Packaging scientists, engineers, managers, and others charged with responsibilities related to substrate or component bonding that is permanent or temporary.

Daetec’s engineering team conducts this class to facilitate a highly interactive “hands-on” setting. Jared Pettit is technical director at Daetec, has co-authored many publications and patents in the area of coatings and cleaners. He, along with Alman Law, and Alex Brewer, hold degrees in chemistry of different disciplines. Their focus is on applications of coating, adhesion, and the effects of interfacial chemistry. John Moore is founder of Daetec, his third company, providing new products for the electronics market. In the last 10yrs, he has created some of the leading temporary bonding products for the industry. Mr. Moore performed his graduate work at UCSB in chemistry. Daetec is an internationally recognized company specializing in areas of temporary bonding and cleaning. For the past 15yrs, the company has created solutions for thin substrates down to 4um, encapsulating 300um bumps, or resisting temperatures to 450C. Daetec’s customers include top suppliers and fabs in microelectronics manufacturing.




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