KESTER


 
    PREMIER PROGRAM SPONSOR:
 
 
Premier Program Sponsor - Heraeus Materials Technology

 

    PREMIER TECHNOLOGY SPONSOR :

   PREMIER TECHNOLOGY SPONSOR:
   PREMIER TECHNOLOGY SPONSOR:
Premier Tech Sponsor - Metalor
Premier Tech Sponsor - Indium Corp.
Premier Tech Sponsor - NGK NTK

IMAPS 2016 - Pasadena
Packaging the Connected World
www.imaps2016.org

IMAPS 2016 Pasadena

Conference:
October 11-13, 2016
Exhibition:
October 11-12, 2016
Professional Development Courses:
October 10, 2016
General Chair:
Erica Folk
Northrop Grumman Corp.
Technical Chair:
Dan Krueger
Honeywell FM&T
     
Technical Co-Chair - USA:
Mary Cristina Ruales Ortega
University of Missouri, Kansas City
Technical Co-Chair - Europe:
André Rouzaud
CEA LETI
Technical Co-Chair - Asia:
Woong-Sun Lee
SK Hynix, Inc
Assistant Technical Co-Chair - USA:
Samson Shahbazi, Heraeus
Aric Shorey, Corning
Assistant Technical Co-Chairs - Europe:
Gabriel Parès, CEA LETI
Steffen Kroehnert, Nanium
Assistant Technical Co-Chair - Asia:
Kwang Sung Choi, ETRI
Seungwook Yoon, STATS ChipPAC Ltd.



       


Professional Development Courses
(PDCs / Short Courses / Tutorials)

NEW PDC FORMAT This Year!
Monday, October 10: New 2-hour formats, by theme/track
8:00 AM-10:00 AM | 10:30 AM – 12:30 PM | 1:00 PM – 3:00 PM | 3:30 PM – 5:30 PM

  Track A:
Intro to Microelectronics, Packaging & Test
Track B:
Reliability
Track C:
Materials & Processes
Track D:
Next Generation Packaging Challenges
8:00 AM-10:00 AM A1: Fundamentals of Microelectronics Packaging - John Pan, Cal Poly State University B1: Solder Joint Reliability - Jennie Hwang, H-Technologies Group C1: Polymers in Electronic Packaging - Jeffrey Gotro, InnoCentrix LLC D1: Emerging Challenges in Semiconductor Packaging - Raja Swaminathan, Intel NOW BEING TAUGHT BY: Kyu-Oh Lee, Intel
10:00 AM-10:30 AM
Coffee / Networking
Open to all PDC participants
10:30 AM – 12:30 PM A2: Fundamentals of 3D and 2.5D Packaging Integration - Urmi Ray, Qualcomm B2: Reliability of Electronics – the Role of Intermetallic Compounds - Jennie Hwang, H-Technologies Group C2: Technology of Screen Printing - CANCELLED D2: Glass Packaging for Consumer, High Bandwidth and Automotive Electronics - Venky Sundaram, Georgia Tech PRC
12:30 PM-1:00 PM
Lunch
Open ONLY to PDC participants taking morning AND afternoon courses
1:00 PM-3:00 PM A3: Introduction to Copper Pillar Flip Chip Interconnect - Mark Gerber, ASE US Inc. B3: Achieving High Reliability for Lead-Free Solder Joints - Materials Consideration - Ning-Cheng Lee, Indium Corporation C3: Contamination and Cleanliness - Developing Practical Responses to a Challenging Problem - Greg Caswell, DfR Solutions D3: Introduction to Fan-Out Wafer Level Packaging (FOWLP) - Beth Keser, Qualcomm
3:00 PM-3:30 PM
Coffee / Networking
Open to all PDC participants
3:30 PM-5:30 PM A4: Electrical Modeling & Test Strategies for 3D Packages - Bruce Kim, City University of New York B4: Reliability Testing of Implanted Class III Medical Devices & In Vivo Sensors - Thomas J. Green, TJ Green Associates LLC C4: It is Time for Low Temperature - Low Temperature Solders , New Development, and Their Applications - Ning-Cheng Lee, Indium Corporation D4: Advances in Fan-Out Wafer Level Packaging (FOWLP) - Beth Keser, Qualcomm
5:30 PM-7:30 PM
Welcome Reception
Open to all IMAPS 2016 participants

 

Cost for Each PDC: $300 (on/before 9/14/2016); $400 (after 9/14/2016)
Register Online

 

Get off line and learn Face to Face...Sign up for a PDC!

PDCs (Professional Development Course) are a big part of the Annual IMAPS Symposium each year. Why not plan to take a course on Monday before IMAPS 2016 kicks off and take advantage of the rich learning opportunities available at the IMAPS symposium.

This year the Monday courses have been completely redesigned to enhance your experience!
PDCs are all now scheduled for 2-hour lessons. Shorter courses for you to digest great information without being overwhelmed by a 4-8 hour commitments after your travels!
The shorter tutorials also allow for you to participate in more topical areas and learn from a variety of instructors! The courses are also now arranged under 4 "TRACK" categories: (A) - Introduction to Microelectronics, Packaging & Test; (B) Reliability; (C) Materials & Processes; and (D) Next Generation Packaging Challenges.

PDCs create a unique environment whereby students can personally interact with the instructors, and with each other in the classroom and over lunch. It's mentally stimulating and the new found professional connections will prove to be valuable in the long run. Learning on line is fine, but it cannot duplicate hours spent immersed in a specific topic, led by an industry expert in the field and surrounded by like-minded professionals.

This year we've put together another impressive assortment course options Our goal is to make the IMAPS PDCs the premier learning experience; so we ask that you take time to fill out the evaluation form that accompanies each course and give us your feedback on this or any other aspects of the PDCs. Read through the course descriptions on line and pick the course that best suits your company and career objectives. Every PDC includes a full set of comprehensive course notes. Class sizes typically range from ten to thirty students and there is always ample time for questions and networking. We hope you will consider joining us in Pasadena for a learning experience like no other.

Education is a lifelong pursuit, don't miss out on this opportunity!
Tom Green, Tom Terlizzi, and Urmi Ray
IMAPS 2016 PDC Co-Chairs

 

Your PDC Registration Fee Includes:

  • Refreshment breaks
  • Hard-copy workbook of course materials (no electronic copies provided)
  • Lunch (ONLY for those taking Morning & Afternoon courses)

PDCs under SESSIONS
during IMAPS 2016 Online Registration

PDC Cancellation policy: IMAPS reserves the right to cancel a course if the number of attendees is not sufficient.
You can transfer to a different course or we will refund you the corresponding amount.


Cost for Each PDC: $300 (on/before 9/14/2016); $400 (after 9/14/2016)
Register Online

 

Monday Morning (8:00 AM-10:00 AM) Courses
YOU MAY SELECT ONE OF THESE FOUR COURSES ONLY

Track A:
Intro to Microelectronics, Packaging & Test
Track B:
Reliability
Track C:
Materials & Processes
Track D:
Next Generation Packaging Challenges

A1: Fundamentals of Microelectronics Packaging
Instructor: John Pan, Cal Poly State University

Course description:

This course will review various electronics package types from common packages DIP, PGA, SOP, QFP, PLCC, BGA, CSP, QFN, and LGA to latest packages PoP, SiP, TSV, 2D, 2.5D, and 3D packaging. The materials and processes used in wire bonding and flip chip for interconnection and the material and processes used for electronic assembly will be presented.

Course outline:

• Introduction to Microelectronics Packaging
o Electronics Packaging Hierarchy and Functions
o Electronics Package Types
o Electronics Packaging Trends

• Microelectronics Packaging Materials and Processes
o Die attachment
o Wire bonding
o Flip Chip
o Encapsulation and Sealing

• Electronics Assembly Processes
o Surface Mount Assembly
o Soldering Basic
o Reflow soldering and wave soldering
o Lead-free solder joint reliability

At the end of this course, participants should be able to:

• Identify various electronics package types from common packages DIP, PGA, SOP, QFP, PLCC, BGA, CSP, QFN, and LGA to latest packages PoP, SiP, TSV, 2D, 2.5D, and 3D packaging;
• Describe microelectronics and electronic packaging processes including die attachment, wire bonding, flip chip, and encapsulation.
• Describe PCB assembly processes and soldering.

Biography:

Dr. John Pan is a professor in Industrial and Manufacturing Engineering Department at California Polytechnic State University, San Luis Obispo. His research interests include the materials, processes, and reliability of microelectronics packaging. He has authored or co-authored over 40 technical papers. He is a Fellow of IMAPS and a recipient of the 2011 IMAPS Outstanding Educator Award. He is currently the Editor-in-Chief of Journal of Microelectronics and Electronic Packaging and an Associate Editor of IEEE Transactions on Components, Packaging and Manufacturing Technology.

 

B1: Solder Joint Reliability - Essentials in Principles and Applications
Instructor: Jennie Hwang, H-Technologies Group

Course description:

The course synopsizes solder joint reliability fundamentals in fatigue and creep damage mechanisms via ductile, brittle, ductile-brittle fracture, and highlights the critical “players” of solder joint reliability (e.g. intermetallics, manufacturing process, substrate/component surface finish materials). Likely solder joint failure modes of interfacial, near-interfacial, bulk, inter-phase, intra-phase, voids-induced and surface cracks will be summarized. To withstand harsh environments, the strengthening metallurgy to further increase fatigue resistance and creep resistance will be summarized, and the power of metallurgy and its ability to anticipate the relative performance will be illustrated by comparing the performance vs. metallurgical phases and microstructure. The relative reliability among commercially available solder systems will be ranked, and the scientific, engineering and manufacturing reasons behind the ranking will be outlined. The course emphasizes on practical, working knowledge, yet balanced and substantiated by science. Attendees are encouraged to bring their own selected systems for deliberation.

Course outline:

• Solder joint fundamentals – mechanical properties vs. microstructure evolution vs. services;
• Solder joint thermo-mechanical behavior and degradation – fatigue and creep interaction;
• Solder joint failures modes - interfacial, near-interfacial, bulk, inter-phase, intra-phase, voids-induced, surface-crack, and others;
• Solder joint failure mechanisms – ductile, brittle, ductile-brittle transition fracture;
• Solder joint strengthening metallurgy;
• Power of metallurgy for increased fatigue resistance and creep resistance;
• Distinctions and commonalties between Pb-free and SnPb solder joints;
• Thermal cycling conditions - effects on test results and test results interpretation;
• Testing solder joint reliability – discriminating tests and discerning parameters;
• Solder joint performance in harsh environments;
• What are on the horizon and what impact will be on reliability- present vs. future system;
• Best practices – competitive manufacturing (yield, cost, reliability); • Ultimate reliability.

Biography:

Author of 450+ publications including several internationally-used textbooks and a speaker in innumerable international and national events, Dr. Hwang is a long-standing leader in SMT manufacturing and lead-free implementation. She brings deep knowledge to this course through both hands-on and advisory experiences. She has provided solutions to many challenging problems, ranging from production yield to field failure diagnosis to reliability issues covering both commercial and military applications. Her formal education includes Harvard Business School Executive Program and four academic degrees in Metallurgical Engineering and Materials Science, Physical Chemistry, Organic Chemistry and liquid Crystal Science (Ph.D. M.S., M.S., B.S.). She has held various senior executive positions with Lockheed Martin Corp., SCM Corp, Sherwin Williams Co, and IEM Corp. She is also an invited distinguished adj. Professor of Engineering School of Case Western Reserve University, and serves on the University’s Board of Trustees.

C1: Polymers in Electronic Packaging
Instructor: Jeffrey Gotro, InnoCentrix LLC

Course description:

The course will provide an overview of polymers and the important structure-property-process-performance relationships for electronic packaging.

The main learning objectives will be 1) understand how polymers are used in electronic packaging, 2) learn why specific chemistries are used depending on the application 3) learn the fundamentals of polymer characterization related to electronic packaging 4) develop a foundation in rheology and rheology issues in electronic packaging.

Topics to be covered are:

Thermosetting polymers, curing mechanisms (heat and light cured), network formation, and an overview of key chemistries used (epoxies, acrylates, polyimides, bismaleimides, curing agents, and catalysts).

The course will provide a more in-depth discussion of the chemistries, material properties, and process considerations for adhesives (both paste and film), capillary underfills, packaging substrate materials, encapsulants (mold compounds), with new content on polymers used in 2.5D packaging such as Wafer Level Packaging and Fanout eWLP.

Characterization using thermal analysis will be covered allowing understanding of structure-property relationships and how to interpret the material property data typically presented on technical data sheets.

The final portion of the PDC will provide an introduction to rheological characterization methods (various types of rheometers and viscometers) and the properties of adhesives (shear thinning, viscosity, time dependence, and rheology changes during curing), underfills, and mold compounds.

Participants are invited to bring problems for discussion.

Biography:

Dr. Jeff Gotro has over thirty two years' experience in polymers for electronic applications and composites having held scientific and leadership positions at IBM, AlliedSignal, Honeywell, and Ablestik Laboratories. Jeff is an expert in thermosetting polymers and has received invitations to speak at prestigious Gordon Research Conferences (Thermosetting Polymers and Composites). He has presented numerous invited lectures and short courses at technical meetings, has over 60 technical publications and 21 patents/patent applications. Jeff was an Adjunct Professor at Syracuse University in the Dept. of Chemical Engineering and Materials Science from 1986-1993. Jeff is a member of the American Chemical Society (ACS), the Institute for Management Consultants (IMC), the Forensic Expert Witness Association (FEWA), Society of Plastics Engineers, and the International Microelectronics Assembly and Packaging Society (IMAPS). Jeff was awarded the John A. Wagnon Jr. Technical Achievement Award in 2014 and elected as IMAPS Fellow.

D1: Emerging Challenges in Semiconductor Packaging
Instructor: Raja Swaminathan, Intel Corp. NOW BEING TAUGHT BY: Kyu-Oh Lee, Intel

Course description:

The course will introduce role of packaging in the interconnect hierarchy and introduce packaging trends per industry. We will then deep dive into the key elements driving the definition of a package architecture (scaling challenges, high speed signaling, power delivery, thermo-mechanical integration as well as thermal challenges). The interactions between these elements towards enabling a successful package architecture for a given product will be reviewed.

The second half of the course will focus on the package, assembly, test and silicon integration and surface mount challenges towards enabling high volume manufacturing of the package architectures.

Biography:

Dr. Raja Swaminathan is an IEEE senior member and is a package architect at Intel for next generation server, client and SOC products. His expertise is on delivering integrated HVM friendly package architectures with optimized electrical, mechanical, thermal solutions. He is an ITRS author and iNEMI TWG chair on packaging and design. He has also served on IEEE micro-electronics and magnetics technical committees. He has 18 patents and 23 peer reviewed publications and holds a Ph.D in Materials Science and Engineering from Carnegie Mellon University.

10:00 AM-10:30 AM
Coffee / Networking

Open to all PDC participants

 

Monday Morning (10:30 AM - 12:30 PM) Courses
YOU MAY SELECT ONE OF THESE FOUR COURSES ONLY

Track A:
Intro to Microelectronics, Packaging & Test
Track B:
Reliability
Track C:
Materials & Processes
Track D:
Next Generation Packaging Challenges

A2: Fundamentals of 3D and 2.5D Packaging Integration
Instructor: Urmi Ray, Qualcomm

Course description:

This course will cover the fundamental technology aspects of 3D and 2.5D integration including summaries of key benefits, process flow, test, cost and reliability challenges. The goal of this course is to provide a review of technology status to date and spend additional time on case studies of market and product adoption.

Course outline:

• Why 3D:
o New architectural & partitioning capabilities
o Package Density and Form Factor
o Improved Performance

• Types of 3D:
o Via first
o Via middle
o Via last

• Types of 2.5D
o Si/glass interposer
o Fan Out
o Laminate substrate/embedding

• Manufacturing process flow for Via-middle

• Manufacturing process flow for Si interposer

• Challenges for market adoption
o Cost
o Reliability
o Supply Chain
o Others

• Case Studies of successful recent product adoption
o HBM memory with TSV
o Graphics processor integration using 2.5D

• Roadmap

Biography:

Urmi Ray is a Principal Engineer in Qualcomm. She has been the technology and program lead in several forward looking programs in 3D and 2.5D and system integration, with particular focus on low cost packaging for mobile industry. She joined Qualcomm in 2006, after spending 10+ years at Lucent Technologies Bell Laboratories in NJ working on advanced materials and reliability for a diverse set of product portfolios, including consumer products to high reliability telecommunications projects. She is currently active in many aspects of advanced packaging technology area. She has a PhD from Columbia University (New York City).

B2: Reliability of Electronics - the Role of Intermetallic Compounds
Instructor: Jennie Hwang, H-Technologies Group

Course description:

Intermetallic compounds play an increasingly critical role to the performance and reliability of solder interconnections in the chip level, package level and board level of lead-free electronics. This course covers the essential aspects of intermetallic compounds. Intermetallic compounds before solder joint formation, during solder joint formation and after solder joint formation in storage and service will be outlined. The course also summarizes intermetallics at-interface and in-bulk, as well as the surface finish/component coating in relation to reliability. The difference between SnPb and Pb-free solder joint in terms of intermetallic compounds, which in turn is attributed to production-floor phenomena and the actual field failure, will be discussed.

Course outline:

• Intermetallic compounds - definition, fundamentals, characteristics;
• Intermetallic compounds in the intrinsic material- Pb-free vs. SnPb;
• Formation and growth during production process and in product service life;
• Different types of intermetallic compounds - effects on solder joint reliability;
• Intermetallic compounds - at-interface vs. in-bulk;
• Effects from substrate compositions (hybrid module thick film pads, PCB surface finish) + component surface coating;
• SAC alloys incorporated with various doping elements - characteristics, performance;
• Effects on failure mode;
• Effects on reliability.

Biography:

Author of 450+ publications including several internationally-used textbooks and a speaker in innumerable international and national events, Dr. Hwang is a long-standing leader in SMT manufacturing and lead-free implementation. She brings deep knowledge to this course through both hands-on and advisory experiences. She has provided solutions to many challenging problems, ranging from production yield to field failure diagnosis to reliability issues covering both commercial and military applications. Her formal education includes Harvard Business School Executive Program and four academic degrees in Metallurgical Engineering and Materials Science, Physical Chemistry, Organic Chemistry and liquid Crystal Science (Ph.D. M.S., M.S., B.S.). She has held various senior executive positions with Lockheed Martin Corp., SCM Corp, Sherwin Williams Co, and IEM Corp. She is also an invited distinguished adj. Professor of Engineering School of Case Western Reserve University, and serves on the University’s Board of Trustees.

C2: Technology of Screen Printing
Instructors: Art Dobie, Chromalin; David Malanga, Heraeus

CANCELLED

D2: Glass Packaging for Consumer, High Bandwidth and Automotive Electronics
Instructor: Venky Sundaram, Georgia Tech PRC

Course description:

This course will provide the most comprehensive summary of glass packaging, including the latest technical updates as well as an introduction to glass package technologies, market drivers, application examples and infrastructure evolution. Two types of architectures, namely, glass substrates and glass panel fanout, will be described in detail, highlighting recent progress in key building blocks such as through vias and RDL.

In the consumer electronics domain, RF LTE modules, power management modules, application processor and memory packaging and other applications of glass packages will be covered. In high bandwidth electronics, high density glass interposers in networking, graphics and other high performance computing applications will be discussed.

2.5D Interposers bridge the interconnect gap between back end of the line (BEOL) pitch and current organic BGA packages, and have recently gained prominence as a mainstream platform. In the past couple of years, the technology development and manufacturing infrastructure maturity has been progressing rapidly. The first volume products using silicon interposers hit the graphics market in 2015 integrating high bandwidth memory (HBM) and GPUs. Several other applications are also exploring product designs based on interposer concepts. It is certainly an exciting time for interposer technologies.

This year's PDC by one of the top experts in the world in glass packaging, includes significant new material covering the emerging area of automotive electronics. Applications of glass fanout and glass interposer packages, such as RADAR, LiDAR and Cameras for autonomous driving will be introduced, in addition to infotainment and connectivity applications such as 5G communication.

The course will address both glass packaging fundamentals, as well as applications and supply chain infrastructure. The course will be interactive and include audience Q&A and samples of latest interposer demonstrators will be passed around for a hands-on experience.

Biography:

Dr. Venky Sundaram is a faculty member in the School of Electrical & Computer Engineering at Georgia Tech, ranked 4th in the nation in engineering programs, and Associate Director of Industry Programs at the 3D Systems Packaging Research Center. He is a globally recognized expert in electronics packaging technology with more than 17 years experience in semiconductor and electronic systems packaging technology. He currently directs and manages one of the largest electronics R&D programs in the world, valued at over $10 Million per year. He also directs the largest Glass Packaging program in the world, with more than 50 active global industry members. He has pioneered major technologies including embedded RF passives in organic substrates, chip-last die embedding and glass interposers. In 2001, he co-founded Jacket Micro Devices, a venture capital funded RF/wireless module technology start-up, acquired by AVX. He is a former member of the Executive Council of IMAPS.

12:30 PM-1:00 PM
Lunch

Open ONLY to PDC participants taking morning AND afternoon courses

 

Monday Afternoon (1:00 PM - 3:00 PM) Courses
YOU MAY SELECT ONE OF THESE FOUR COURSES ONLY

Track A:
Intro to Microelectronics, Packaging & Test
Track B:
Reliability
Track C:
Materials & Processes
Track D:
Next Generation Packaging Challenges

A3: Introduction to Copper Pillar Flip Chip Interconnect
Instructor: Mark Gerber, ASE US Inc.

Course description:

This PDC course will review Copper Pillar Flip Chip interconnect structure, process flows and package integration process methods for evolving flip chip applications. The understanding the trade-offs between the traditional solder based flip chip and Copper Pillar is key in determining the silicon device layout and the type of design rules that can be leveraged. As part of this course, the Copper Pillar bump structure formation and IMC formation considerations will be reviewed as well as multiple Cu Pillar flip chip attachment methods. Current market trends have led to additional questions regarding the longevity of flip chip versus other competing technologies such as Fan Out Wafer Level Packaging (FOWLP) will also be reviewed as well as a comparison between technologies.

Biography:

Mark Gerber is the Director of Engineering & Technical Marketing at ASE-US Inc, specializing in Flip Chip and Advanced Interconnect package technologies. Mark joined ASE in Feb of 2015, and brings a diverse set of semiconductor experiences from Texas Instruments, Motorola/Freescale, and Dallas Semiconductor, including advanced interconnect & IC package development, as well as a history of new product introductions. Mark holds a bachelor’s degree in Mechanical Engineering from Texas A&M University, and has worked in the Semiconductor Industry for the last 20 years, has written +20 papers, and currently holds over 30 patents in the area of semiconductor packaging.

B3: Achieving High Reliability for Lead-Free Solder Joints - Materials Consideration
Instructor: Ning-Cheng Lee, Indium Corporation

Course description:

This course covers the detailed material considerations required for achieving high reliability for lead-free solder joints. The reliability discussed includes joint mechanical properties, development of type and extent of intermetallic compounds (IMC) under a variety of material combinations and aging conditions and how those IMCs affect the reliability. The failure modes, thermal cycling reliability, and fragility of solder joints as a function of material combination, thermal history, and stress history will be addressed in details, and novel alloys with reduced fragility will be presented. Electromigration, corrosion, and tin whisker will also be discussed. Furthermore, the reliability of through-hole solder joints will be reviewed, and recommendation will be provided, particularly for thick boards.

The emphasis of this course is placed on the understanding of how the various factors contributing to the failure modes, and how to select proper solder alloys and surface finishes for achieving high reliability. Also will be presented are the desirable future alloys and fluxes in order to meet the challenge of miniaturization.

Biography:

Ning-Cheng Lee is the Vice President of Technology of Indium Corporation. He has been with Indium since 1986. Prior to joining Indium, he was with Morton Chemical and SCM. He has more than 30 years of experience in the development of fluxes and solder pastes for SMT industries. He received his PhD in polymer science from University of Akron in 1981, and BS in chemistry from National Taiwan University in 1973. Ning-Cheng is the author of "Reflow Soldering Processes and Troubleshooting: SMT, BGA, CSP, and Flip Chip Technologies", and co-author of "Electronics Manufacturing with Lead-Free, Halogen-Free, and Conductive-Adhesive Materials".

C3: Contamination and Cleanliness - Developing Practical Responses to a Challenging Problem
Instructor: Greg Caswell, DfR Solutions

Course description:

To understand the challenge of contamination and cleanliness, one only needs to look at the many problems associated with high reliability environments, such as those encountered in automotive, and military applications. Particularly, high humidity exposure (85 % RH 85 C) can result in shorting occurring in less than 168 hours, due to dendritic growth and corrosion. This issue, in turn, can result from poor cleanliness both before solder mask and after soldering.

Course outline:

This course will present an Overview of:

• Contamination and Cleanliness;
• Drivers;
• Temperature Effects;
• Humidity/Moisture Effects;
• Voltage and Electric Field;
• Sources of Contamination;
• PCB fab;
• Fluxes;
• Assembly;
• Handling;
• Use Environment;
• Mitigation Approaches; and
• Conformal Coating

Biography:

Greg Caswell is widely recognized as a pioneer in surface mount technology (SMT) and has 42 years of experience in the electronics industry. In his current position he is a Sr. Member of the Technical Staff for DfR Solutions. Greg has been involved with IMAPS in numerous capacities: 1984 Centex Chapter President, 1986 ISHM Vice President, 2001 President of the IMAPS, 1989-2000 ATW Chairman, 2008 GBC Chair, 2007 General Chair for Symposium, and 2009-2012 Editor Advancing Microelectronics. He has received the IMAPS Technical Achievement (1986), Fellow of the Society (1993), and Daniel C Hughes Memorial Award (1995). He received his Bachelor of Science in Electrical Engineering from Rutgers University and also has a Bachelors in Management from St. Edwards University in Austin.

D3: Introduction to Fan-Out Wafer Level Packaging (FOWLP)
Instructor: Beth Keser, Qualcomm

Course description:

Fan-out wafer level packaging (FO-WLP) technologies have been developed across the industry over the past 15 years and have been in high volume manufacturing for over 8 years. FO-WLP has matured enough that it has come to a crossroads where it has the potential to change the electronic packaging industry by eliminating wirebond and bump interconnections, substrates, leadframes, and the traditional flip chip or wirebond chip attach and underfill assembly technologies across multiple applications. This course will cover the advantages of FO-WLP, potential application spaces, package structures available in the industry, design rule roadmap, and reliability.

Course outline:

• Current Challenges in Packaging
• Definitions and Advantages
• Applications
• Package Structures
• Design Rules
• Reliability

Biography:

Dr. Beth Keser has over 17 years’ experience in the semiconductor industry. Beth received her B.S. degree in Materials Science and Engineering from Cornell University and her Ph.D. in Materials Science and Engineering at the University of Illinois at Urbana-Champaign. Beth’s development of materials and packaging technologies for the semiconductor industry has resulted in 8 patents, 10 patents pending, and over 40 publications in this area. Currently, Beth is the Fan-Out Wafer Level Packaging Technology Manager at Qualcomm, San Diego.

Before joining Qualcomm in 2009, Beth Keser was instrumental in developing 2 packaging technologies during her career at Motorola and Freescale Semiconductor. Beth led the Wafer-Level Chip Scale packaging team at Motorola, which included directing the activities of process engineering, package characterization, package reliability, and mechanical modeling. In addition, Beth Keser was the lead technologist and manager of the Redistributed Chip Packaging Technology (RCP). Beth led the team that developed this technology for 6 years. Beth developed several process and material solutions for this new technology.

3:00 PM-3:30 PM
Coffee / Networking

Open to all PDC participants

 

Monday Afternoon (3:30 PM - 5:30 PM) Courses
YOU MAY SELECT ONE OF THESE FOUR COURSES ONLY

Track A:
Intro to Microelectronics, Packaging & Test
Track B:
Reliability
Track C:
Materials & Processes
Track D:
Next Generation Packaging Challenges

A4: Electrical Modeling & Test Strategies for 3D Packages
Instructor: Bruce Kim, City University of New York

Course description:

Today's miniaturization and performance requirements result in the usage of high-density advanced packaging technologies, such as system-in-package (SIP), direct-chip-attach, chip-scale packaging (CSP), and ball-grid-arrays (BGA). Due to their physical access limitation, the complexity and cost associated with their test and diagnosis are considered major issues facing their use.

This course introduces comprehensive knowledge of electrical modeling and test solutions for 3D packages. We begin by a short tutorial on 3D packages including interposers and TSV. We then place particular emphasis on electrical modeling; test and debugging approaches for 3D packages for RF, bio, power and MEMS packages. Finally, we cover diagnosis and repair techniques for assembled packages.

Course outline:

• What is 3D packaging?
• Introduction to existing 3D package techniques in
o Analog/Digital/RF device packages
o Mixed-signal device packages
• New Research Electrical Test strategies
o RF testing o Mixed-signal testing
o MEMS/Nano testing
• 3D package modeling
• TSV inductor design
• 3D package testing
o Interconnect modeling
o Defect testing
o Overview of existing techniques
o Research substrate test strategies
• Repair/diagnosis techniques for modules
• Summary and Outlook

Biography:

Dr. Bruce Kim is a professor of the Department of Electrical Engineering at City University of New York. He has about 300 publications in packaging and testing areas. He has instructed previous PDCs at IMAPS, IEEE EPTC and ECTC conferences. He is a Fellow of IMAPS and received the IMAPS Outstanding Educator award in 2012. He has also been a student chapter advisor. His research interests are in 3D passive components modeling and testing.

B4: Reliability Testing of Implanted Class III Medical Devices & In Vivo Sensors Instructor: Thomas Green, TJ Green Associates LLC

Course description:

Hermetic and non-hermetic packaging and testing of microelectronics, sensors, MEMS, hybrids and microwave components for use as implanted Class II/III devices in vivo is of critical importance. Reliability, small form factors, biocompatibility and patient safety are driving concerns. This tutorial reviews the major issues with screening and reliability testing of both hermetic and “non-hermetic” devices for use in vivo.

Most pacemakers, IPGs, cochlear implants in use today follow a prescribed and proven path of hermetic sealing and testing to assure product reliability and patient safety, which includes hermeticity testing in accordance with MIL-STD-883 Test Method 1014. Packages made from polymeric materials require a different approach from a manufacturing and testing standpoint. The problem is now one of moisture diffusion through the barrier and package interfaces. How to test and evaluate "non-hermetic" packaging methods such as parylene, PDMS, various ALD and CVD organic and inorganic coatings, LCP, silicones are reviewed and discussed.

Course outline:

• Hermetic Seal Processes
o Laser welding aluminum and Al-Si alloys
o On wafer MEMS seal processes
• Review of hermeticity test methods
• “Near- Hermetic Packaging” and Testing Issues
o Qualification of near hermetic packages for medical applications
o Ficks law of moisture diffusion
• Coating material evaluation and effectiveness
• FDA Regulations for Class III medical implants 21 CRF 820

Biography:

Thomas Green is the principle at TJ Green Associates LLC (www.tjgreenllc.com) a veteran owned small business focused on training and consulting for military, space and medical microelectronic devices. Tom has extensive experience analyzing in vivo Class III medical device failures and has served numerous times as an expert witness. He teaches a variety of public training courses related to microelectronic packaging around the globe and in plant at major corporations. He has over thirty three years of experience in packaging of microcircuits working at positions in industry, academia and government. Tom is an IMAPS Society Fellow. He earned a B.S. in Materials Engineering from Lehigh University and a Masters from the University of Utah

C4: It is Time for Low Temperature - Low Temperature Solders , New Development, and Their Applications
Instructor: Ning-Cheng Lee, Indium Corporation

Course description:

Since the dawn of electronic industry, the soldering process encompasses mainly component manufacturing and printed circuit board assembly with hierarchic melting range selection. The former use solder alloys with melting temperature around 300 C, which will not melt in the subsequent PCB assembly process, where the solders typically melt around 200 C. Low temperature solders with melting temperature < 180 C are currently mainly used for niche applications. However, iNEMI roadmap predicts low temperature soldering to become one of the main stream processes by 2017. The low temperature soldering is greatly desired for a number of special applications, such as heat sensitive devices, systems with more hierarchic levels, parts with significant difference in coefficient of thermal expansion, components exhibiting severe thermal warpage, or products with highly miniaturized design.

This course will cover the varieties of low temperature solders with emphasis on lead-free alloys, their physical, mechanical, and soldering properties, and the applications involved with those alloys.

Biography:

Ning-Cheng Lee is the Vice President of Technology of Indium Corporation. He has been with Indium since 1986. Prior to joining Indium, he was with Morton Chemical and SCM. He has more than 30 years of experience in the development of fluxes and solder pastes for SMT industries. He received his PhD in polymer science from University of Akron in 1981, and BS in chemistry from National Taiwan University in 1973. Ning-Cheng is the author of "Reflow Soldering Processes and Troubleshooting: SMT, BGA, CSP, and Flip Chip Technologies", and co-author of "Electronics Manufacturing with Lead-Free, Halogen-Free, and Conductive-Adhesive Materials".

D4: Advances in Fan-Out Wafer Level Packaging (FOWLP)
Instructor: Beth Keser, Qualcomm

Course description:

Now that Fan-out wafer level packaging (FO-WLP) has matured, unique advanced FO-WLP structures have been developed. This course will cover these advanced structures of FO-WLP and potential application spaces, technology roadmaps, and benchmarking. The challenges of moving from 300mm FO-WLP to panel will also be discussed.

Course outline:

• Definitions and Advantages
• Advanced Applications
• Package Structures including Advanced FO technologies
• Technology Roadmap
• Panel Challenges
• Benchmarking

Biography:

Dr. Beth Keser has over 17 years’ experience in the semiconductor industry. Beth received her B.S. degree in Materials Science and Engineering from Cornell University and her Ph.D. in Materials Science and Engineering at the University of Illinois at Urbana-Champaign. Beth’s development of materials and packaging technologies for the semiconductor industry has resulted in 8 patents, 10 patents pending, and over 40 publications in this area. Currently, Beth is the Fan-Out Wafer Level Packaging Technology Manager at Qualcomm, San Diego.

Before joining Qualcomm in 2009, Beth Keser was instrumental in developing 2 packaging technologies during her career at Motorola and Freescale Semiconductor. Beth led the Wafer-Level Chip Scale packaging team at Motorola, which included directing the activities of process engineering, package characterization, package reliability, and mechanical modeling. In addition, Beth Keser was the lead technologist and manager of the Redistributed Chip Packaging Technology (RCP). Beth led the team that developed this technology for 6 years. Beth developed several process and material solutions for this new technology.

5:30 PM-7:30 PM
Welcome Reception

Open to all IMAPS 2016 participants

 

Cost for Each PDC: $300 (on/before 9/14/2016); $400 (after 9/14/2016)
Register Online

 

 

 

 


PREMIER Sponsors:

 

    Premier Program Sponsor:
Premier Program Sponsor - Heraeus Materials Technology

    Premier Technology Sponsor:

    Premier Technology Sponsor:
    Premier Technology Sponsor:
Premier Tech Sponsor - Metalor
Premier Tech Sponsor - Indium Corp.
Premier Tech Sponsor - NGK NTK
Event Sponsors:
Dessert "Happy Hour" Sponsor:

Palomar Technologies: Dessert "Happy Hour" Sponsor
Posters & Pizza Sponsor:

Northrop Grumman EC - Poster Session Sponsor
Keynote Sponsor:

Applied Materials - Keynote Sponsor

Lunch Sponsor:
EMD Performance Materials - Corporate Sponsor

Student Programs Sponsor:
Honeywell - Student Programs Sponsor

Coffee Break Sponsor:

Fujifilm Dimatix - Coffee Break Sponsor

Coffee Break Sponsor:
MRSI - Break Sponsor

Coffee Break Sponsor:
Shenmao - Event Sponsor

Golf Sponsors
EMD Performance Materials - Corporate Sponsor
Technic - Golf Hole Sponsor
MicroScreen - Golf Sponsor
golf holes still available
Media Sponsors
Media Sponsor: MEMS Journal
Media Sponsor: US Tech
Solid State Technology - Media Sponsor
Media Sponsor: MEPTEC
3D Incites - Media Sponsor
Media Sponsor: Webcom - Antenna Systems & Technology
Media Sponsor: Webcom - Electronics Protection
Media Sponsor: Webcom - Thermal News
Media Sponsor: Chip Scale Review
GlobalSMT - Media Sponsor
   

 




CORPORATE PREMIER MEMBERS
  • Amkor
  • ASE
  • Canon
  • EMD Performance Materials
  • Honeywell
  • Indium
  • Kester
  • Kyocera America
  • Master Bond
  • Micro Systems Technologies
  • MRSI
  • NGK NTK
  • Palomar
  • Plexus
  • Promex
  • Qualcomm
  • Quik-Pak
  • Raytheon
  • Specialty Coating Systems