KESTER


 
    PREMIER PROGRAM SPONSOR:
 
 
Premier Program Sponsor - Heraeus Materials Technology

 

    PREMIER TECHNOLOGY SPONSOR :

   PREMIER TECHNOLOGY SPONSOR:
   PREMIER TECHNOLOGY SPONSOR:
Premier Tech Sponsor - Metalor
Premier Tech Sponsor - Indium Corp.
Premier Tech Sponsor - NGK NTK

IMAPS 2016 - Pasadena
Packaging the Connected World
www.imaps2016.org

IMAPS 2016 Pasadena

Conference:
October 11-13, 2016
Exhibition:
October 11-12, 2016
Professional Development Courses:
October 10, 2016
General Chair:
Erica Folk
Northrop Grumman Corp.
Technical Chair:
Dan Krueger
Honeywell FM&T
     
Technical Co-Chair - USA:
Mary Cristina Ruales Ortega
University of Missouri, Kansas City
Technical Co-Chair - Europe:
André Rouzaud
CEA LETI
Technical Co-Chair - Asia:
Woong-Sun Lee
SK Hynix, Inc
Assistant Technical Co-Chair - USA:
Samson Shahbazi, Heraeus
Aric Shorey, Corning
Assistant Technical Co-Chairs - Europe:
Gabriel Parès, CEA LETI
Steffen Kroehnert, Nanium
Assistant Technical Co-Chair - Asia:
Kwang Sung Choi, ETRI
Seungwook Yoon, STATS ChipPAC Ltd.



       

Early Registration & Hotel Deadlines: September 14, 2016


IMAPS 2016 Technical Program


Monday, October 10, 2016

IMAPS Microelectronics Foundation David C. Virissimo Memorial Golf Classic | 6:45 AM - "Scramble"

Professional Development Courses (PDCs) - 8:00 AM - 5:30 PM)

Microelectronics/Packaging Industry Tour - 10:00 AM - 3:00 PM
SUSS Photonic Systems Inc. - Corona, CA
The tour will include company introduction, general tour of the facilities including development and prototype tools, lunch and live demos using a projection scanner and excimer laser ablation on production tools. $15 fee - includes lunch and transportation

Welcome Reception | 5:30 PM - 7:30 PM

Welcome Reception Sponsored by:

 
   Gold Premier Program Sponsor:
 
 
Heraeus Materials Technology - Premier Sponsor, Gold
 

 

 

NEW PDC FORMAT This Year!
Monday, October 10: New 2-hour formats, by theme/track
8:00 AM-10:00 AM | 10:30 AM – 12:30 PM | 1:00 PM – 3:00 PM | 3:30 PM – 5:30 PM

  Track A:
Intro to Microelectronics, Packaging & Test
Track B:
Reliability
Track C:
Materials & Processes
Track D:
Next Generation Packaging Challenges
8:00 AM-10:00 AM A1: Fundamentals of Microelectronics Packaging - John Pan, Cal Poly State University B1: Solder Joint Reliability - Jennie Hwang, H-Technologies Group C1: Polymers in Electronic Packaging - Jeffrey Gotro, InnoCentrix LLC D1: Emerging Challenges in Semiconductor Packaging - Raja Swaminathan, Intel - NOW BEING TAUGHT BY: Kyu-Oh Lee, Intel
10:00 AM-10:30 AM
Coffee / Networking
Open to all PDC participants
10:30 AM – 12:30 PM A2: Fundamentals of 3D and 2.5D Packaging Integration - Urmi Ray, Qualcomm B2: Reliability of Electronics – the Role of Intermetallic Compounds - Jennie Hwang, H-Technologies Group C2: Technology of Screen Printing - CANCELLED D2: Glass Packaging for Consumer, High Bandwidth and Automotive Electronics - Venky Sundaram, Georgia Tech PRC
12:30 PM-1:00 PM
Lunch
Open ONLY to PDC participants taking morning AND afternoon courses
1:00 PM-3:00 PM A3: Introduction to Copper Pillar Flip Chip Interconnect - Mark Gerber, ASE US Inc. B3: Achieving High Reliability for Lead-Free Solder Joints - Materials Consideration - Ning-Cheng Lee, Indium Corporation C3: Contamination and Cleanliness - Developing Practical Responses to a Challenging Problem - Greg Caswell, DfR Solutions D3: Introduction to Fan-Out Wafer Level Packaging (FOWLP) - Beth Keser, Qualcomm
3:00 PM-3:30 PM
Coffee / Networking
Open to all PDC participants
3:30 PM-5:30 PM A4: Electrical Modeling & Test Strategies for 3D Packages - Bruce Kim, City University of New York B4: Reliability Testing of Implanted Class III Medical Devices & In Vivo Sensors - Thomas J. Green, TJ Green Associates LLC C4: It is Time for Low Temperature - Low Temperature Solders , New Development, and Their Applications - Ning-Cheng Lee, Indium Corporation D4: Advances in Fan-Out Wafer Level Packaging (FOWLP) - Beth Keser, Qualcomm
5:30 PM-7:30 PM
Welcome Reception
Open to all IMAPS 2016 participants

 

Cost for Each PDC: $300 (on/before 9/14/2016); $400 (after 9/14/2016)
Register Online

 


 

TUESDAY, OCTOBER 11, 2016

7:00 AM - 5:30 PM: Registration Open
11:00 AM - 5:00 PM: Exhibit Hall Open

IMAPS 2016 Opening Ceremonies & Plenary Session:

8:00 AM - 8:15 AM: Welcome to IMAPS 2016 Pasadena!
Erica Folk, General Chair, Northrop Grumman

8:15 AM - 8:45 AM: Annual Business Meeting & Awards Ceremony
IMAPS President

Keynote Introductions - Erica Folk, General Chair & Dan Krueger, Technical Chair

Keynote Sessions sponsored by:
Applied Materials - Keynote Sponsor

8:45 AM - 9:30 AM: Keynote 1
Doug Yu, TSMC

"Simpler is Better"- New Trend and Challenges for Advanced Packaging
Heterogeneous system integration plays important role in providing better system solution for semiconductor industry. Various structures and associated integration flows have been proposed that impact on system performance, power, profile and manufacturing cost. Simpler structure with simpler integration flow can enable shorter integration flow with shorter cycle-time and more competitive cost. Furthermore, it can also realize system with higher performance, lower power consumption and lower profile. Simpler supply chain and simpler design flow and design support provide further benefits to the industry. This presentation will illustrate those points with real examples.

Douglas Yu

Douglas Yu is a senior director in charge of TSMC Advanced Package R&D. His team has developed and delivered CoWoSTM and InFO, industry first Si interposer technology, and first high-density 3D-FOWLP, respectively. He was previously responsible for the development industry’s first Cu/Low-K on-chip interconnect from TSMC 0.13m technology. Doug received Ph.D. degree on Materials Science and Engineering from Georgia Institute of Technology. He holds 600 issued US patents and publishes more than 100 papers. Doug is an IEEE Fellow.

 

9:30 AM - 10:00 AM: Coffee Break in Foyer

Coffee Break sponsored by:
Fujifilm Dimatix - Coffee Break Sponsor

10:00 AM - 10:45 AM: Keynote 2
Mark Brillhart, Flextronics

Enabling Product Innovation Through Microelectronics Packaging
Creating innovative products in the Age of Intelligence requires deep microelectronics expertise. Flex works with customers to turn ideas into breakthrough products, delivering from sketch to scale™. As a supply chain solution company and contract manufacturer, Flex’s impact on the microelectronics packaging industry is critical. From wafer sawing to COB to wire bonding, Flex plays an important role in bringing the next generation products to market. We provide customers with world-class facilities to test innovations from the earliest concepting stages through design and volume manufacturing. Our engineers are engaged with the latest advancements in industries including medical, energy, communications and consumer. We integrate that knowledge with the best innovations from our partnerships with research institutions, startups, and our own Centers of Excellence and innovation labs. Flex brings customers the competitive advantages of proven microelectronics packaging solutions, reducing adoption risks. Creating and qualifying new technology, we anticipate relevant trends, test what’s new, and secure the latest resources. Integrating the best of these innovative technologies into our customers’ products helps maximize functionality, reduce time to market and optimize cost thus helping our customers succeed in their markets.

Mark Brillhart

Mark Brillhart is Chief Technology Officer and a Senior Vice President of the Flex Communications Infrastructure Computing Enterprise (CEC) business group. His team focuses on leading the technical initiatives across networking, telco and compute segments. He has over twenty years’ experience in the technology sector. Mr. Brillhart is accomplished in establishing and driving partner-integrated end-to-end supply chains. He has a deep background in quality (component, factory and product), component and assembly technology, as well as broad experience in the test of network products. Previously, as Vice President Manufacturing Operations, Quality and Manufacturing Engineering with Juniper Networks, Mr. Brillhart led a global team responsible for all aspects of contract manufacturing including original design manufacturing, product quality, NPI test engineering and manufacturing engineering. He attended the University of Illinois, studied Civil Engineering and obtained a Masters in Civil Engineering. In addition, he holds a Master Degree in Polymers from the Massachusetts Institute of Technology.

 

10:45 AM - 11:30 AM: Keynote 3
Reza Ghaffarian, Jet Propulsion Laboratory, California Institute of Technology


Lift up! to IC Packaging: Trends and Assembly Reliability
For five decades, the semiconductor industry has distinguished itself from other industries by continuously reducing IC sizes while exponentially increasing functionality (Moore’s Law) that enabled IC shrinkage and lower cost. The problem now is that IC shrinkage hit a brick wall, in response, a new paradigm shift is emerged—packaging technologies. Industries now focusing on shrinking the IC packaging through stacking and system integration. This talk presents electronics packaging miniaturization trends from ball grid arrays to wafer level and stack technologies with emphasis on system to package qualification and reliability testing methodologies and results.

Reza Ghaffarian

Dr. Reza Ghaffarian has more than 35 years of industrial and academic experience. For the last 22 years at NASA/JPL, he led R&D activities on reliability and quality assurance in advanced electronics packaging/assembly and has been a subject matter expert (SME) resource for most JPL projects including Mars Curiosity Rover. He has received many awards including the NASA Exception Service Medal for outstanding leadership and industrial partnership. He has authored more than 150 technical papers, 11 book chapters, two guidelines, and co-edited a CSP book. He serves as technical Advisor/Committee to IPC, Microelectronics Journal, SMTA, IMAPS and IEEE IEMT/CPMT. He received his Ph.D. in 1982 from University of California at Los Angeles (UCLA).

 

11:30 AM - 11:45 AM: Introduction and What's Ahead with the Technical Program
Dan Krueger, Technical Chair, Honeywell FM&T

11:45 AM - 2:00 PM: Lunch & Networking in Exhibit Hall

Lunch sponsored by:
EMD Performance Materials - Corporate Sponsor

 

AFTERNOON SESSION SCHEDULE

EMERGING APPLICATIONS & THE CONNECTED WORLD

2.5/3D PACKAGING & EMBEDDED PACKAGING TECHNOLOGIES

ADVANCED PACKAGING & ENABLING TECHNOLOGIES

ADVANCED MATERIALS & PROCESSES

MODELING, DESIGN, TEST & RELIABILITY

Tuesday, October 11, 2016

2:00 PM -
5:55 PM

Session TP1:
Innovative Substrates

Chairs: Doug Shelton, Canon USA; Benson Chan, Binghamton University

Session TP2:
3D Integration Materials and Processes

Chairs: Mark Gerber, ASE US; Doug Link, Starkey Hearing Technologies

Session TP3:
INVITED SESSION: Chip-Package Interactions in Fanout Wafer Level and Embedded Packages

Chairs: Rajiv Roy, Rudolph Technologies; Tengfei Jiang, University of Central Florida

Session TP4:
Materials Solutions for Different Applications

Chairs: Samson Shahbazi, Heraeus; Chris Kapusta, GE Global Research Center

Session TP5:
Advanced Solder Joint Reliability

Chairs: Tom Green, TJ Green Associates; Stevan Hunter, ON Semi.

2:00 PM - 2:25 PM

The Die Embedded and RDL Structure on the High Density Substrate (i-THOP®) for Mobile Application
Masahiro Kyozuka, Shinko Electric Industries Co., Ltd. (Tatsuro Yoshida, Noriyoshi Shimizu, Koichi Tanaka, Tetsuya Koyama)

Smart In-line Defectivity/Metrology Process Control Solution for Advanced 3D Integration
Amina Sidhoum, CEA-Leti (Nicolas Devanciard, Franck Bana, Arnaud Garnier, Nicolas Bresson, Sandra Bos, Stéphane Rey, Carlos Beitia, CEA; Dario Alliata, Darcy Hart, John Thornell, Justin Miller, Gilles Vera, Scott Balak, Rudolph Technologies)

FO-WLP: A Disruptive Technology
Jan Vardaman, TechSearch International

Innovative Uses for Plasma in the Assembly of Electronic Devices
Andy Stecher, Plasmatreat

Effects of Silicon Wafer Bump Pad structures on Solder and Cu Pillar Flip-Chip Reliability
Shannon Pan, Qorvo (Scott Exon, Liping Zhu, Shirley Asoy, Peter Moon, Mike Carroll)

2:30 PM - 2:55 PM

Co-Design and Demonstration of Fully Integrated Optical Transceiver Package Featuring Optical, Electrical, and Thermal Interconnects in Glass Substrate
Bruce Chou, Georgia Institute of Technology (Brett Sawyer, William Vis, Ryuta Furuya, Fuhan Liu, Venky Sundaram, Rao Tummala)

Characterizing and Solving Imaging Challenges in Thick Resists for Wafer and Panel Based Lithography Applications
James Webb, Rudolph Technologies Inc. (Roger McCleary)

Assessment of Optimized Process Quality and Reliability for Wafer Level Applications
Ennis Ogawa, Broadcom

Plasma Activated Bonding for an Enhanced Alignment Electrostatic Lens
Elham Vakil Asadollahei, University of California, Irvine (Manuel Gamero-Castaño)

Reliability of SAC 105 and SAC1205N Under Drop Tests
Jia-Shen Lan, National Sun Yat-sen University (Mei-Ling Wu)

3:00 PM - 3:25 PM

Glass 3D Solenoid Inductors IPD Substrate Manufacturing Assembly and Characterization
Chun-Hsien Chien, Unimicron Technology Corp. (Yu-Hua Chen, Yu-Chung Hsieh, Wei-Ti Lin, Chien-Chou Chen, Dyi-Chung Hu, Tzvy-Jang Tseng, Unimicron Technology Corp.; Ravi Shenoy, Qualcomm Inc.)

Anisotropic Conductive Film for Fine-Pitch Interconnects
Daniel Nilsen Wright, SINTEF (Branson Belle, Hoang-Vu Nguyen, Jakob Gakkestad, Helge Kristiansen, Kari Schjoelberg-Henriksen, Maaike M. Visser Taklo)

Chip Package Interaction Considerations in Fan-out Wafer Level Packaging
Urmi Ray, Qualcomm

Investigation of the Direct Plating Copper (DPC) on Al2O3, BeO or AlN Ceramic Substrates for High Power Density Applications
Ho Chieh (Jay) Yu, ICP Technology (Jason Huang)

Comparative Modeling and Analysis of Lead-free Solder Extrusion for the Design of Reliability
Youngtak Lee, Starkey Laboratories

3:30 PM - 4:30 PM: Dessert "Happy Hour" in the Exhibit Hall

IMAPS Dessert Happy Hour sponsored by Palomar:

Palomar Technologies: Dessert "Happy Hour" Sponsor

4:30 PM - 4:55 PM

Hybrid Fabrication of Flexible Munitions Circuitry Integrating Printed Electronics and COTS Components
James Zunino, US Army RDECOM-ARDEC (D. Sabanosh, G. Di Benedetto, D. Schmidt, K. Church, C. Pereira)

Detection of Low Copper Concentrations in Nickel Plating Baths
Michael Pavlov, ECI Technology (Danni Lin, Eugene Shalyt, Mitch Coffin)

FOWLP Technology eWLB - Enabler for Packaging of IoT/IoE Modules
Steffen Kroenhert, Nanium

Performance Comparison of High Temperature Pt-Based Sensor Using Pt Core-Shell Powder and Paste
Richard Stephenson, Silicon Valley Materials Technology Corp (Howard Imhof)

Reliability Analysis of Lead Free Solder Joints with Solder Doping on Harsh Environment
Cong Zhao, Auburn University (Thomas Sanders, Zhou Hai, Chaobo Shen, John Evans)

5:00 PM - 5:25 PM

Silicon based Cell Sorting Device: Fabrication, Characterization and Applications
Bivragh Majeed, IMEC (Chengxun Liu, Lut Van Acker, Koen De Wijs, Deniz Sabuncuoglu, Liesbet Lagae)

Addressing Flux Dip Challenges for 3D Integrated Large Die, Ultra-fine Pitch Interconnects
Catherine Marsan-Loyer, Université de Sherbrooke (David Danovitch, Université de Sherbrooke; Nicolas Boyer, IBM)

Experimental Study on 28nm Chip/Package Interactions in eWLB (Embedded Wafer Level BGA) Fan-Out Wafer Level Packages
Dongkai Shangguan, STATSChipPAC Inc.

Electrodeposited Copper-graphite Composites for Low-CTE Integrated Thermal Structures
Shreya Dwarakanath, Georgia Institute of Technology (Pulugurtha Markondeya Raj, Vanessa Smet, Venky Sundaram, Rao Tummala)

Design of BGA Assemblies with Enhanced Thermal Cycle Capability Using Solder Coated Polymer Balls
Thomas Marinis, Draper Labs. (Joseph Soucy)

5:30 PM - 5:55 PM

Embedded RDL formation in Non Photo Polymer using Excimer Laser Ablation
Habib Hichri, SUSS MicroTec (Seongkuk Lee, Markus Arendt, Sanjay Malik, Ognian Dimov, Raj Sakamuri, Venky Sundaram)

Ultra Thin, Low ESL and High Frequency Performance of High Density Silicon Capacitors
Franck Murray, IPDIA (Catherine Bunel)

On the Way from Fan-out Wafer to Fan-out Panel Level Packaging
Tanja Braun, Fraunhofer IZM (T. Braun, K.-F. Becker, S. Raatz, M. Minkus, V. Bader, J. Bauer, R. Aschenbrenner; R. Kahle, L. Georgi, S. Voges, M. Wöhrmann, K.-D. Lang)

Washable Coatings for Packaging Applications
John Moore, Daetec LLC (Alex Brewer)

How Mitigation Techniques Affect Reliability Results for BGAs
Greg Caswell, DfR Solutions (Melissa Keener, Black and Decker)

 

 




 

WEDNESDAY, OCTOBER 12, 2016

7:00 AM - 5:30 PM: Registration Open
11:00 AM - 6:00 PM: Exhibit Hall Open

8:00 AM - 8:15 AM: Welcome, About the Global Business Council, & Keynote Introductions (Plenary Session)
Iris Labadie, GBC Chair, Kyocera America

Keynote Sessions sponsored by:
Applied Materials - Keynote Sponsor

GBC

8:15 AM - 9:00 AM: GBC Keynote 1
Ron Huemoeller, Amkor Technology Inc.

Creating Semiconductor Value through Advanced Package Technology
Over the past few years, there has been a significant shift from PCs and notebooks to smartphones and tablets as drivers of advanced packaging innovation. In fact, the overall packaging industry is doing quite well today as a result, with solid growth expected to create a market value in excess of $30B USD by 2020. This is largely due to the technology innovation in the semiconductor industry continuing to march forward at an incredible pace, with silicon advancements in new node technologies continuing on one end of the spectrum and innovative packaging solutions coming forward on the other in a complementary fashion. The pace of innovation has quickened as has the investments required to bring such technologies to production. At the packaging level, the investments required to support the advancements in silicon miniaturization and heterogeneous integration have now reached well beyond $500M USD per year. Why has the investment to support technology innovation in the packaging community grown so much? One needs to look no further than the complexity of the most advanced package technologies being used today and coming into production over the next year.

Advanced packaging technologies have increased in complexity over the years, transitioning from single to multi-die packaging, enabled by 3-dimensional integration, system-in-package (SiP), wafer-level packaging (WLP), 2.5D/3D technologies and creative approached to embedding die. These new innovative packaging technologies enable more functionality and offer higher levels of integration within the same package footprint, or even more so, in an intensely reduced footprint. In an industry segment that has grown accustomed to a multitude of package options, technology consolidation seems evident, producing “The Big Five” advanced packaging platforms. These include low-cost flip chip, wafer-level chip-scale package (WLCSP), microelectromechanical systems (MEMS), laminate-based advanced system-in-package (SiP) and wafer-based advanced SiP designs.

This presentation will address ‘The Big Five’ packaging platforms and how they are adding value to the Semiconductor Industry.

Ron Huemoeller

Ron Huemoeller is Corporate Vice President, Worldwide R&D, at Amkor Technology. Ron joined Amkor in 1995 and has since served in multiple senior to executive level roles. Currently, Ron is responsible for global R&D and technology strategy. Prior to joining Amkor, Ron was Director of Engineering at Cray Computer Corp. in Colorado Springs for 5 years, leading the facilitation, startup and development of state of the art motherboards for the world’s fastest supercomputer. Ron has authored numerous technical publications, co-authored a chapter in the Handbook of 3D Stacking (McGraw Hill) and has been granted more than 100 U.S. patents. Ron holds a B.S. in Chemistry from Augsburg College with highest honors, a MBA in Business Management from Arizona State University and a Masters in Technology Management from the University of Phoenix.

 

9:00 AM - 9:45 AM: GBC Keynote 2
Jon Greenwood, Plexus


Strategy and Ecosystem for Microelectronics Assembly in the United States
In the 1980’s the US based electronics manufacturing and ecosystem witnessed a significant shift from manual operations to automated assembly to enable high volume, lower cost products. The maturation of surface mount technology and the introduction of organic semiconductor packaging were key drivers and enablers during this era. The 1990’s brought about the shift from the OEM microelectronics innovation & assembly ecosystem to the outsourced model as OEM’s tried to stay ahead of the cost reduction curve during this dotcom era. The end result was a short lived US based model for outsourced volume microelectronics assembly that crashed with many of the other startups in the early 2000’s. The severity of the downturn not only affected the volume assembly service model but, more importantly the innovation and development opportunities for microelectronics as well. With the recent renewed emphasis on innovation, security, reshoring and manufacturing job creation the opportunity to create a new model for microelectronics assembly in the US has successfully emerged.

Jon Greenwood

Jonathon Greenwood is currently the General Manager of the Plexus Boise, ID campus which specializes in high complexity manufacturing solutions in support of their customers. Previously he has held strategic leadership positions at GLOBALFOUNDRIES, Micron Technology, Amkor Technology and Motorola with a focus on global technology strategy, business development, operational excellence and organizational transformation. He holds a B.S. in Chemical Engineering from the University of Florida and has authored numerous patents and papers in the field of advanced semiconductor packaging including high performance flip chip, 2.5D & 3D packaging, MEMS, SiP, optoelectronics and other related technologies.

9:45 AM - 10:00 AM: Coffee Break in Foyer

Coffee Break sponsored by:
MRSI - Break Sponsor

 

 

MORNING SESSION SCHEDULE

EMERGING APPLICATIONS & THE CONNECTED WORLD

2.5/3D PACKAGING & EMBEDDED PACKAGING TECHNOLOGIES

ADVANCED PACKAGING & ENABLING TECHNOLOGIES

ADVANCED MATERIALS & PROCESSES

MODELING, DESIGN, TEST & RELIABILITY

Wednesday, October 12, 2016

10:00 AM - 11:55 AM

WA1:
Medical Applications

Chairs: Susan Bagen, Micro Systems Technologies, Inc.; Tim LeClair, Cerapax

WA2:
3D Technologies and Applications

Chairs: Jim Will, Honeywell FM&T; Anne Zeng, Northrop Grumman

WA3:
Fanout Wafer Level Packaging I

Chairs: Steffen Kroehnert, Nanium; Habib Hichri, SUSS MicroTec

WA4:
SMT

Chairs: Aicha Elshabini, University of Alaska Anchorage; Frank Eberle, Northrop Grumman

WA5:
Advanced Wire Bonding Technology for Reliability

Chairs: Matt Apanius, SMART Microsystems; Randy Hamm, Honeywell FM&T

10:00 AM - 10:25 AM

Packaging for Medical and Wellness Applications
Andre Rouzaud, CEA-Léti (M. Cartier, J-C. Souriau, G. Simon, J. Brun, G.Pares)

High Speed Serial Interfaces in 2.5D Integrated Systems
Muhammad Waqas Chaudhary, Fraunhofer IIS/EAS (Andy Heinig)

Fan-Out Wafer Level Packaging: Market and Technology Trends
J. Azemar, Yole (A. Pizzagalli, S. Kumar, A. Ivankovic, T. Buisson)

Optical Role of Die Bonding for Chip-on-Board White Light Emitting Diode Emitters
Gunwoo Kim, University of California, Irvine (Yu-Chou Shih, Frank Shi)

Advanced Wire Bonding for High Reliability and High Temperature Applications
Michael Guyenot, BOSCH (Manfred Reinold, Youssef Maniar, Martin Rittner)

10:30 AM - 10:55 AM

Package Architecture and Component Design for an Implantable Peripheral Nerve Stimulation and Recording System for Advanced Prosthetics
Tirunelveli Sriram, Draper Labs. (Carolne Bjune, John Lachapelle, Andrew Czarnecki, Alexander L. Kindle, John Burns, Julianne Grainger, Carlos Segura, Brian Nugent, Philip Parks)

Correlation of Through-silicon Via (TSV) Dimension Scaling to TSV Stress and Reliability for 3D Interconnects
Laura Spinella, University of Texas at Austin (Tengfei Jiang, Jang-hi Im, Paul Ho)

Cost Comparison of Fan-out Wafer-Level Packaging to Fan-out Panel-Based Packaging
Chet Palesko, SavanSys Solutions LLC (Amy Lujan)

Process Development and Material Characterization of Cu-Cu thermo-Compression Bonding (TCB) for High-conductivity Electrical Interconnects
Adeel Ahmad Bajwa, University of California at Los Angeles (Siva Chandra, Saptadeep Pal, Niteesh Marathe, Evangeline Lui, Mark Goorsky, Subramanian Iyer)

Effects of Probe Marks on Shear Test of Copper Ball Bonds in Two Pad Aluminum Thicknesses
Dustin Tenney, Brigham Young University (Priscila Brown, Rachel Wynder, Jacob Marsh, Stevan Hunter)

11:00 AM - 11:25 AM

Unique Silicon Passive Component Technology for Medical Implants Combining Highly Flexible Integration with Outstanding Performances
Catherine Bunel, IPDIA (Franck Murray)

Proposal of Ultra-fine and High Reliable Trench Wiring Process for Organic Interposer
Kazuyuki Mitsukura, Hitachi Chemical (Masaya Toba, Kousuke Urashima, Yoshinori Ejiri, Kenichi Iwashita, Tomonori Minegishi, Kazuhiko Kurafuchi)

Advanced Wafer Level Packaging of RF-MEMS with RDL Inductor
Seung Wook Yoon, STATSChipPAC Ltd. (Lin Yaojian, Bernard Adams, Babak Jamshidi , Paul Castillou, Roberto Gaddi, Rob van Kampen)

Investigations on Wire Bonding Capability of Selective Laser Melted Structures
Christopher Kaestle, Friedrich-Alexander University (Aarief Syed-Khaja, Joerg Franke)

Aluminum Bonding Pad Corrosion of Wirebond Packages
Varughese Mathew, NXP Semiconductors (Sheila Chopin, NXP; Oliver Chyan, Nick Ross, Alex Lambert, Muthappan Asokan, University of North Texas)

11:30 AM - 11:55 AM

Hermetic Packaging of Implantable Devices: How Did We Get Here? And Where Are We Going?
Heather Dunn, Cirtec Medical

High Aspect Ratio Bumping Process with Solder Bump included Core Pillar
Sho Nakagawa, Mitsubishi Materials Corporation (Tsukasa Yasoshima, Hironori Uno, Masayuki Ishikawa)

Optimization of Laser Release Layer, Glass Carrier, and Organic Build-up Layer to Enable RDL-first Fan-out Wafer-level Packaging
Alvin Lee, Brewer Science, Inc. (Jay Su, Baron Huang, Ram Trichur, Dongshun Bai, Xiao Liu, Brewer Science, Inc.; Leon Tsai, Bor Kai Wang, Aric Shorey, Corning Incorporated; Yu-Min Lin, Tao-Chih Chang, Wen-Wei Shen, Hsiang-Hung Chang, Chia Wei Chiang, Huan-Chun Fu, Yuan-Chang Lee, K. C. Chen, Yu-Lan Lu, Industrial Technology Research Institute)

 

Reliability of Heavy Gage Aluminum Wirebonds Under High Temperature Aging
Nishant Lakhera, NXP Semiconductors (Catherine Pronga, Emmanuel Labroye, Florence Molinie, Samuel Lesnakowksi)

 

12:00 PM - 1:30 PM: Networking & Lunch in Exhibit Hall
(EXHIBITS OPEN: 11am-6pm)

Lunch sponsored by:
EMD Performance Materials - Corporate Sponsor

 

AFTERNOON SESSION SCHEDULE

EMERGING APPLICATIONS & THE CONNECTED WORLD

2.5/3D PACKAGING & EMBEDDED PACKAGING TECHNOLOGIES

ADVANCED PACKAGING & ENABLING TECHNOLOGIES

ADVANCED MATERIALS & PROCESSES

MODELING, DESIGN, TEST & RELIABILITY

Wednesday, October 12, 2016

1:30 PM - 3:55 PM

WP1:
Additive Technologies

Chairs: John Bolger, Department of Defense; Otto Fanini, Baker Hughes

WP2:
Glass Interposers and Technologies

Chairs: Aric Shorey, Corning; Y.H. Chen, Unimicron

WP3:
Fanout Wafer Level Packaging II

Chairs: Karl-Friedrich Becker, Fraunhofer IZM; Rajiv Dunne, Qualcomm

WP4:
Polymers, Underfill, Encapsulants, and Adhesives

Chairs: Lyndon Larson, Dow Corning Electronics; Jeff Gotro, InnoCentrix

WP5:
Characterization and Modeling for Reliability

Chairs: Mary Cristina Ruales Ortega, University of Missouri, Kansas City; Ivan Ndip, Fraunhofer IZM

1:30 PM - 1:55 PM

Increasing the Reliability of 3D Printing a Wi-Fi Sensor Device
Paul Deffenbaugh, Sciperio, Inc. (D. Stramel, K.H. Church)

Addressing Next Generation Packaging and IoT with Glass Solutions
Aric Shorey, Corning Inc. (Rachel Lu, Kevin Adriance, Gene Smith)

Package Thickness - How Low can you go with WLFO
Steffen Kroehnert, NANIUM S.A. (Eoin O'Toole, José Campos, Virgilio Barbosa, Leonor Dias)

High Thermal Conductive Die Attach Paste Using Polymer and Micron Size Silver for Power Semiconductor Package
Howard (Hwa Il) Jin, Alpha Advanced Materials (Kewei Xu, Loreto Naungayan, Jose Quinones)

Computer Aided Predictive Reliability Risk Analysis for High Temperature Operation of Subsurface Electronics Development
Otto Fanini, Baker Hughes Inc. (Josh Liew)

2:00 PM - 2:25 PM

Challenges in Fine Feature Solder Paste Printing for SiP Application
Sze Pei Lim, Indium Corporation (Kenneth Thum, Andy Mackie)

3D SiP Assembly and Reliability for Glass Substrate with Through Vias
Ra-Min Tain, Unimicron Technology Corp. (Dyi-Chung Hu, Kai-Ming Yang, Yu-Hua Chen, Jui-Tang Chen)

Ultra-High Density System-in-Package (SiP) for The Lowest Size Weight and Power (SWAP)
Bruce Barbara, Aurora Semiconductor LLC.

New Low Temperature Alloy Core-Shell Structures for Joining Applications
Richard Stephenson, Silicon Valley Materials Technology Corp. (Kyle Bandaccari, Howard Imhof)

Electrical Characterization of Low-Profile Copper Foil for Reduced Surface Roughness Loss
Qianfei Su, San Diego State University (A. Ege Engin, Jerry Aguirre)

2:30 PM - 2:55 PM

Digital Manufacturing and Performance Testing for Military Grade Application Specific Electronic Packaging (ASEP)
C. Mike Newton, Sciperio (Nathan Crane, USF; James Zunino, Army RDE Command; Clayton Neff, Justin Nussbaum, Eric Tridas, USF; Paul Deffenbaugh, Kenneth Church, Sciperio)

Fabrication and Characterization of Advanced Through Glass Via Interconnects
Timothy Clingenpeel, University of Florida (Arian Rahimi, Seahee Hwangbo, Aric Shorey, Yong-Kyu Yoon)

New Laser-Based FOWLP Processes for High I/O Applications with Ultra-Fine Line Routing and Sub 4 Um Vias
Markus Woehrmann, Fraunhofer IZM (Robert Gernhardt; Karin Hauck; Kevin Kroehnert; Kai Zoschke; Olaf Wuensch; Nils Juergensen; Michael Toepper; Tanja Braun; Klaus-Dieter Lang)

Pre-applied Inter Chip Fill Material for 3D Chip Stack Integration - How to Improve Bonding Quality and Reliability
Kan Takeshita, Mitsubishi Chemical Corporation (Masaya Sugiyama, Makoto Ikemoto, Hidehiro Yamamoto, Hideki Kiritani, Tetsuharu Yuge, Kuni Shin, Hiroya Kodama, Yashuhiro Kawase)

3D TSV-based Inductor Design for Secure Internet of Things
Bruce Kim, City University of New York (Sang Bock Cho, University of Ulsan)

3:00 PM - 3:25 PM

Additive Printing of Tight Tolerance Embedded Components via High Precision Shadow Masking and Their Integration with Traditional Circuit Board Manufacturing
Scott Lauer, Advantech U.S.

Ultra-thin Glasses for Semiconductor Packaging
Ruediger Sprengard, SCHOTT AG (Matthias Jotz, Martin Letz, Lutz Parthier, Fredrik Prince, J. U. Thomas, SCHOTT AG; Markus Wöhrmann, Michael Töpper, Fraunhofer IZM)

Photolithography Alignment Mark Transfer System for Low Cost Advanced Packaging and Bonded Wafer Applications
Tom Swarbrick, Rudolph Technologies (Keith Best, Steve Gardner, Casey Donaher)

Effect of Vapor-Deposited Parylene Coating on Reliability of Sintered Silver Joints for Extreme Temperature Applications
Zhenzhen Shen, Baker Hughes (Otto Fanini, Aleksey Reiderman)

Simulation and Measurement of Power Distribution Networks (PDN)
Aicha Elshabini, University of Alaska Anchorage (Fred Barlow, University of Alaska Anchorage; Pin Jen Wang, Sharmin Islam, University of Idaho)

3:30 PM - 3:55 PM

Investigation of Defects in Thin Silicon Oxynitride Film by Cu Electroplating for Organic Device Encapsulation
Kunmo Chu, Samsung Advanced Institute of Technology

Glass Based Inductors, Capacitors and System-In-Package for RF Applications
Jeb Flemming, 3D Glass Solutions (Kyle McWethy, Roger Cook)

Assembly Equipment Requirements for Next Generations Advanced Packaging
Bob Chylak, Kulicke and Soffa Industries, Inc. (Tom Strothmann, Horst Clauberg)

High Viscosity Paste Dosing for Microelectronic Applications
Tina Thomas, TU Berlin (S. Voges, K.-F. Becker, M. Koch, M. Fliess, J. Bauer, T. Braun, M. Schneider-Ramelow, K.-D. Lang)

Spurious Turn-On inside a Power Module of Paralleled SiC MOSFETs
Zichen Miao, Virginia Tech (Khai D. T. Ngo)

4:00 PM - 6:00 PM:
HAPPY HOUR in the Exhibit Hall

Happy Hour sponsored by:

Heraeus Materials Technology - Premier Sponsor, Gold

 


 

 

THURSDAY, OCTOBER 13, 2016

7:00 AM - 3:00 PM: Registration Open
NO EXHIBITS – Exhibitor Move-Out

 

MORNING SESSION SCHEDULE

EMERGING APPLICATIONS & THE CONNECTED WORLD

2.5/3D PACKAGING & EMBEDDED PACKAGING TECHNOLOGIES

ADVANCED PACKAGING & ENABLING TECHNOLOGIES

ADVANCED MATERIALS & PROCESSES

MODELING, DESIGN, TEST & RELIABILITY

Thursday, October 13, 2016

8:00 AM - 11:10 AM

THA1:
Power Devices

Chairs: Doug Hopkins, North Carolina State University; Kyu-oh Lee, Intel Corp.

THA2:
Embedded Packages

Chairs: Chet Palesko, Savansys; Zhenzhen Shen, Baker Hughes

THA3:
Wire Bonding

Chairs: Dan Evans, Palomar Technologies; Martin Schneider-Ramelow, Fraunhofer IZM

THA4:
Semiconductor Processes & Thermal Management

Chairs: Kevin Mercurio, Northrop Grumman; John Mazurowski, Penn State Electro-Optics Center

THA5:
Design of QFN and WL-CSP for Reliability

Chairs: Tim Jensen, Indium Corp.; Vicentiu Grosu, Teledyne

8:00 AM - 8:25 AM

The Reliability of Ag Wedge Bonding with Various Bonding Pads for Power Devices
Xing Wei, Waseda University (Zhou Yu, Ge Yan, Tomonori Iizuka, Kohei Tatsumi)

Higher Efficiency Power Module Integrated Solution by Chip Embedding
Kay Essig, ASE Group (CT Chiu, Jarris Kuo, Phidia Chen, Jean-Marc Yannou)

A Deeper Understanding on the Motion Behaviors of Wire during Ultrasonic Wedge-Wedge Bonding Process
Yangyang Long, Leibniz University Hannover (Folke Dencker, Marc Wurz, Jens Twiefel, Armin Feldhoff)

High Selective Wet Silicon Etch Chemistry and Process for Advanced Semiconductor Packaging
Yongqiang Lu, SACHEM Inc (Sian Collins, Laura Mauer, John Taddei, John Clark)

Behaviors of QFN Packages on a Substrate Strip
Eric Ouyang, STATSChip PAC (Billy Ahn, Seng Guan Chow, Anonuevo Dexter, SeonMo Gu, YongHyuk Jeong, JaeMyong Kim)

8:30 AM - 8:55 AM

NEW PRESENTATION:
Ultra Low Leakage Module for 12kV-225˚C SiC Semiconductor Testing

Douglas Hopkins, North Carolina State University (Haotao Ke, Xin Zhao, Yifan Jiang, Adam Morgan, Yang Xu)

ORIGINAL PRESENTATION WITHDRAWN BY AUTHOR ON 9/26:
Pendulum Generators to Power Wearable Devices from Human Motion
Edwar Romero, Universidad del Turabo (Jose Montoya, Dulce Mariscal, Eduardo Castillo, Bernardo Restrepo)

NEW PRESENTATION:
Direct Write Lithography Approach for Panel Level Package
Hiroshi Matsui, SCREEN Semiconductor Solutions

ORIGINAL PRESENTATION MOVED TO POSTER SESSION:
Effect of Temperature/Humidity Treatment on Interfacial Reliability on Screen-Printed Ag / Polyimide for Advanced Embedded Packaging Technologies
Kyu Hawn Lee, Korea Instittue of Materials Science (Byung-Hyun Bae, Min-Su Jeong, Jeong-Kyu Kim, Young-Bae Park)

Ultrasonic System Normalization on Wedge Bonders
Omid Niayesh, Kulicke & Soffa Industries, Inc. (Vaughn Svendsen, Raymond Chen, Jason Fu)

Temporary Wafer Bonding Materials with Mechanical/Laser Debonding Technologies for Semiconductor Device Processing
Xiao Liu, Brewer Science Inc.

Evaluating the Effect of SMT Material & Process Variables on Voiding Under QFNs
Maria Durham, Indium Corporation (Brandon Judd)

9:00 AM - 9:25 AM

Thermal and Electrical Characterizations of Ultra-Thin Flexible 3YSZ Ceramic for Electronic Packaging Applications
Xin Zhao, North Carolina State University (K. Jagannadham, Wuttichai Reainthippayasakul, Michael. Lanagan, Douglas Hopkins)

Novel Mold-free Fan-out (MFFO) Wafer Level Package using Silicon Wafer
Vivek Sridharan, Maxim Integrated (Amit Kelkar, Khanh Tran, Anu Srivastava, Viren Khandekar, Ricky Agrawal)

Design and Process Considerations in Transitioning From Aluminum Wire to Aluminum Ribbon
Tom Bobal, Coining Inc. (Charles Italiano, Y. Mindin, M. Oud)

In-situ Measuring Module for Transfer Molding Process Monitoring
Ruben Kahle, Technical University Berlin (Tanja Braun, Jörg Bauer, Karl-F. Becker, Martin Schneider-Ramelow, Klaus-Dieter Lang)

Minimizing Voiding in Bottom Terminated Components by Optimizing the Solder Paste Flux
Ed Briggs, Indium Corporation

9:25 AM - 10:00 AM: Break in the Foyer

Sponsored by:
Shenmao - Event Sponsor

10:00 AM - 10:25 AM

Power Device Packaging Targeting High Temperature Operation with Maximum Tcase = 250C
Shijo Nagao, Osaka University (Zhang Hao, Takuo Sugioka, Satoshi Ogawa, Teruhisa Fujibayashi, Katsuaki Suganuma)

Isothermal DSC Study of the Curing Kinetics of an Epoxy/silica Composite for Microelectronics
Lerys Granado, Atotech Deutschland GmbH (Stefan Kempa, Stefanie Wiese, Laurence Gregoriades, Frank Bruening, Eric Anglaret, Nicole Fréty)

Consumable and Process Improvement for Large Copper Wire Bonding
Tao Xu, Kulicke & Soffa Industries, Inc.

Improvement of Coherency of the Panel Level Package by Integrated Dry Process
Shinichi Endo, Ushio Inc. (Tomoyuki Habu, Akira Aiba, Hiroko Suzuki, Noritaka Takezoe, Hiroki Horibe, Kazuki Arikawa, Masaki Miura, Hajime Kikuiri,Shintaro Yabu)

Optimizing Board Level Reliability of a Novel LGA Package for IoT Applications -- NEW PRESENTATION TOPIC
Tara Assi, NXP Semiconductors (Paul Galles, Andrew Mawer, Trent Uehling and Steve Safai)

10:30 AM - 10:55 AM

Ultrasonic Bonding on Unstable Pin
Henri Seppaenen, Kulicke and Soffa (Jason Fu)

Wedge Bonding Wire and Ribbon to Support RF and Optoelectronic Packaging
Daniel Evans, Palomar Technologies (Wenjuan Qi, Kevin Bauder)

Performance Evaluation of Gold (Au) Wire and Ribbon Interconnects in High Frequency Circuits
Cenk Atalan, ASELSAN A.S (Taylan Eker)

Joint Healing Thermal Interface Material
Jingting Yang, Laird (Jason Strader, Sean Orzolek, Eugene Pruss, Laird; Phillip Fosnot, Jesse Galloway, Amkor)

WITHDRAWN BY AUTHOR ON 9/19:

Impact of Cleaning Technologies on Lead Frame Packages: The Difference in Wire Bond Yields
Ravi Parthasarathy, ZESTRON Americas (Larry Park, Umut Tosun, GT Yeoh)

11:00 AM - 11:25 AM


 

Advances in Wire Bonding Technology for Overhang Applications
Aashish Shah, Kulicke & Soffa Industries Inc (Nestor Mendoza, Rob Ellenberg, Gary Schulze, Ivy Qin, Bob Chylak)

Metallic TIM Testing and Selection for IC, Power, and RF Semiconductors
Tim Jensen, Indium Corporation (David Saums, DS&A LLC)

Understanding Whisker Growth: Effect of Substrate and Underlayer
Piyush Jagtap, Indian Institute of Science, Bangalore (Praveen Kumar)

 

 

11:30 AM - 1:00 PM: Posters & Pizza in the Foyer
Interactive Poster Session in the Foyer starting at 11:30 AM
(Pizza served from 12:00 PM - 1:00 PM)

Chairs: Erica Folk, Northrop Grumman Corporation; Dan Krueger, Honeywell FM&T

Posters & Pizza Sponsored by:


Feasibility Studies on Selective Laser Melting of Copper Powders for the Development of High-temperature Circuit Carriers
Aarief Syed-Khaja, Friedrich-Alexander-University Erlangen-Nuremberg, Institute FAPS (Christopher Kaestle, Joerg Franke)

Optimization of Processing Condition for Isotropic Conductive Paste using Cu and Solder Powder
Yong-Sung EOM, Electronics and Telecommunications Research Institute (Ji-Hye SON, Hyun-Cheol BAE, Kwang-Seong Choi, Jin-Ho LEE)

SigNature DNA Program and Product Updates Across a Broad Range of Industries -- WITHDRAWN BY SPEAKER ON OCTOBER 5
Janice Meraglia, Applied DNA Sciences (Bob MacDowell)

Development and Challenges of Warpage for Fan-Out Wafer-Level Package Technology
Mu-Hsuan Chan, Siliconware Precision Industries Co., Ltd. (Yu-Po Wang, Ivan Chang, James Chiang, George Pan, Nicholas Kao, David Wang)

Paying by the Micron - ED-XRF Analysis of Consumer Products
Brian Goolsby, Hitachi High-Technologies America, Inc.

NSOP Reduction for QFN RF-IC Packages
Mumtaz Bora, Peregrine Semiconductor

Introduction to a New Silicone Adhesive Designed for Wearables Technologies
Michelle Poliskie, NuSil (Javier Fregoso, Robert Krizan)

High Speed Fluorescent Inspection of Non-visible Defects
Gurvinder Singh, Rudolph Technologies (Chet Suresh, John Thornell, Woo Young Han)

Effect of Temperature/Humidity Treatment on Interfacial Reliability on Screen-Printed Ag / Polyimide for Advanced Embedded Packaging Technologies
Kyu Hawn Lee, Korea Instittue of Materials Science (Byung-Hyun Bae, Min-Su Jeong, Jeong-Kyu Kim, Young-Bae Park)

Direct Write Lithography Approach for Panel Level Package (ALSO PRESENTED IN SESSION THA2)
Hiroshi Matsui, SCREEN Semiconductor Solutions

The Impact of Stencil Printing Upon Assembly & Reliability of 0.3mm Pitch CSP Components (ALSO PRESENTED IN SESSION THP5)
Mark Whitmore, ASM Assembly Systems (Jeff Schake)

Isothermal DSC Study of the Curing Kinetics of an Epoxy/silica Composite for Microelectronics (ALSO PRESENTED IN SESSION THA2)
Lerys Granado, Atotech Deutschland GmbH (Stefan Kempa, Stefanie Wiese, Laurence Gregoriades, Frank Bruening, Eric Anglaret, Nicole Fréty)

Washable Coatings for Packaging Applications (ALSO PRESENTED IN SESSION TP4)
John Moore, Daetec LLC (Alex Brewer)

Role of Crystallographic Texture and Local Stress Field on Whisker Growth from Electrodeposited Sn (RELATED TO PRESENTATION IN SESSION THA5)
Piyush Jagtap, Indian Institute of Science, Bangalore (Praveen Kumar)

Thermoplastic EXTEM™ Resins for Optical Components Assembled via Lead-Free SMT (NEW)
Peter Johnson, SABIC (Gabrie Hoogland)

Smartflux Dipping Paste for Advanced Packaging (NEW)
LiSan Chan, Heraeus Singapore

Pressureless Low Temperature Sinter Paste for NiAu substrate (NEW)
Ling Xin Yong, Heraeus Electronics Technology (Tan, Juo Yan; Schmitt, Wolfgang; Nachreiner, Jens; Chew, Ly May)

Improvement of Coherency of the Panel Level Package by Integrated Dry Process (ALSO PRESENTED IN SESSION THA4)
Shinichi Endo, Ushio Inc. (Tomoyuki Habu, Akira Aiba, Hiroko Suzuki, Noritaka Takezoe, Hiroki Horibe, Kazuki Arikawa, Masaki Miura, Hajime Kikuiri,Shintaro Yabu)

 

 

AFTERNOON SESSION SCHEDULE

EMERGING APPLICATIONS & THE CONNECTED WORLD

ADVANCED MATERIALS & PROCESSES - 2

ADVANCED PACKAGING & ENABLING TECHNOLOGIES

ADVANCED MATERIALS & PROCESSES

MODELING, DESIGN, TEST & RELIABILITY

Thursday, October 13, 2016

1:00 PM - 3:25 PM

THP1:
MEMS & Sensors

Chairs: Andre Rouzaud, CEA-Léti; Gabriel Pares, CEA-Léti

THP2:
LTCC and Ceramic Technologies

Chairs: Thomas Bartnitzek, Micro Hybrid; Howard Imhof, Silicon Valley Materials Technology Corp

THP3:
Package on Package, BGA, Flip Chip

Chairs: Bill Marsh, Northrop Grumman; Bob Chylak, Kulicke & Soffa

THP4:
Reliability and Soldering Application

Chairs: Maria Durham, Indium Corp.; Seungwook Yoon, STATS ChipPAC, Ltd.

THP5:
Reliability of Sensor, Connector and Flash Memory

Chairs: Woong-Sun Lee, SK Hynix;

1:00 PM - 1:25 PM

Alternative Metallurgies for MEMS Lid Seal
Catherine Shearer, Ormet Circuits, Inc EMD Performance Materials

Novel Core-Shell Conductive Materials for LTCC Metallizations
Richard Stephenson, Silicon Valley Materials Technology Corp (Kyle Bandaccari, Howard Imhof)

Challenges in Assembly Implementation of Ultra-thin Profile Flipchip Package-on-Package
Abu Eghan, Open Silicon

Achieving Low Voiding with Lead Free Solder Paste for Power Devices
Pierino Zappella, SST International (Saeed Sedehi, Robert Hizon, Adrienne Williams)

Fire Damage and Repair Techniques for Flash Memory Modules: Implications for Post Crash Investigations
Preeth Sivakumar, Binghamton University (Jack Lombardi, Stephen Cain)

1:30 PM - 1:55 PM

A Comparison of Immersion Gold and Tin Surface Finishes on Sensing Electrodes for PCB Environmental Saltwater Concentration Sensors
Robert Dean, Auburn University (Frank Werner)

Evaluation of a Lead-Free Ultra Low Fire Ceramic (ULTCC) Tape Designed for Lamination on Aluminum Substrates and a Compatible Co-Fireable Silver
Steven Grabey, Heraeus Electronics (Samson Shahbazi, Ryan Persons)

Enabling Low Warpage on Low-Profile BVA™ Package On Package (PoP)
Akash Agrawal, Invensas Corporation (Ashok Prabhu, Min Tao, Wael Zohni)

Transient Liquid Phase Sintering Materials (TLPS) vs. Conventional Solders for High Temperature MLCC Interconnects
John McConnell, KEMET Corporation (J. Bultitude, L. Jones, J. Qazi)

High-Temperature Acoustic Fluid Velocity Sensor Development
Otto Fanini, Baker Hughes, Inc. (Imran Moton, Rocco DiFoggio, Josh Liew, Otto Fanini)

2:00 PM - 2:25 PM

Thermal Measurement and Modelling of Nuclear Waste in the Double Shell Tanks at Hanford Nuclear Waste Site using Miniature Sensors
Aparna Aravelli, Florida International University (Dwayne McDaniel, Anthony Abrahao, Amer Awwad, Clarice Davila)

Advantages and Limitations of Ceramic Packaging Technologies in Harsh Applications
Thomas Bartnitzek, Micro Hybrid Electronic GmbH (Torsten Thelemann, Stefan Apel, Karl-Heinz Suphan)

Novel Glass Substrates for Minimizing Thermal Stress Development during Electronic Device Packaging Process
Shuhei Nomura, Asahi Glass Co., Ltd. (Shigeki Sawamura, Yu Hanawa, Yusuke Sakai, Kazutaka Hayashi)

Voiding Control at Preform Soldering
Ning-Cheng Lee, Indium Corporation (Arnab Dasgupta, Elaina Zito)

Effects of X-ray Exposure on NOR and NAND Flash Memory Devices During High-resolution 2D and 3D X-ray Inspection
Anju Sharma, Binghamton University (Preeth Sivakumar, Andrew Feigel, In-Tae Bae, Steve Cain, Larry Lehman, Joseph Gregor, James Cash, Joseph Kolly)

2:30 PM - 2:55 PM

An Integrated Sensor for Detecting Moisture Ingress in Printed Circuit Board Assemblies
Robert Dean, Auburn University (Nathan Loden, Curtis Hartley, Jeffery Craven)

New Ferrimagnetic Garnets for LTCC-Technology Circulators
Lilia Qassym,Thales Research and Technology (Gérard Cibien, Richard Lebourgeois, Gilles Martin, Dorothée Colson)

Measuring Die Tilt Using Shadow Moiré Optical Measurements; New Techniques for Discontinuous and Semi-Reflective Surfaces
Neil Hubble, Akrometrix

Study of Void Formation Mechanism in Electroplated SnAg Solder Bump
Koji Tatsumi, Mitsubishi Materials Corporation (Akio Sakai, Syunsuke Kawai, Takuma Katase, Takashi Miyazawa, Masayuki Ishikawa)

iNEMI Connector Reliability Test Recommendations Project Report
Vincent Pasucci, TE Connectivity

3:00 PM - 3:25 PM


NEW PRESENTATION ADDED:

The Relevance of LTCC in 5G Technology
Ton Schless, SIBCO LLC (Frank Chen, Allen Chang)
ABSTRACT: LTCC ceramic technology has been the key technology in high frequency micro wave applications as well as the preferred packaging technology for applications in harsh environments like automotive electronics. The new 5G technology and with that the IoT requirements demand the same micro wave antenna and Tx/Rx module performance and harsh environment requirements for which LTCC multi chips modules are the preferred technology. This presentation will address the 5G applications and the solutions that require LTCC for specific 5G applications.

 

The True Cost of Hermeticity in Microelectronic Packaging
Timothy Dittman, Northrop Grumman Mission Systems (Alex Bailey, Steve Smalley)

The Impact of Stencil Printing Upon Assembly & Reliability of 0.3mm Pitch CSP Components
Mark Whitmore, ASM Assembly Systems (Jeff Schake)

 

Register Online

 

 


Student Presenters:

The Microelectronics Foundation sponsors Student Paper Competitions and Awards in conjunction with IMAPS 2016. Students submitting their work and identifying that "Yes, I'm a full-time student" on the abstract submission form, will automatically be considered for these awards. The review committee will evaluate all student papers/posters and award the following at the 2016 Symposium:

  • Three (3) "Outstanding Student Paper" Awards - $500 Each Award
  • One (1) "Best Student Paper of Symposium" Award - $2000 Award
  • One (1) "Best Student Poster Presentation" Award - $250 Award

The selected student must attend the event to present his or her work and receive the award.

The Microelectronics Foundation

 

IMAPS 2016 Poster Session:
Interactive Poster Session Student papers will be considered for this interactive session. Students submitting abstracts for the poster session will be required to submit a full paper which will be PEER-REVIEWED and considered for paper and poster awards noted above. If you are interested in presenting in the interactive session at IMAPS Symposium, select the "Poster Session" option under the session field on the abstract submission form.

 


Speaker/Author Information:

 
  • Notice of Acceptance: June 1, 2016
  • Manuscripts Due for Peer-Review: July 15, 2016
  • Peer-Review Comments to Author: August 29, 2016
  • Final Papers Due To IMAPS: September 14, 2016
  • Early Registration / Hotel Deadline: September 14, 2016
  • Speaker Bios Due: October 1, 2016
  • Powerpoint/Presentation file used during session:
    • Speaker's responsibility to bring to session on USB
    • Recommended to have back-up on personal laptop or email to bschieman@imaps.org prior to event
  • Technical Presentation Time: 25 minutes (20 to present; 5 for Q&A)
  • Keynote Presentation Time: 45 minutes (40 to present; 5 for Q&A)

Paper Format/Template
IMAPS emailed all the speakers the required paper template upon acceptance and with instructions for paper submission and peer review.

Presentation Format/Template:
IMAPS does not require you to use a conference powerpoint template.
You are able to use your regular company/preferred powerpoint templates.
Please include the IMAPS show name and dates on your template and/or an IMAPS logo.

Dress Code:
There is no officially "dress code" for IMAPS Conferences. We ask you to be BUSINESS CASUAL or whatever more you prefer. Most speakers tend to be in business pants and button down/company logo shirts (Women in dresses or the same). Suits, sport coats and ties are common as well. We do not recommend casual attire.

Session rooms will be equipped with:
Screen, projector, podium, IMAPS laptop (with Microsoft Windows and recent OFFICE suite), microphone, and slide remote/laser pointer.

All session presentations are 20 minutes followed by 5 minutes for Questions
You are required to load your powerpoint/presentation onto the session laptop yourself using your USB drive.
Speak with your session chair if you need assistance.

About the Session:
Sessions begin with Session Chairs making general announcements. Session Chairs will then introduce speakers by reading BIOs. Speaker will present for 20 minutes, followed by 5 minutes for questions. Session Chairs will thank the speakers. This process is repeated for each speaker in the session. Many sessions will take refreshment breaks (see program).

Poster Session/Information
The poster session is planned to be an INTERACTIVE presentation. This means you do not start and complete a scheduled talk without interuption like in a regular/oral session. Speakers should have talking points and be at their poster throughout the entire session. You can "present" your scheduled materials, but more often the attendees will review your slides and ask questions. Or you can watch them and talk to them depending on which slide they are on. .

Authors may either print out each of their powerpoint slides on regular paper and tack them up in order, or prepare a large poster (or 2 even). Recommended poster size is typically 3x4 feet, with the max space on the board being 4 ft high x 8 ft wide. IMAPS staff will provide tacks to secure your print outs. The session is first-come-first-serve so there are not assigned poster boards/locations. POSTER SETUP FROM 10AM UNTIL 11:15AM.

Photography is not permitted in the session rooms.

Silence all mobile phones during session attendance.


Special Paper Recognition - Cash Awards Offered!

6 "Best of Track" Outstanding Papers - Six (6) $500 Cash Awards
Six "Best of Track" Winners will then be reviewed for...

1 Best Paper of the Symposium - One (1) additional $500 Cash Award for a "Best of Track" Winner


IMAPS Microelectronics Foundation Student Paper Awards
The Foundation is offering CASH AWARDS to the best papers submitted and presented by students at IMAPS 2015.

 

Registration & Hotel Information:
(Early Registration Deadline: September 14, 2016)
| REGISTER ONLINE

Full attendee registrations (not exhibits only) includes the Opening Ceremonies, IMAPS Annual Business Meeting, IMAPS Awards Ceremony, Keynote Presentations, Welcome Reception, Technical Sessions, GBC Plenary Session, Panel Discussion, Exhibit attendance, Breaks, Exhibit Hall Reception on Wednesday, Exhibit Hall Lunch on Tuesday, one 2016 Proceedings Download (and access via our Mobile APP) and an automatic one-year IMAPS membership renewal for individual and student members in good standing at the time of registration. For an additional fee you can register for a Professional Development Course (PDC), the Golf Tournament, and other activities/purchases. All prices below are subject to change.

Full Symposium cancellations will be refunded (less a $100 processing fee) only if written notice is postmarked on or before September 14, 2016. No refunds will be issued after that date.

ALL PRICING BELOW MAY CHANGE

Type
Early Fee
Through 9/14/2016
Advance/Onsite Fee
After 9/14/2016
IMAPS Member
$775
$875
Non-Member
$875
$975
Speaker
$625
$725
Chair
$625
$725
Chapter Officer
$625
$725
Student (IMAPS Member)
$50
$75
Student (Non-Member)
$75
$100
Exhibits Guest Pass - NO LUNCH INCLUDED
Complimentary
Complimentary
ADDITIONAL REGISTRATION FEES:
Short Course "PDC" (one 2-hour course: Monday)
$300
$400
Golf (1 Golfer, Monday)
$125
$125

Register Online

 

Hotel Reservations (Hotel Deadline: September 14, 2016)
Reservations must be made directly with the:

Sheraton Pasadena Hotel (HOST HOTEL - NEXT DOOR TO CC)
Single/Double: $209 + taxes/fee
REGISTER ONLINE

Hilton Pasadena Hotel (6-minute Walk to CC)
Single/Double: $195 + taxes/fee
REGISTER ONLINE

Book your hotel reservation today! We have reserved a block of rooms at the host hotel to accommodate our attendees. The discounted room rates are only available until the hotel deadline listed above, or until the room block sells out (and they often sell out early - before the expire dates). Reservations received after the noted deadline or after the room block has been filled may be subject to significantly higher rates. IMAPS room blocks at most hotels historically sell out ahead of the discount deadline, so we encourage you to make your hotel reservations quickly for the best price and availability.

Hotel Scams Alert - The only way to book a room in the official IMAPS Housing Block using the reservations information above. IMAPS does not authorize any other hotel service/group to operate on its behalf.

 

 


PREMIER Sponsors:

 

    Premier Program Sponsor:
Premier Program Sponsor - Heraeus Materials Technology

    Premier Technology Sponsor:

    Premier Technology Sponsor:
    Premier Technology Sponsor:
Premier Tech Sponsor - Metalor
Premier Tech Sponsor - Indium Corp.
Premier Tech Sponsor - NGK NTK
Event Sponsors:
Dessert "Happy Hour" Sponsor:

Palomar Technologies: Dessert "Happy Hour" Sponsor
Posters & Pizza Sponsor:

Northrop Grumman EC - Poster Session Sponsor
Keynote Sponsor:

Applied Materials - Keynote Sponsor

Lunch Sponsor:
EMD Performance Materials - Corporate Sponsor

Student Programs Sponsor:
Honeywell - Student Programs Sponsor

Coffee Break Sponsor:

Fujifilm Dimatix - Coffee Break Sponsor

Coffee Break Sponsor:
MRSI - Break Sponsor

Coffee Break Sponsor:
Shenmao - Event Sponsor

Golf Sponsors
EMD Performance Materials - Corporate Sponsor
Technic - Golf Hole Sponsor
MicroScreen - Golf Sponsor
golf holes still available
Media Sponsors
Media Sponsor: MEMS Journal
Media Sponsor: US Tech
Solid State Technology - Media Sponsor
Media Sponsor: MEPTEC
3D Incites - Media Sponsor
Media Sponsor: Webcom - Antenna Systems & Technology
Media Sponsor: Webcom - Electronics Protection
Media Sponsor: Webcom - Thermal News
Media Sponsor: Chip Scale Review
GlobalSMT - Media Sponsor
   

 




CORPORATE PREMIER MEMBERS
  • Amkor
  • ASE
  • Canon
  • EMD Performance Materials
  • Honeywell
  • Indium
  • Kester
  • Kyocera America
  • Master Bond
  • Micro Systems Technologies
  • MRSI
  • NGK NTK
  • Palomar
  • Plexus
  • Promex
  • Qualcomm
  • Quik-Pak
  • Raytheon
  • Specialty Coating Systems