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IMAPS 2017 - Raleigh

IMAPS 2017 - Raleigh
IMAPS 50th Anniversary Symposium
www.imaps2017.org | www.imaps50th.org

Conference:
October 10-12, 2017
Exhibition:
October 10-11, 2017
Professional Development Courses:
October 9, 2017
General Chair:
Dan Krueger
Honeywell FM&T
Technical Chair:
Mary Cristina Ruales Ortega
University of Missouri, Kansas City
Technical Co-Chair:
Andre Rouzaud
CEA Leti

 
    PREMIER PROGRAM SPONSOR:
 
 
Premier Program Sponsor - Heraeus Materials Technology

 

    PREMIER TECHNOLOGY SPONSOR :

   PREMIER TECHNOLOGY SPONSOR:
   PREMIER TECHNOLOGY SPONSOR:
Premier Tech Sponsor - NGK NTK
Premier Tech Sponsor - EMD Performance Materials
available

Professional Development Courses
(PDCs / Short Courses / Tutorials)

Register Online | Call for History

   

 

Monday, October 9: 2-hour formats, by theme/track
8:00 AM-10:00 AM | 10:30 AM – 12:30 PM | 1:00 PM – 3:00 PM | 3:30 PM – 5:30 PM
*Attendees can take ONE PDC during each timeslot*

  Track A:
Intro to Microelectronics Packaging
Track B:
Next Generation Packaging Challenges
Track C:
Baseline and Emerging Technologies
Track D:
Reliability
8:00 AM-10:00 AM A1: Introduction to System in Package (SiP) – The Heterogeneous Integration Driver - Mark Gerber, ASE Group

B1: Emerging Challenges in Semiconductor Packaging - Raja Swaminathan, Intel

C1: 2.5D IC Integration and TSV-less Interposers - John Lau, ASM Pacific Technology D1: Choosing Solders for the New Era: Low cost High Reliability Solder Alloy - Ning-Cheng Lee, Indium Corporation
10:00 AM-10:30 AM
Coffee / Networking
Open to all PDC participants
10:30 AM – 12:30 PM A2: Wire bonding Fundamentals - Lee Levine, Process Solutions Consulting

(*NEW TIME: 10:30 AM - 12:30 PM*)
B2: Introduction to Package-on-Package (PoP) Design, Assembly and Quality: Focus on New Trends and Applications for Advanced Packaging - Fernando Roa, Amkor Technology, Inc C2: Workmanship Standards for Advanced Hybrids, ICs and Microwave Assemblies - Tom Green, TJ Green Associates D2: A Methodology for Understanding the Reliability of Electronic Packaging - Greg Caswell, DfR Solutions
12:30 PM-1:00 PM
Lunch
Open ONLY to PDC participants taking morning AND afternoon courses
1:00 PM-3:00 PM A3: Fundamentals of 3D and 2.5D Packaging Integration - Urmi Ray, STATS ChipPAC

(*NEW TIME: 1pm-3pm*)
B3: Introduction to Fan Out Packaging - John Hunt, ASE Group C3: Photonic Interconnects - an Overview - Kannan Raj, Oracle D3: Package/Board Level Integrity & Solder Joint Reliability - Jennie Hwang, H-Technologies Group
3:00 PM-3:30 PM
Coffee / Networking
Open to all PDC participants
3:30 PM-5:30 PM A4: Introduction to Copper Pillar Flip Chip Interconnect - Mark Gerber, ASE US Inc. B4: Fan Out Packaging Evolution & Complexity - John Hunt, ASE Group C4: Heterogeneous Packaging of Wide Band Gap Power Electronics: Moving from IPM to SiP - Doug Hopkins, North Carolina State University D4: Copper and Gold Ball Bonding: Intermetallics, Aging and Bond Reliability - Lee Levine, Process Solutions Consulting
5:30 PM-7:30 PM
Welcome Reception
Open to all IMAPS 2017 participants

 

Cost for Each PDC: $300 (on/before 9/8/2017); $400 (after 9/8/2017)
Register Online

 

Get off line and learn Face to Face...Sign up for a PDC!

PDCs (Professional Development Course) are a big part of the Annual IMAPS Symposium each year. Why not plan to take a course on Monday before IMAPS 2017 kicks off and take advantage of the rich learning opportunities available at the IMAPS symposium.

PDCs are all now scheduled for 2-hour lessons. Shorter courses for you to digest great information without being overwhelmed by a 4-8 hour commitments after your travels! The shorter tutorials also allow for you to participate in more topical areas and learn from a variety of instructors! The courses are also now arranged under 4 "TRACK" categories: (A) - Introduction to Microelectronics Packaging; (B) Next Generation Packaging Challenges; (C) Baseline and Emerging Technologies; and (D) Reliability.

PDCs create a unique environment whereby students can personally interact with the instructors, and with each other in the classroom and over lunch. It's mentally stimulating and the new found professional connections will prove to be valuable in the long run. Learning on line is fine, but it cannot duplicate hours spent immersed in a specific topic, led by an industry expert in the field and surrounded by like-minded professionals.

This year we've put together another impressive assortment course options Our goal is to make the IMAPS PDCs the premier learning experience; so we ask that you take time to fill out the evaluation form that accompanies each course and give us your feedback on this or any other aspects of the PDCs. Read through the course descriptions on line and pick the course that best suits your company and career objectives. Every PDC includes a full set of comprehensive course notes. Class sizes typically range from ten to thirty students and there is always ample time for questions and networking. We hope you will consider joining us in Raleigh for a learning experience like no other.

Education is a lifelong pursuit, don't miss out on this opportunity!
Tom Green and Urmi Ray
IMAPS 2017 PDC Co-Chairs

 

Your PDC Registration Fee Includes:

  • Refreshment breaks
  • Hard-copy workbook of course materials (no electronic copies provided)
  • Lunch (ONLY for those taking Morning & Afternoon courses)

PDCs under SESSIONS
during IMAPS 2017 Online Registration

PDC Cancellation policy: IMAPS reserves the right to cancel a course if the number of attendees is not sufficient.
You can transfer to a different course or we will refund you the corresponding amount.


Cost for Each PDC: $300 (on/before 9/8/2017); $400 (after 9/8/2017)
Register Online

 

Early Monday Morning (8:00 AM-10:00 AM) Courses
YOU MAY SELECT ONE OF THESE FOUR COURSES ONLY

Track A:
Intro to Microelectronics, Packaging
Track B:
Next Generation Packaging Challenges
Track C:
Baseline and Emerging Technologies
Track D:
Reliability

A1: Introduction to System in Package (SiP) – The Heterogeneous Integration Driver
Instructor: Mark Gerber, ASE US, Inc.

Course description:

This PDC course will introduce the package platform SiP (System-in-Package) and how some companies are diversifying from SOC (System-on-a-Chip) to leverage heterogeneous silicon integration and overall package miniaturization. A short market perspective will be reviewed as well as how industry segments are leveraging SiP and how the OEM market is evolving and creating system level ecosystems to enabling content revenue- a key area of IOT. SiP general process flow details will be covered as well as key process considerations for yield improvements. In addition, a brief overview of some of the tools that may be leveraged to help miniaturize module solutions and improve performance. As SiP has evolved, there has also been interest in Fan Out Wafer level technology and the potential integration of multiple active devices as well as discretes into this technology- a brief overview of this option and considerations will be discussed.

Biography:

Mark Gerber is the Director of Engineering & Technical Marketing at ASE-US Inc, specializing in Flip Chip and Advanced Interconnect package technologies. Mark joined ASE in Feb of 2015, and brings a diverse set of semiconductor experiences from Texas Instruments, Motorola/Freescale, and Dallas Semiconductor, including advanced interconnect & IC package development, as well as a history of new product introductions. Mark holds a bachelor’s degree in Mechanical Engineering from Texas A&M University, and has worked in the Semiconductor Industry for the last 20 years, has written +20 papers, and currently holds over 30 patents in the area of semiconductor packaging.

 

B1: Emerging Challenges in Semiconductor Packaging
Instructor: Raja Swaminathan, Intel Corp.

Course description:

The course will introduce role of packaging in the interconnect hierarchy and introduce packaging trends per industry. We will then deep dive into the key elements driving the definition of a package architecture (scaling challenges, high speed signaling, power delivery, thermo-mechanical integration as well as thermal challenges). The interactions between these elements towards enabling a successful package architecture for a given product will be reviewed.

The second half of the course will focus on the package, assembly, test and silicon integration and surface mount challenges towards enabling high volume manufacturing of the package architectures.

Who Should Attend?

The attendees are expected to have an in depth understanding of the fundamentals of packaging.

Biography:

Dr. Raja Swaminathan is an IEEE senior member and is a package architect at Intel for next generation server, client and SOC products. His expertise is on delivering integrated HVM friendly package architectures with optimized electrical, mechanical, thermal solutions. He is an ITRS author and iNEMI TWG chair on packaging and design. He has also served on IEEE micro-electronics and magnetics technical committees. He has 18 patents and 23 peer reviewed publications and holds a Ph.D in Materials Science and Engineering from Carnegie Mellon University.

C1: 2.5D IC Integration and TSV-less Interposers
Instructor: John Lau, ASM Pacific Technology

Course description:

TAn interposer (2.5D IC integration) is just a piece of dummy silicon (a part of the package substrate) without devices but with TSVs (through-silicon vias) and RDLs (redistribution layers). Because TSVs involve many semiconductor processes, e.g., DRIE, PECVD, PVD, ECD, CMP, and Cu revealing, TSV technology is very expensive for a package substrate. In order to lower the cost, enhance the electrical performance, and reduce the package profile, the TSV should be eliminated from the interposer, i.e., a TSV-less interposer.

In this PDC, some TSV-less interposers proposed in the past three years such as those developed by Xilinx/SPIL, Amkor, ASE, Mediatek, Intel, ITRI, Shinko, Cisco, Sony, and Samsung will be presented and discussed. The materials and process of TSV and 2.5D IC integration will be briefly mentioned first. The future trends of 2.5D IC integration will also be presented.

Who Should Attend?

If you (students, engineers, and managers) are involved with any aspect of the microelectronics industry, you should attend this course. It is equally suited for R&D professionals and scientists. All the materials are based on the papers and books published in the past 3 years.

Biography:

With more than 38 years of R&D and manufacturing experience in semiconductor packaging, John Lau has published more than 450 peer-reviewed papers, 30 issued and pending patents, and 18 textbooks on, e.g., Advanced MEMS Packaging (McGraw-Hill Book Company, 2010), Reliability of RoHS compliant 2D and 3D IC Interconnects (McGraw-Hill Book Company, 2011), TSV for 3D Integration, (McGraw-Hill Book Company, 2013), and 3D IC Integration and Packaging (McGraw-Hill Book Company, 2016).

D1: Choosing Solders for the New Era: Low Cost High Reliability Solder Alloys
Instructor: Ning-Cheng Lee, Indium Corporation

Course description:

While the electronic industry is advancing rapidly toward miniaturization, two more important drivers actually dictate whether the manufacturers could stay in the game or not - Low Cost, and High Reliability. The former is the ticket to get into the game, while the latter is the ticket to stay in the game. These two drivers exemplified their vital role most astonishingly in solder materials. This course covers the roles of solder composition on cost, and on reliability. After reviewing the role of Ag in both cost and reliability, the solder materials are reviewed from the lowest cost, zero-Ag solders to composition with higher and higher Ag content. Among all of the alloy options present on the market, including the most recent development, the representative alloys are introduced with more details, including materials properties, soldering performance, some of the known failure modes, and the primary merit of these alloys.

Who Should Attend?

Technology directors, technology managers, product managers, design engineers, process engineers, reliability engineers, material scientists, process technicians, anyone who wants to know what are the solder alloys available, and what are the pros and cons about all of the options on solder alloys should take this course.

Biography:

Ning-Cheng Lee is Vice President of Technology of Indium Corporation. He has been with Indium since 1986. Prior to joining Indium, he was with Morton Chemical and SCM. He has more than 30 years of experience in the development of fluxes and solder pastes for SMT industries. He received his PhD in polymer science from University of Akron in 1981, and BS in chemistry from National Taiwan University in 1973. He is author of “Reflow Soldering Processes and Troubleshooting: SMT, BGA, CSP, and Flip Chip Technologies”, and co-author of “Electronics Manufacturing with Lead-Free, Halogen-Free, and Conductive-Adhesive Materials”. He was honored as 2002 Member of Distinction from SMTA, 2003 Lead Free Co-Operation Award from Soldertec, 2006 Exceptional Technical Achievement Award and 2007 Distinguished Lecturer from CPMT, 2009 Distinguished Author from SMTA, 2010 Electronics Manufacturing Technology Award from CPMT, 2015 IEEE Senior Member, 2015 Founder’s Award from SMTA, and 2017 IEEE Fellow.

10:00 AM-10:30 AM
Coffee / Networking

Open to all PDC participants

 

Late Monday Morning (10:30 AM - 12:30 PM) Courses
YOU MAY SELECT ONE OF THESE FOUR COURSES ONLY

Track A:
Intro to Microelectronics, Packaging
Track B:
Next Generation Packaging Challenges
Track C:
Baseline and Emerging Technologies
Track D:
Reliability

A2: Wire Bonding Fundamentals
Instructor: Lee Levine, Process Solutions Consulting

Course description:

With more than 15 trillion wire bonds produced annually and volume still growing the reliability and productivity of wire bonding makes it one of the most reliable processes in manufacturing. But that does not mean that rigorous attention to details can be ignored. New products must be fully qualified and periodic testing of the weld intermetallic is an important part of assuring high quality bonds. Process changes, materials changes and tool changes must all be tested and reliability confirmed. Long-term aging studies using accelerated high temperature storage, thermal cycling and temperature/humidity tests are not only initial qualification requirements but should be a part of any review when materials s and encapsulation changes are required.

Mechanical testing of wire bonds is normally performed on every lot, at shift changes and if a tool is changed. Pull testing of wire bonds is the most common test performed. The mechanics of the pull test is based on simple resolution of forces but using the pull test to control the process must be done with an understanding of the mechanics. It is not unusual for companies to miss poor bonds because they fail to understand the mechanics and use the pull test incorrectly. A macro-scale model will be used to model the pull test and explain where problems can be missed during standard test procedures.

The shear test provides a good measure of the strength of the intermetallic weld. The use of the shear test for optimizing wire bond process parameters is common. Designed experiments provide good understanding of the effect of process parameters on the bond quality. Shear strength requirements, testing and interferences will be discussed.

Ultrasonic welding is an aggressive process that allows large scale deformation of the ball and wire at much lower temperature and force than would be possible without ultrasonic assistance. However, some wire bond failure modes such as cratering and cracking of interlayer dielectrics in multi-layer die are very sensitive to ultrasonic energy. A discussion of these failures, how to detect them and the effect of bond parameters on these failures will be discussed.

Who Should Attend?

Wire bond process engineers, technicians, quality control engineers and managers should take this course.

Biography:

Lee Levine is a consultant for Process Solutions Consulting, Inc. where he provides process engineering consultation, SEM/EDS analysis, and wire bond training. Lee’s previous experience includes 20 years as Principal and Staff Metallurgical Process Engineer at Kulicke & Soffa and Distinguished Member of the Technical Staff at Agere Systems. He has been awarded 4 patents, published more than 70 technical papers, and has won both the John A. Wagnon Technical Achievement award and the Daniel C. Hughes award from the International Microelectronics and Packaging Society (IMAPs). Major innovations include copper ball bonding, loop shapes for thin, small outline packages (TSOP and TSSOP, and CSPs) and introduction of DOE and statistical techniques for understanding semiconductor assembly processes. He is an IMAPs Fellow and a senior, life member of IEEE. Lee is a graduate of Lehigh University, Bethlehem, Pa where he earned a degree in Metallurgy and Materials Engineering.

B2: Introduction to Package-on-Package (PoP) Design, Assembly and Quality: Focus on New Trends and Applications for Advanced Packaging
Instructor: Fernando Roa, Amkor Technology, Inc

Course description:

This course will provide an introduction to design, packaging and reliability fundamentals required in the definition, process development and production of package on package applications. As such, we'll delve into critical design rules to observe during the layout of the substrates required for such packaging as well as best known methods for assembly including rules of thumb for selection of materials. The course will also include typical process flows used based on final EMS implementation of these PoPs and quality metrics to use.

Who Should Attend?

Design, product and process engineers, managers, procurement organizations from OEM and IDM organizations operating the baseband, AP and advanced packaging of components; also, CM and EMS representatives which are receiving PoPs for integration on boards.

Biography:

Fernando Roa, PhD, Sr Director, Advanced Products, Amkor Technology, Inc. Fernando has been with Amkor since 2007, working in product management, technology development and strategic initiatives roles. In his current position, he’s responsible for Copper pillar flip chip packaging platform development and commercialization in addition to other advanced packaging initiatives. Fernando received his PhD in Chemical Engineering from University of Colorado in 2003. After completing his PhD, Fernando joined Intel Corporation where he worked in assembly process development and Platform Integration. Fernando holds 10 US Patents and has published over 25 papers in different publications.

C2: Workmanship Standards for Advanced Hybrids, ICs and Microwave Assemblies
Instructor: Thomas Green, TJ Green Associates LLC

Course description:

Next generation Hybrids, Microcircuits, IMAs (Integrated Microwave Assemblies) and chip and wire PCBs all require a visual inspection step just prior to encapsulation or hermetic seal. This is a critical process step that requires a high degree of skill and understanding of what to look for and reject as part of the inspection process. This tutorial defines the inspection criteria based on traditional Mil-Std-883 requirements in conjunction with industry accepted best commercial practices. High Mag inspection of ICs, MMICs and diodes along with Low mag die attach, wirebond and assembly related defects are reviewed in detail. Each student receives a 30 day access to the Workmanship Standards eBook: Hybrids, Microcircuits and RF/MMIC modules, an online illustrated guide depicting photos of common workmanship defects as seen during production and each defect slide is tied to a particular page and referenced requirement in MIL-STD-883/750. The students are exposed to a variety of defects and how the defects relate to the materials and process flow. Students learn what to look for as part of visual inspection and how to interpret and apply the very latest mil spec visual inspection criteria.

Who Should Attend?

The course is intended for quality and process engineers, inspectors, lead operators and others responsible for inspection of the hardware prior to the final package sealing process. Designers and quality managers would also benefit from understanding the critical importance of visual inspection and its impact on reliability of the finished product.

Biography:

Mr. Thomas Green is the principle at TJ Green Associates LLC (www.tjgreenllc.com), a veteran owned small business focused on training and consulting for military, space and medical microelectronic devices. He teaches a variety of microelectronics packaging courses around the globe and in plant at major corporations and consults for a variety companies in the military/industrial and medical device industries. He has thirty five years of experience in microelectronics working at positions in industry, academia and government. Tom has demonstrated expertise in die attach, wirebond, visual inspection, failure analysis, hermetic seal and leak testing processes. Tom is an active IMAPS member and Society Fellow. He has a B.S. in Materials Engineering from Lehigh University and a Masters from the University of Utah.

 

D2: A Methodology for Understanding the Reliability of Electronic Packaging
Instructor: Greg Caswell, DfR Solutions

Course description:

Reliability is the measure of a product’s ability to perform its specified function at the customer’s facility, in their use environment, over the desired lifetime. Designing for reliability is the method for ensuring the reliability of a product or system during the design stage, before a physical prototype is produced is paramount.

This course will describe the failure modes associated with die attach, wire bonding, and solder joints using a Physics of Failure approach. Strain energy equations will be discussed for the potential failure modes to help the student facilitate prediction of failure.

The course will then discuss the relatively new failure mechanism, that of silicon wearout. As gate geometries have continued to shrink, the susceptibility of the device to fail has increased, to a point where some of the newer 14 nm feature devices will not hold up well in high reliability applications. We will look at the intrinsic mechanisms of ICs to understand their susceptibility based on environments.

The next module of the course will demonstrate a methodology for using Physics of Failure to assess the failure modes associated with the populated circuit board, looking at issues such as thermos-mechanical fatigue, thermal effects, and the more probabilistic mechanisms like CAF and IMC fracture from mechanical shock. The approach will show how to predict failure at this level.

Finally, the course will introduce a method for assessing the microvias in a package to identify the highest stressor points and provide an approach for obviation. Lastly, a short presentation on Electrostatic Discharge (ESD) and how to mitigate it will be presented.

Who Should Attend?

Engineers and managers who have a vested interest in producing high reliability devices and systems that meet their customer’s expectations.

Biography:

Greg Caswell, a Senior Member of the Technical Staff for DfR Solutions, is an industry recognized expert in the fields of SMT, advanced packaging, printed board fabrication, circuit card assembly, and bonding solutions using nanotechnology. He has been well-regarded as a leader in the electronics contract manufacturing and component packaging industries for the past 45 years. Prior to joining DfR Greg was the Vice President of Engineering at Reactive Nanotechnology (RNT), where he led application development for the RNT Nanofoil® and ensured a successful transition of product technology to Indium Corporation. His previous appointments include Vice President of Business Development for Newport Enterprises, Director of Engineering for VirTex Assembly Services, and Technical Director at Silicon Hills Design. He has presented over 250 papers at conferences all over the world and has taught courses at IMAPS, SMTA and IPC events. He helped design the 1st pick and place system used exclusively for SMT in 1978, edited and co-authored the 1st book on SMT in 1984 for ISHM and built the 1st SMT electronics launched into space. B.A., Management (St. Edwards University). B.S., Electrical Engineering (Rutgers University)

12:30 PM-1:00 PM
Lunch

Open ONLY to PDC participants taking morning AND afternoon courses

 

Early Monday Afternoon (1:00 PM - 3:00 PM) Courses
YOU MAY SELECT ONE OF THESE FOUR COURSES ONLY

Track A:
Intro to Microelectronics, Packaging
Track B:
Next Generation Packaging Challenges
Track C:
Baseline and Emerging Technologies
Track D:
Reliability

A3: Fundamentals of 3D and 2.5D Packaging Integration
Instructor: Urmi Ray, STATS ChipPAC

Course description:

This course will cover the fundamental technology aspects of 3D and 2.5D integration including summaries of key benefits, process flow, test, cost and reliability challenges. The goal of this course is to provide a review of technology status to date and spend additional time on case studies of market and product adoption.

Course outline:

• Why 3D:
o New architectural & partitioning capabilities
o Package Density and Form Factor
o Improved Performance

• Types of 3D:
o Via first
o Via middle
o Via last

• Types of 2.5D
o Si/glass interposer
o Fan Out
o Laminate substrate/embedding

• Manufacturing process flow for Via-middle

• Manufacturing process flow for Si interposer

• Challenges for market adoption
o Cost
o Reliability
o Supply Chain
o Others

• Case Studies of successful recent product adoption
o HBM memory with TSV
o Graphics processor integration using 2.5D

• Roadmap

Biography:

Urmi Ray is currently Senior Director at STATS ChipPAC focusing on advanced system in package (SIP) technologies. Prior to joining STATS, Urmi served as a Principal Engineer in Qualcomm where she had been the technology and program lead in several forward looking programs in 3D and 2.5D and system integration, with particular focus on low cost packaging for mobile industry. She joined Qualcomm in 2006, after spending 10+ years at Lucent Technologies Bell Laboratories in NJ working on advanced materials and reliability for a diverse set of product portfolios, including consumer products to high reliability telecommunications projects. She is currently active in many aspects of advanced packaging technology area. She has a PhD from Columbia University (New York City).

 

B3: Introduction to Fan Out Packaging
Instructor: John Hunt, ASE US, Inc.

Course description:

With the fierce competition between mobile device manufacturers, along with the rise of the Internet of Things, the Electronics industry has been driven by the need for a continual reduction in the thickness and volume of semiconductor packaging. Fan Out technology has evolved as an alternative package to answer this need for miniaturization of electronics.

We will review how the integration of wafer level processing technologies, substrate evolution and Flip Chip packaging structures have come together into what is being called Fan Out Packaging. These packages are for both low density and high density, Mobile and server applications. They have higher levels of integration and sophistication than has ever been possible in the past. A basic overview of the concept of Fan Out packaging, a history of its evolution, and market trends will be included in this course.

Biography:

John Hunt is Senior Director for Engineering, Technical Promotion, at ASE (US) Inc., and provides technical support for the Introduction, Engineering, Marketing, and Business Development activities for Advanced Wafer Level and Fan out Packaging Technologies at ASE.

John has more than 45 years of experience in various areas of manufacturing, assembly and testing of electronic components and systems, with emphasis on the development of new technologies and processes, with a B.S. from Rutgers and an M.S. from University of Central Florida.

C3: Photonic Interconnects - an Overview
Instructor: Kannan Raj, Oracle

Course description:

This short course will provide an overview of optical interconnects in telecom and datacom applications. The following topics will be covered in detail:

- Anatomy of a link
- Progression toward optical links
- Short reach & long reach links
- Building blocks of transceivers
- electronics, lasers, detectors
- Optical transceiver types and fiber connectivity
- Assembly of optical transceivers
- Industry standards and form factors
- Electrical, thermal, Mechanical and optical requirements
- Dense integration requirements
- Embedded optics in systems platforms
- Dense integration requirement for next generation links
- Silicon photonics
- Interposers, multi-chip photonic modules & assemblies
- Connectors, packaging & assembly constraints
- Reliability requirements

Who Should Attend?

Professionals with background in the semiconductor, optical, packaging and manufacturing industry.

Biography:

Kannan Raj is a Senior Director at Oracle in the Networking Group. He came into Oracle via Oracle’s acquisition of Sun Microsystems. Prior to Oracle & Sun Microsystems, he served as the Datacom product line manager at Zarlink Semiconductor and Primarion, growing groups in Phoenix and Sweden from startup phase. He also played significant roles at Intel and has managed several industry-university collaborative programs. He has a Ph.D. from George Mason University, MSEE from Virginia Tech, ME from Indian Institute of Science, Bangalore. He holds 60 issued patents and has co-authored over 125 conference and journal publications. He was elected Sr. Member IEEE in 2004.

D3: Package/Board Level Integrity & Solder Joint Reliability
Instructor: Jennie Hwang, H-Technologies Group

Course description:

With the goal to produce reliable products while achieving high yield production, this course provides a holistic overview of product reliability and of critical “players”of the package/board level integrity and solder joint reliability, including the roles of materials, processes and testing/service conditions, as well as the crucial principles behind the product reliability. Recent developments related to lead-free package and board assembly, lead-free solder materials, PCB laminates and surface finishes in relation to manufacturability and reliability will be outlined.

The likely solder joint failure modes (interfacial, near-interfacial, bulk, inter-phase, intra-phase, voids-induced, surface-crack and others) will be illustrated. Solder joint reliability fundamentals including fatigue and creep damage mechanisms via ductile, brittle, ductile-brittle fracture will be outlined. To withstand harsh environments, the strengthening metallurgy to further increase fatigue resistance and creep resistance and the power of metallurgy and its ability to anticipate the relative performance will be illustrated by examining the comparative performance in relation to metallurgical phases and microstructures.

Parameters for a working life-prediction model will be highlighted. A relative reliability ranking among commercially viable solder systems, the scientific, engineering and manufacturing reasons behind the ranking, and newer solder alloy developments and their impact on product performance and reliability will be summarized.

The course also examines the role of intermetallics at-interface and in-bulk (contributing from packages and board surface finish coating) in relation to product reliability. The difference between SnPb and Pb-free solder joint in terms of intermetallic compounds, which in turn is attributed to production-floor phenomena and the actual field failure, will be discussed. From practical perspectives, tin whisker with emphasis on risk mitigation through understanding the factors that affect tin whisker growth and its preventive and remedial solutions will be outlined. Practical tin whisker criteria for reliability implications in the lead-free environment and the relative effectiveness and the order of priority in mitigating measures will be ranked.

The course emphasizes on practical, working knowledge, yet balanced and substantiated by science. Attendees are encouraged to bring their own selected systems for deliberation.

Who Should Attend?

The course provides a higher level of working knowledge in package/board level integrity and solder joint reliability to all who are concerned about or interested in understanding product integrity and solder joint reliability, including designers, researchers, managers, quality, manufacturing and reliability professionals; also designed for those who desire the scientific basis behind the practical know-how.

Biography:

Dr. Hwang, a long-standing leader in lead-free implementation and SMT manufacturing , brings deep knowledge to this course through both hands-on and advisory experiences. She has provided solutions to many challenging problems, ranging from production yield to field failure diagnosis to reliability issues in both commercial and military applications. She has 475+ publications to her credit, including the sole authorship of several internationally-used textbooks, and is a speaker in innumerable international and national events. Her formal education includes Harvard Business School Executive Program and four academic degrees (Ph.D. M.S., M.S., B.S.) in Metallurgical Engineering and Materials Science, Physical Chemistry, Organic Chemistry and liquid Crystal Science. She has held various senior executive positions with Lockheed Martin Corp., SCM Corp, Sherwin Williams Co, and IEM Corp. She is also an invited distinguished adj. Professor of Engineering School of Case Western Reserve University, and serves on the University’s Board of Trustees.

3:00 PM-3:30 PM
Coffee / Networking

Open to all PDC participants

 

Late Monday Afternoon (3:30 PM - 5:30 PM) Courses
YOU MAY SELECT ONE OF THESE FOUR COURSES ONLY

Track A:
Intro to Microelectronics, Packaging
Track B:
Next Generation Packaging Challenges
Track C:
Baseline and Emerging Technologies
Track D:
Reliability

A4: Introduction to Solder Flip Chip with an Emphasis on Cu Pillar
Instructor: Mark Gerber, ASE US, Inc.

Course description:

This PDC course will provide a historical overview and background on Solder Flip Chip technology with an emphasis on Copper Pillar Flip Chip as well as short market perspective. Interconnect structure, process flows, materials and package integration process methods for evolving Flip Chip applications will be discussed in detail. The understanding The trade-offs between The traditional Solder based Flip Chip and Copper Pillar is key in determining The silicon device layout and The type of design rules that can be leveraged for new products. as part of This course, The Solder Bump and Copper Pillar Bump structure formation will be reviewed as well as multiple Cu Pillar Flip Chip attachment methods such as Mass Reflow and Thermo-Compression Non-Conductive Paste (TCNCP) bonding. Reliability aspects such as IMC formations and ways to address will also be covered as a key consideration for Interconnect decisions. Current market trends have led to additional questions regarding the longevity of Flip Chip versus other competing technologies such as Fan Out Wafer Level Packaging (FOWLP) will also be reviewed as well as a comparison between technologies.

Biography:

Mark Gerber is the Director of Engineering & Technical Marketing at ASE-US Inc, specializing in Flip Chip and Advanced Interconnect package technologies. Mark joined ASE in Feb of 2015, and brings a diverse set of semiconductor experiences from Texas Instruments, Motorola/Freescale, and Dallas Semiconductor, including advanced interconnect & IC package development, as well as a history of new product introductions. Mark holds a bachelor’s degree in Mechanical Engineering from Texas A&M University, and has worked in the Semiconductor Industry for the last 20 years, has written +20 papers, and currently holds over 30 patents in the area of semiconductor packaging.

B4: Fan Out Packaging Evolution & Complexity
Instructor: John Hunt, ASE US, Inc.

Course description:

Mobile electronics has driven the need for ever increasing density and performance in electronics packaging. This has only accelerated with the advent of advanced smart phones and the burgeoning Internet of Things. This evolution has led to a need for higher levels of component density and functionality than has been traditionally available using standard packaging, resulting in a wide variety of new packaging options.

We will review how the first relatively simple, low I/O Fan Out packages are evolving into more and more complex structures that provide the capability to replace many current packaging strategies. These packages can be both low density and high density, Mobile and server applications. They can have higher levels of integration and sophistication than was used to produce the early Fan Out packages. These options include Wafer Level Fan Out, Panel Level Fan Out, and Chip Last Fan Out packaging. All of these can combine low cost materials and varied process flows to create both simple devices, and more complex System in Package and Package on Package applications. This course will provide an overview of the drivers, technology, advantages and disadvantages of various structural and processing options, as well as a view of potential future trends for Fan Out Packaging.

Biography:

John Hunt is Senior Director for Engineering, Technical Promotion, at ASE (US) Inc., and provides technical support for the Introduction, Engineering, Marketing, and Business Development activities for Advanced Wafer Level and Fan out Packaging Technologies at ASE.

John has more than 45 years of experience in various areas of manufacturing, assembly and testing of electronic components and systems, with emphasis on the development of new technologies and processes, with a B.S. from Rutgers and an M.S. from University of Central Florida.

C4: Heterogeneous Packaging of Wide Band Gap Powerelectronics – Moving from IPM to SiP
Instructor: Doug Hopkins, North Carolina State University

Course description:

With the recent availability of essentially chip-scale packaged GaN and higher voltage SiC Wide Band Gap (WBG) power devices, the onus is on packaging engineers to expand their understanding of the unprecedented high-speed and high-power-density characteristics of these devices and the impact on package design. The trend for the past several years has been to place the WBG devices in packages designed for Si, but only to provide end users with familiar outlines. However, the WBG devices have matured sufficiently to show that only high levels of package integration will allow the claimed higher WBG performances.

The course topics are:

- Understanding critical operating characteristics of WBG power devices from the perspective needed by the packaging engineer. (This is critical due to the unprecedented di/dt’s, dv/dt’s, and dT/dt’s from WBG device switching.)
- A review of gate driver circuits that operate at >10X frequency of the power stages, and are integrated into devices and integrated through packaging
- Introduction to planar power GaN and on-chip functional integration
- Developing design rules for packaging engineers and showing trends to multidisciplinary power electronics packaging, and heterogeneous integration of power components and devices, including quilt packaging. (incl. Yole studies, and comparisons of traditional packaging approaches)
- Step-by-step presentation of multiphysics modeling for design, and use of Q3D for power circuit parameter extraction and design refinement
- Use of case studies to support the above topic

Biography:

Dr. Douglas Hopkins is Professor and Director of the Laboratory for "Packaging Research in Electronic Energy Systems" as part of the NSF-funded FREEDM Systems Center at North Carolina State University in Raleigh, NC. He was formerly with SUNY Buffalo as Director of the "Electronic Power and Energy Research Lab". He received his Ph.D. from Virginia Tech, worked for GE's and Carrier's R&D Centers, and held visiting positions at several national labs. He is an IEEE senior member and IMAPS fellow. He is a founding member of IMAPS Subcommittee on Power Packaging, now chairs the technical subcommittee on Electronic Energy Packaging in IEEE-CPMT and member of the IEEE-PELS technical committee on Emerging Technologies. He has authored over 100 journal and conference publications, received three ISHM/IMAPS awards.

D4: Copper and Gold Ball Bonding: Intermetallics, Aging and Bond Reliability
Instructor: Lee Levine, Process Solutions Consulting

Course description:

Wire Bonding is a welding process that is the dominant chip interconnection method. More than 15 trillion wires are bonded annually. In the past gold wire was predominant but in 2015 copper and palladium coated copper wire captured more than 51% of the total market. Copper provides benefits in cost, improved conductivity, stiffness and reliability. However, it is significantly harder than gold and achieving a robust, reliable process is a challenge. Wire bonding high-volume lead-frame often experiences defect rates below 10ppm, this presents a significant barrier to entry for any process competitor but copper is meeting the challenge.

Like any welding process wire bonding forms an intermetallic nugget that is an alloy of the wires being bonded. The quality and reliability of the intermetallic weld is the key to long-term reliability. After initial bond formation the intermetallic undergoes dynamic transformations from one intermetallic alloy to another as diffusion and growth proceeds and the bond ages. Each intermetallic phase has different properties and lattice structures. Phase transformations can result in significant lattice strain and fail precipitously. Wire alloy chemistry plays an important role in intermetallic alloy transformations and can play an important role in achieving a successful high-reliable process.

Ultrasonic energy provides the driving force input for bond formation. Ultrasonics changes the material properties of the ball and substrate allowing easy internal flow and deformation joining the mixture into an alloy. The effect of ultrasonic energy on bond formation will be discussed.

Biography:

Lee Levine is a consultant for Process Solutions Consulting, Inc. where he provides process engineering consultation, SEM/EDS analysis, and wire bond training. Lee’s previous experience includes 20 years as Principal and Staff Metallurgical Process Engineer at Kulicke & Soffa and Distinguished Member of the Technical Staff at Agere Systems. He has been awarded 4 patents, published more than 70 technical papers, and has won both the John A. Wagnon Technical Achievement award and the Daniel C. Hughes award from the International Microelectronics and Packaging Society (IMAPs). Major innovations include copper ball bonding, loop shapes for thin, small outline packages (TSOP and TSSOP, and CSPs) and introduction of DOE and statistical techniques for understanding semiconductor assembly processes. He is an IMAPs Fellow and a senior, life member of IEEE. Lee is a graduate of Lehigh University, Bethlehem, Pa where he earned a degree in Metallurgy and Materials Engineering.

5:30 PM-7:30 PM
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