Micross

IMAPS 2017 - Raleigh

IMAPS 2017 - Raleigh
IMAPS 50th Anniversary Symposium
www.imaps2017.org | www.imaps50th.org

Conference:
October 10-12, 2017
Exhibition:
October 10-11, 2017
Professional Development Courses:
October 9, 2017
General Chair:
Dan Krueger
Honeywell FM&T
Technical Chair:
Mary Cristina Ruales Ortega
University of Missouri, Kansas City
Technical Co-Chair:
Andre Rouzaud
CEA Leti

 
    PREMIER PROGRAM SPONSOR:
 
 
Premier Program Sponsor - Heraeus Materials Technology

 

    PREMIER TECHNOLOGY SPONSOR :

   PREMIER TECHNOLOGY SPONSOR:
   PREMIER TECHNOLOGY SPONSOR:
Premier Tech Sponsor - NGK NTK
Premier Tech Sponsor - EMD Performance Materials
Premier Tech Sponsor - Amkor Technology

TECHNICAL PROGRAM
(Keynote Presentations, Sessions, Posters, and more!)

Register Online | Call for History

   

 

Monday, October 9, 2017

IMAPS Microelectronics Foundation David C. Virissimo Memorial Golf Classic | 9:00 AM - "Scramble"

Professional Development Courses (PDCs) - 8:00 AM - 5:30 PM)

Microelectronics/Packaging Industry Tour - 10:30 AM - 2:00 PM - TBD
Micross Advanced Interconnect Technology (AIT), a specialized division of Micross
Micross is the leading one-source, one-solution provider of bare die & wafers, wafer bumping & advanced interconnect technologies, custom packaging & assembly, component modification services, electrical & environmental testing and Hi-Rel products to manufacturers and users of semiconductor devices. In business for 35+ years, our comprehensive array of high-reliability capabilities serves the global defense, space, medical, industrial and fabless semiconductor markets. Micross possesses the sourcing, packaging, assembly, test and logistics expertise needed to support an application throughout its entire program cycle.

Micross Advanced Interconnect Technology (AIT), a specialized division of Micross, is home to one of the premier wafer bumping and wafer level packaging facilities in the U.S., with 20+ years of experience developing and providing leading edge interconnect and 3D integration technologies (TSV, Si interposers, 3D IC) to customers around the world. AIT has the unique ability to support early stage development needs as well as low-to-mid volume production for more mature applications and platform technologies. Our ITAR-registered facility supports wafer sizes up to 200mm with established and proven processes and the flexibility to tailor unique solutions for your most demanding interconnect requirements. The facility can also support the processing of non-standard materials, as well as the fabrication of novel device structures (e.g. MEMS and 3D microstructures).

Arrival and sign-in 11:10 -11:25
Introduction/Welcome to AIT (20-30 min) 11:30-12
Lunch 12-1 (IMAPS will bring in catered lunch for group)
Tour 1 (10-12 people): 11:55 ~12:40 Tour 2 (10-12 people): 12:00~12:45 Tour 3 (10-12 people): 12:05~12:50
Coffee in lobby 12:30-1:00
Depart 1:00

 

Monday, October 9: 2-hour formats, by theme/track
8:00 AM-10:00 AM | 10:30 AM - 12:30 PM | 1:00 PM - 3:00 PM | 3:30 PM - 5:30 PM
*Attendees can take ONE PDC during each timeslot*

  Track A:
Intro to Microelectronics Packaging
Track B:
Next Generation Packaging Challenges
Track C:
Baseline and Emerging Technologies
Track D:
Reliability
8:00 AM-10:00 AM A1: Introduction to System in Package (SiP) - The Heterogeneous Integration Driver - Mark Gerber, ASE Group

B1: Emerging Challenges in Semiconductor Packaging - Raja Swaminathan, Intel

C1: 2.5D IC Integration and TSV-less Interposers - John Lau, ASM Pacific Technology D1: Choosing Solders for the New Era: Low cost High Reliability Solder Alloy - Ning-Cheng Lee, Indium Corporation
10:00 AM-10:30 AM
Coffee / Networking
Open to all PDC participants
10:30 AM - 12:30 PM A2: Wire bonding Fundamentals - Lee Levine, Process Solutions Consulting

(*NEW TIME: 10:30 AM - 12:30 PM*)
B2: Introduction to Package-on-Package (PoP) Design, Assembly and Quality: Focus on New Trends and Applications for Advanced Packaging - Fernando Roa, Amkor Technology, Inc C2: Workmanship Standards for Advanced Hybrids, ICs and Microwave Assemblies - Tom Green, TJ Green Associates D2: A Methodology for Understanding the Reliability of Electronic Packaging - Greg Caswell, DfR Solutions
12:30 PM-1:00 PM
Lunch
Open ONLY to PDC participants taking morning AND afternoon courses
1:00 PM-3:00 PM A3: Fundamentals of 3D and 2.5D Packaging Integration - Urmi Ray, STATS ChipPAC

(*NEW TIME: 1pm-3pm*)
B3: Introduction to Fan Out Packaging - John Hunt, ASE Group C3: Photonic Interconnects - an Overview - Kannan Raj, Oracle D3: Package/Board Level Integrity & Solder Joint Reliability - Jennie Hwang, H-Technologies Group
3:00 PM-3:30 PM
Coffee / Networking
Open to all PDC participants
3:30 PM-5:30 PM A4: Introduction to Copper Pillar Flip Chip Interconnect - Mark Gerber, ASE US Inc. B4: Fan Out Packaging Evolution & Complexity - John Hunt, ASE Group C4: Heterogeneous Packaging of Wide Band Gap Power Electronics: Moving from IPM to SiP - Doug Hopkins, North Carolina State University D4: Copper and Gold Ball Bonding: Intermetallics, Aging and Bond Reliability - Lee Levine, Process Solutions Consulting
5:30 PM-7:30 PM
Welcome Reception
Open to all IMAPS 2017 participants

 

Cost for Each PDC: $300 (on/before 9/8/2017); $400 (after 9/8/2017)
Register Online

Welcome Reception | 5:30 PM - 7:30 PM

Welcome Reception Sponsored by:

 
   Premier Program Sponsor:
 
 
Heraeus Materials Technology - Premier Sponsor, Gold
 

 

 

DIVERSITY ROUNDTABLE AND NETWORKING DISCUSSIONS
Join IMAPS leaders for a networking discussion on diversity in IMAPS and the microelectronics industry on Monday, October 9th from 7pm-8pm just following the welcome reception. The event will feature up to six concurrent roundtable discussions with participants who will rotate between different tables and discussion leaders. Discussion leaders will inspire conversation about overcoming diversity barriers, experiences using your strengths in a diverse workforce, how to identify and collaborate with a mentor, and more. All IMAPS attendees are invited to participate!


 

TUESDAY, OCTOBER 10, 2017

7:00 AM - 6:00 PM: Registration Open
12:00 PM - 5:00 PM: Exhibit Hall Open

IMAPS 2017 Opening & Plenary Session:

8:00 am - 8:15 am: Welcome to IMAPS 50th & the Annual Meeting
IMAPS President, Susan Trulli

8:15 am - 8:30 am: It's Time for IMAPS 2017
General Chair, Dan Krueger

Keynote Session sponsored by:
Keynote Sponsor: SAMTEC

 

8:30 am - 9:15 am: Keynote Presentation 1

Ahmer Syed

Packaging Challenges for the Next Generation of Mobile Devices
Changes in board technology, denser packaging due to board size limitations, and phone thickness trends pose number of technical challenges for designing IC packages for mobile applications. While thin packages are required to meet height constraints requirements, room temperature co-planarity and high temperature warpage become critical issues for packages with thin substrate, die, and mold cap. Similarly, while PoP provides numerous benefits from size and business standpoint; heat dissipation and thickness constraints requires continuous development of new packaging technologies. In addition, changes in board behavior is affecting the overall stress equation, making Chip-Package-Board interaction very important when deciding chip and package level interconnections. This presentation will highlight some of these challenges and identify technology innovations in areas such as System in Package (SIP) to mitigating these factors while simplifying supply chain and improving overall time to market.

Ahmer Syed, Senior Director, Package Engineering, Qualcomm Technologies, Inc.
Ahmer Syed is Sr Director of Package Engineering at Qualcomm and leads package process and technology development. Ahmer is a packaging industry veteran with more than 25 years of experience in advance package development, package and board level reliability, and simulations. Prior to Qualcomm, Ahmer held various technical and management positions at Amkor for 16 years. Ahmer received his Master’s degree in Mechanical Engineering from the University of Maryland and has author/co-authored more than 50 technical papers and articles.

9:15 am - 10:00 am: Keynote Presentation 2

Keynote - Subu Iyer

Packaging without the Package - A More Holistic Moore's Law
Silicon features have scaled by over 1500X for over six decades, and with the adoption of innovative materials delivered better power-performance, density and till recently, cost per function, almost every generation. This has spawned a vibrant system-on-chip (SoC) approach, where progressively more function has been integrated on a single die. The integration of multiple dies on packages and boards has, however, scaled only modestly by a factor of three to five times. However, as SoCs have become bigger and more complex, the Non-Recurring Engineering (NRE) Charge and time to market have both ballooned out of control leading to ever increasing market consolidation. We need to address this problem through novel methods of system Integration. With the well-documented slowing down of scaling and the advent of the Internet of Things, there is a focus on heterogeneous integration and system-level scaling. Packaging itself is undergoing a transformation that focuses on overall system performance through integration rather than on packaging individual components. We propose ways in which this transformation can evolve to provide a significant value at the system level while providing a significantly lower barrier to entry compared with a chip-based SoC approach that is currently used. More importantly it will allow us to re-architect systems in a very significant way. This transformation is already under way with 3-D stacking of dies, Wafer level fan-out processing, and will evolve to make heterogeneous integration the backbone of a new SoC methodology, extending to integrate entire Systems on Wafers (SoWs). We will describe the technology we use and the results to-date. This has implications in redefining the memory hierarchy in conventional systems and in neuromorphic systems.  We extend these concepts to flexible and biocompatible electronics.

Subramanian S. Iyer (Subu) is Distinguished Chancellor's Professor and holds the Charles P. Reames Endowed Chair in the Electrical Engineering Department at the University of California at Los Angeles and Director of the Center for Heterogeneous Integration and Performance Scaling (CHIPS )
Subramanian S. Iyer (Subu) is Distinguished Chancellor's Professor and holds the Charles P. Reames Endowed Chair in the Electrical Engineering Department at the University of California at Los Angeles and Director of the Center for Heterogeneous Integration and Performance Scaling (CHIPS ) Prior to Joining UCLA in 2015, he was an IBM Fellow and managed the system integration effort at IBM. His interests lie in developing new integration paradigms that will allow for radically new system architectures.

 

10:00 AM - 10:30 AM: Coffee Break in Foyer

Coffee Break Sponsor:
Break Sponsor: Geib Refining

10:30 am - 11:15 am: Keynote Presentation 3

Keynote - Benjamin Leever

Electronics Outside the Box: Building a Manufacturing Ecosystem for Flexible Hybrid Electronics
As the electronics in our daily lives proliferate, they continue to be largely limited to rigid form factors with bulky packaging dictated by traditional electronics manufacturing processes and fragile components. Yet for applications ranging from wireless, low-profile medical devices to smart food labels to aircraft with embedded stress sensors, there's a need for high-performance electronics that conform to the shape of our bodies, vehicles, and consumer goods. Flexible Hybrid Electronics (FHE), which combine additive manufacturing processes with flexible silicon will enable these capabilities. To move these concepts from the lab to the manufacturing floor in the United States, the Department of Defense established NextFlex, America's Flexible Hybrid Electronics Manufacturing Institute in 2015. Based in San Jose, CA, NextFlex is a $170M public-private partnership that is building a domestic FHE manufacturing ecosystem by developing manufacturing processes and tools with its member companies and universities, standing up an FHE manufacturing pilot line in Silicon Valley, and establishing education and workforce development programs to train tomorrow's workforce. This presentation will focus on the FHE opportunity, the NextFlex FHE manufacturing roadmaps, and NextFlex projects in areas such as device integration & packaging, modeling & design tools, and printed flexible components.

Benjamin Leever, Senior Materials Engineer, Air Force Research Laboratory (AFRL) Soft Matter Materials Branch
Benjamin Leever is currently a Senior Materials Engineer in the Air Force Research Laboratory (AFRL) Soft Matter Materials Branch. His primary roles are Advanced Development Lead and Government Chief Technology Officer of NextFlex, a $170M public-private partnership established to create a domestic manufacturing ecosystem in flexible hybrid electronics. In support of AFRL's investments in Soft Matter Materials, Dr. Leever determines technical strategy, manages AFRL contracts, and establishes industrial, academic, and governmental collaborations. He also leads the directorate's Energy Integrated Product Team and respresents the directorate on numerous domestic and international power & energy and additive manufacturing working groups.

Prior to assuming his current duties, Dr. Leever led a research team focused on the development and modeling of multifunctional materials for structural power applications. Dr. Leever began his career at AFRL in the Manufacturing Technology Division, where he managed programs related to electro-optics systems. He earned a B.S. in Chemical Engineering from the University of Cincinnati and a Ph.D. in Materials Science & Engineering from Northwestern University.


11:15 am - 12:00 pm: Keynote Presentation 4

Tim Olson

Transforming Electronic Interconnect
From nanometers at the transistor level to 100’s of microns at the ball grid array (BGA) connections, electronic interconnect of semiconductors spans orders of magnitude as it forms the central nervous system of today’s advanced electronic products. Tectonic shifts are currently underway within the industries providing electronic interconnect. Traditional supply chain boundaries produce back end of line (BEOL) structures within wafer foundries ranging from 10’s of nanometers to 10’s of microns. First-level interconnect, or packaging, the classical purvey of semiconductor assembly and test services (SATS) providers operates in 10’s to 100’s of microns. Second-level interconnect, or board level assembly, historically rests with electronic manufacturing systems (EMS) providers measuring their work in 100’s of microns and above. The transformation underway in electronic interconnect will redefine historical supply chain boundaries as it blurs the lines between foundries, SATS and EMS providers. At the heart of the transformation is ‘fan-out’ technology moving from initial capacities in wafer form to an emerging format of large panels. Breaking through capital cost, reliability and yield concerns with novel solutions will open the door for widespread industry growth of fan-out.

Tim Olson, Founder & CTO, Deca Technologies
In 2009, Tim Olson founded Deca Technologies with a vision of transforming electronic interconnect. Tim served as President and CEO until transitioning in 2013 into his current role of CTO. Tim has been board member since establishment of the company.

Prior to Deca, Tim was senior vice president of Amkor Technology where he led global research and development introducing key innovations to the market including PoP TMV* (Package on Package Through Mold Via) technology, FusionQuad* and the industry’s first high volume fine pitch Cu pillar flip chip on laminate technology. Tim also led creation of the micro-EMS model at Amkor establishing direct technology & business relationships with leading electronic systems OEMs providing SiP (System in Package) modules and other advanced electronic interconnect solutions. *Note: TMV and FusionQuad are trademarks of Amkor

Previously, Tim established the Systems Integration Division of Fico (now Besi) where the “Strip Testing” breakthrough was commercialized into the semiconductor industry for leadframe and laminate based devices. After several years, Tim led the sale of the Systems Integration division to Micro Component Technology (MCT) where he became Executive Vice President of products and operations. During this time, MCT established itself as the world leader in strip test technology as well as related automation software and systems.

Tim served for several years as the Chairman of the SEMI International Test, Assembly & Packaging committee while working in the semiconductor equipment industry with Fico and MCT. Tim began his semiconductor career at Motorola in manufacturing engineering. Within a few years, Tim led the creation, implementation and operation of PRISM, a highly automated and integrated semiconductor factory serving leading automotive and cellular handset OEMs. While at PRISM, Tim pioneered the concept of individual device traceability through utilization of 2D codes within manufacturing by adopting the technology used by NASA for traceability in spacecraft. The concept of strip testing was also pioneered at PRISM with the industry’s first high volume production implementation. PRISM was awarded CEO model factory in 1995 for the multiple innovations realized.

Tim graduated magna cum laude from the University of North Dakota with bachelor’s degrees in mechanical engineering and engineering management. Tim holds over two dozen patents relating to wafer processing, packaging, equipment, software, process and design.

 

12:00 pm - 12:15 pm:
What's next for IMAPS? Urmi Ray, IMAPS VP of Technology
This Week's Technical Program - Mary Cristina Ruales Ortega, IMAPS 2017 Technical Chair

 

IMAPS 2017 EXHIBITS OPEN: 12:00 pm - 5:00 pm

12:15 pm - 2:30 pm: Lunch in Exhibit Hall

Exhibit Lunch Sponsor:

Lunch Sponsor: MRSI

12:00 pm - 2:30 pm:
Student-Industry Networking Lunch Tuesday, October 10th

In the Exhibit Hall (Look for a special dining section within the hall just for this event!)
Students should plan to enjoy this informal networking hour with IMAPS and industry leaders over lunch in the exhibit hall. Ask questions to learn more about work opportunities, navigating the hiring process, tips for making the best impression and more. Any topic goes!


Student Programs Sponsored by:

Honeywell - Student Programs Sponsor

Applied Materials - Keynote Sponsor

 

 

 

TUESDAY AFTERNOON PROGRAM

 

CHIP PACKAGE INTERACTION (CPI)

HIGH PERFORMANCE, RELIABILITY, & SECURITY

ADVANCED PACKAGING & ENABLING TECHNOLOGIES

ADVANCED PACKAGING & SYSTEM INTEGRATION

ADVANCED MATERIALS & PROCESSES

 

Session TP1
Materials and Reliability I

Session Chairs: Tengfei Jiang, UCF; Venky Sundaram, Georgia Tech

In the first of the two sessions addressing this topic, we will address the many ways, new materials used in the assembly process can impact both "outgoing" and in-use reliability of the packages due to Chip-Package Interactions. Variables such as dielectric materials, CTE and modulus and qualification methodology will be discussed.

Session TP2
Packaging to meet the RF Roadmap - 2.4 to 26 to 60 GHz

Session Chairs: Mumtaz Bora, Peregrine Semi; Ambrose Wolf, Honeywell

The new generation of high speed wireless technologies coming to market require packaging technologies that can meet the material, process and assembly needs of the high frequency applications. Packaging roadmaps need to be flexible and scalable to meet the demands of distance, speed, low interference risk, security and cost targets of the emerging markets and technologies.

Session TP3
3D Technologies: Materials, Processes, and Applications

Session Chairs: Mark Gerber, ASE; Chet Palesko, SavanSys

This session will dive into the materials, processes and applications that enable various 3D technologies. Specific technologies including laser TSV, Passive Integration in RDL, Micro bumping, 3D printing, high thermal conductivity and other advanced processes will be reviewed. In support of this key focus area, this session will also review how the 2.5D/3D Ecosystem Is evolving and may influence the product solutions moving forward.

Session TP4
Wafer Level Packaging & Panel Level Packaging

Session Chairs: Habib Hichri, SUSS;
Michael Gallagher, DOW

This session will address the multi-functional purpose system packaging method and process. The leading edge technologies, such as ultrafine routing and through glass Via fabrication, and flexible hybrid electronics technologies are introduced for WLP and PLP. Also modeling method and applications for EMI shielding will be presented.

Session TP5
Novel Materials/Processes I

Session Chairs: Charles Woychik, i3 Electronics; Richard Stephenson, Silicon Valley Materials Technology Corp, Inc.; Rita Mohanty, DfR Solutions

This session focuses on novel materials and processes for use in thermal and electrical device manufacture and sensing.

2:30 pm - 2:55 pm

031
High Reliability and High Throughput Ball Bumping Process Solution - Solder Joint Encapsulant Adhesives
Wusheng Yin, YINCAE Advanced Materials, LLC. (Mary Liu)

122
Packaging and Miniaturization of a 2-18 GHz UWB Radar for Measurements of Snow and Ice: Initial Results
F. Rodriguez-Morales, University of Kansas (C. Leuschen, J. Davisson, S. Garrison, & A. Wolf)

027
Development of Stacking Process for 3D TSV Structure using Laser
Kwang-Seong Choi, ETRI (Wagno Alves Braganca Junior, Keon-Soo Jang, Seok Hwan Moon, Hyun-Cheol Bae, Yong-Sung Eom)

060
3D IPD on Thru Glass Via Substrate Using Panel Manufacturing Technology
Takamasa Takano, Dai Nippon Printing (Hobie Yun, Qualcomm Technologies, Inc.)

001
Enhanced In-Plane Heat Transport in Embedded Mini Heat Pipes PCB
Jonathan Silvano de Sousa, AT&S Austria Technologie & Systemtechnik Aktiengesellschaft (P. L. Fulmek, M. Unger, P. Haumer, J. Nicolics)

3:00 pm - 3:25 pm

024
Power Cycle Reliability of SiC Devices with Metal-sinter die-attach and Thermostable Molding
Katsuaki Suganuma, Osaka University (Shijo Nagao, Hiroshi Fujita, Akio Shimoyama, Shinya Seki, Hao Zhang)

044
Ultra-Compact Four-Channel 5-18 GHz Switched Filter Bank Utilizing PolyStrata® Microfabrication and 3D Packaging
Chris Hermanson, Nuvotronics Inc. (Rob Reid, Will Stacy)

061
Inductors using 2.5D Silicon Interposer with Thick RDL and TSV-last Technologies
Gabriel Pares, CEA-Leti (J.P. Michel, E. Deschazeaux, V.Pernin, A. Giry, P. Ferris)

064
The IC in the Flexible Hybrid Electronics Technology: Flexibility and Bend Testing
Val Marinov, Uniqarta, Inc.

034
Alternative Deposition Solution for Cost Reduction of TSV Integration
Julien Vitiello, KOBUS (Fabien Piallat)

3:30 pm - 3:55 pm

051
Temperature and Process Dependent Material Characterization and Multiscale Stress Analysis for Performance and Reliability Management under Chip Package Interaction
Xiaopeng Xu, Synopsys, Inc. (Aditya Karmarkar, Karim El Sayed)

079
RF Test Article to Assess the Impact of Non-Hexavalent Chromium-Based Conversion Coatings on Electrical Assemblies
Joshua Petko, Northrop Grumman (Philip Lovell, Jeremy Clifton, Paul Cohen, Karl Schoch, Jr.)

096
3D Printed Waveguides for the Design of Microwave and Millimeter Passive Circuits
Premjeet Chahal, Michigan State University  (Mohd Ifwat, Mohd Ghazali,
Vincens Gjokaj, Amanpreet Kaur)

081
Shielding Effectiveness Simulation of SMT EMI Gaskets
Christopher Kerwien, W.L. Gore & Associates, Inc. (Charlotte Blair)

003
Highly Reliable Cu Wiring Layer of 1/1 µm Line/Space Using Newly Designed Insulation Barrier Film
Kazuyuki Mitsukura, Hitachi Chemical


Coffee Break in Exhibit Hall: 3:55 pm - 4:55pm


5:00 pm - 5:25 pm

157
Development of Liquid Compression Molding Material (LCM) for Low Warpage 
Tsuyoshi Kamimura, Namics Corp. (Satomi Kawamoto, Daisuke Hashimoto, Yuto Shigeno, Haruyuki Yoshii, Namics Corp.; Hirokazu Noma, Tomohiro Ookubo, Hisato Takahashi, Hidetoshi Inoue, Hitachi Chemical Co.) 

106
Fabrication of X-band Oscillator on LCP Substrate Using Aerosol Printing
Christopher Oakley, Michigan State University (John Albrecht, John Papapolymerou, Premjeet Chahal)

021
Building an EcoSystem for User-friendly Design of Advanced System in Package (SiP) Solutions
Herb Reiter, eda 2 asic Consulting, Inc

011
Fine Line Routing and Micro Via Patterning in ABF Enabled by Excimer Laser Ablation
Habib Hichri, SUSS MicroTec Photonic Systems Inc. (Lee Seongkuk; Markus Arendt; Shohei Fujishima; Shigeo Nakamura)

080
Experimental Assessment of Microwave Loss Caused by Non-Hexavalent Chromium-Based Conversion Coatings
Joshua Petko, Northrop Grumman (Philip Lovell, Jeremy Clifton, Paul Cohen, Karl Schoch, Jr.)

5:30 pm - 5:55 pm

2017imaps126
Fine Resolution Photosensitive Polyimide Dry Film with High Resistance to Electromigration Under HAST Condition
Masao Tomikawa, Toray Industries Inc. (Kazuyuki Matsumura, Yoshiko Tatsuta, Yu Shoji, Ryoji Okuda)

144
Thin Film Capacitor Applications in RF/Microwave Circuits
William Kuhn, Kansas State University  (J. Ambrose Wolf)

025
In line Advanced Process Control Solution for the Fabrication of Micro-bumps
Dario Alliata, UnitySC (Stephane Godny, Cleonisse Serrecchia, Tristan Combier, Astrid Sippel, Philippe Gastaldo)

130
Ultra-fine Line Multi-Redistribution Layers with 10µm Pitch Micro-Vias for Wafer Level and Panel Level Packaging realized by an innovative Excimer Laser Dual Damascene Process 
Robert Gernhardt, Fraunhofer IZM (Friedrich Müller; Markus Woehrmann; Habib Hichri; Karin Hauck; Michael Toepper; Markus Arendt; Klaus-Dieter Lang)

094
Characterization of Ultra-Thin Epoxy-Resin Based Dielectric Substrate for Flexible Power Electronics Applications
Xin Zhao, North Carolina State University (K. Jagannadham, Douglas Hopkins, North Carolina State University; Wuttichai Reainthippayasakul, Michael Lanagan, Pennsylvania State University)

6:00 pm - 6:25 pm

019
Effect of Substrate Finish on Microstructure Evolution of Sintered Ag Joints to Attach Power Devices with Paste of Ag Nanoparticles during Isothermal Ageing
Yun Wang, China Aero-Polytechnology Establishment (Jianfeng Li, Pearl Agyakwa, Christopher Mark Johnson, Shuguang Li)

156
Integration and Miniaturization of a Ka-Band Stepped Frequency Radar for UAV Applications
Jay McDaniel, University of Oklahoma (Mark Yeary, Hjalti Sigmarsson, University of Oklahoma;
Sean Garrison, Kyle Byers, Ambrose Wolf, Honeywell FM&T)

052
Printed Wiring for High-Power Electric Devices by Using Ag-sinter Paste
Seungjun Noh, Osaka University (Chuantong Chen, Toshiyuki Ishina, Shijo Nagao, Katsuaki Suganuma)

108
Separating Temporary Carrier from Large Thin Panel with Air Jetting
Hao Tang, Micro Materials Inc. (My Nguyen, Ming Yin)

043
A Frequency Swept Low-Cost Capacitive Fringing Field PCB Sensor
Robert Dean, Auburn University

 

 


 

WEDNESDAY, OCTOBER 11, 2017

7:00 AM - 6:00 PM: Registration Open
11:00 AM - 5:30 PM: Exhibit Hall Open

WEDNESDAY MORNING PROGRAM

 

CHIP PACKAGE INTERACTION (CPI)

HIGH PERFORMANCE, RELIABILITY, & SECURITY

ADVANCED PACKAGING & ENABLING TECHNOLOGIES

ADVANCED PACKAGING & SYSTEM INTEGRATION

ADVANCED MATERIALS & PROCESSES

 

Session WA1
System Integration

Session Chairs: John Hunt, ASE; Steffen Kroehnert, Amkor Technology (formerly Nanium)

Presentations in this session will discuss evaluations done for system integration related Chip-Package Interaction topics. Packaging technologies addressed are Flip-Chip BGA, Multi-Chip modules, Fan-Out WLP, and System-in-Package, including such for automotive market, and advanced chip technology nodes.

Session WA2
Miniaturization of Bio-devices

Session Chairs: Kedar Shah, Verily Life Sciences (Google); Caroline Bjune, Draper Labs; Tim LeClair, Cerapax

Smaller form factors are critical for Injectables, Insertables, and Implantables.

Session WA3
Emerging Packaging Technologies

Session Chairs: Doug Link, Starkey Hearing; Matt Apanius, SMART Microsystems

In this age of mobile device proliferation, the Internet of Things, and electric vehicles, the drive to further microelectronic miniaturization has spawned emerging tehnological advances in height reduction, extended temperature range, and package flexibility. This session is focused on the emerging and innovative technologies in the advanced packaging world. The topics include the challenges and solutions for Wide-Bandgap (WBG) power packaging, plasma -based dicing technology in the BEOL process flows, new bonding process technique - polymer elastic bump (PEB) bonding for flexible SiF (System in Foil) package, as well as Precision Ultra-Thinning in emerging technology applications.

Session WA4
Heterogeneous & Complex System Packaging

Session Chairs: Woong-Sun Lee, SK Hynix; Robert Dean, Auburn University

This session is focused on the multi-functional purpose system packaging method and process. The leading edge technologies, such as WLP, eWLB etc, are introduced for heterogeneous and complex system packaging. Also modeling method and applications of SiP are presented.

Session WA5
Polymers in Microelectronics

Session Chairs: Andy Mackie, Indium; Frank Eberle, Northrop Grumman

Incorporation of polymers in microelectronics continues to grow and evolve. This session focuses on the development of polymers for the use as encapsulates, dielectrics, conductors, and resistors for use in microelectronic devices.

8:00 am - 8:25 am

105
Advanced Packaging for Automotive
Pascal Oberndorff, NXP Semiconductors (Peter Drummen, Leo van Gemert, Peter Offeringa)

155
Silicon Microfluidics: An Enabling Technology for Life Sciences Application 
Bivragh Majeed, IMEC (Lei Zhang, Giuseppe Fiorentino, Deniz Sabuncuoglu, IMEC; Edward Walsby, ORBOTECH) 

102
Plasma Dicing Process-Flows for Advanced Packaging Fabrications
Frank Wei, DISCO Corporation (Tomotaka Tabuchi, Hideyuki Sando)

030
Investigation of Wafer Level Packaging Schemes for 3D RF Interposer Multi-chip Module
Bart Vereecke, IMEC (Philippe Soussan, IMEC; Jian Zhu, NEDI)

072
Encapsulation of Microelectronic Assemblies for use in Harsh Environments
Hannah Varner, Charles Stark Draper Laboratory (Juliette Mahaffey, Thomas Marinis, Christopher DiBiasio)

8:30 am - 8:55 am

066
A Generic Strategy to Assess and Mitigate Chip Package Interaction Risk Factors
for Semiconductor Devices with Ultra-low k Dielectric Materials in Back End of Line
Frank Kuechenmeister, GLOBALFOUNDRIES Inc. (Dirk Breuer, Holm Geisler, Christian Klewer, Bjoern Boehme, Kashi Vishwanath Machani, Michael Hecker, Christian Goetze, Jae Kyu Cho, Himani Kamineni, Jens Paul, Michael Thiele)

082
Self-powered, Impact-monitoring System using a Flexible Hybrid Electronic Mouthpiece
Jeremy Ward, Air Force Research Lab (Kenji Aono, Casey Pirnstill, Shantanu Chakrabartty, Michael Durstock)

092
Investigation of Package Effects on the Edge Termination E-Field for HV WBG Power Semiconductors
Haotao Ke, North Carolina State University (Yifan Jiang, Adam Morgan, Douglas Hopkins)

039
Innovative Integration Solutions for SiP Packages Using Fan-Out Wafer Level eWLB Technology
Vinayak Pandey, STATS ChipPAC (Jacinta Lim)

053
Ablative Laser Patterning of Polymeric Dielectric Materials
Cristina Matos, Brewer Science, Inc. (Deborah Blumenshine, Lisa Kirchner, Rama Puligadda; Brewer Science, Inc.; Habib Hichri, Seongkuk Lee, Markus Arendt, Suss MicroTec Group)

9:00 am - 9:25 am

035
Co-Simulation Based Multi-Chip Module Design Flow and Wi-Fi Module Example with Integrated BAW and LNA
Jeffrey Dekosky, Qorvo (Deepukumar Nair, Larry Carastro, Scott Knapp)

137
Reliability Analysis of a Wearable Sensor Patch (WSP) to Monitor ECG Signals 
Varun Soman, Binghamton University (Mark Poliks, James Turner, Mark Schadt, Michael Shay, Frank Egitto)

004
Technology Transfer for MEMS and Advanced Packaging: Precision Surface Preparation Innovatively Applied to Emerging Technologies
Bob Roberts, Axus Technology

136
Lighting System Packaging for Smart Underwater Reefs for Sensing, Communications, and Robotics 
David Fries, IHMC (Tim Hutcheson, Connor Tate, Noam Josef, Kirsten Ayres, Sean Hickey)

009
Adhesion Characteristics of Epoxy Molding Compound and Copper Leadframe Interface: Impact of Environmental Reliability Stresses
Nishant Lakhera, NXP Semiconductors (Sandeep Shantaram)


Coffee Break in Foyer: 9:30 am - 10:00 am

Coffee Break Sponsor:
Break Sponsor: Pac Tech


 

10:00 am - 10:25 am

097
Direct Measurement of Silicon Strain in a Fine Pitch Flip Chip BGA Package
Glenn Rinne, Amkor Technology (Nathan Whitchurch, Wei Lin)

104
Practical Application and Analysis of Lead-Free Solder on Chip-On-Flip-Chip SiP for Hearing Aids
Doug Link, Starkey Laboratories (Youngtak Lee)

020
Thermally Stable Ag-Ag Joints Bonded by Ultrasound-assisted Stress Migration Bonding
Katsuaki Suganuma, Osaka University (Hao Zhang, Norio Asatani, Koji Kimoto, Aishi Suetake, Toru Sugahara, Shijo Nagao, Toshiyuki Ishina)

134
Using SPICE to Model Nonlinearities Resulting from Heterogeneous Integration of Complex Systems 
Aubrey Nathan Beal, Oakridge Institute for Science and Education (Robert Dean)

099
Characterization of Silicone Gel for High Temperature Encapsulation in High Voltage WBG Power Modules
Adam Morgan, North Carolina State University (Xin Zhao, Jason Rouse, Douglas Hopkins)

10:30 am - 10:55 am

077
Non-Destructive Testing for System-in-Package Integrity Analysis
Karl-Friedrich Becker, Fraunhofer IZM (Mathias Minkus, Volker Bader, Steve Voges, Gerd Jungmann, Hubert Wieser, Tanja Braun, Martin Schneider-Ramelow, Klaus-Dieter Lang)

143
Microfabrication and Packaging Process for a Single-Chip Position, Navigation, and Timing System 
Vamsy Chodavarapu, University of Dayton (JunJun Huan, George Xereas, Charles Allan)

023
Comparative Evaluation and Analysis of Gate Driver Impact on Switching Speed of SiC MOSFET in a SiC MOSFET-Gate Driver Co-packaged Power Module
Liqi Zhang, FREEDM Systems Center, North Carolina State University  (Alex Huang, Pengkun Liu, Suxuan Guo)

133
Atmospheric Probe for Real Time Weather Monitoring 
J. Craig Prather, Auburn University (Michael Bolt, Haley Harrell, Tyler Horton, John Manobianco, Mark Adams )

128
Reliability of Coated and Alloyed Copper/Silver Ball Bonds
Murali Sarangapani, Heraeus Electronics (Bayaras Abito Danila, Zhang Xi)

11:00 am - 11:25 am

###
CPI JEDEC Publication and Industry Summary
Urmi Ray, STATS ChipPAC

163
An Implantable, Designed-for-Human-Use Peripheral Nerve Stimulation and Recording System for Advanced Prosthetics
Caroline Bjune, Draper (John Lachapelle, Carlos Segura, John Burns IV, Jake Hellman, Alejandro Miranda, Elliot Greenwald, Andrew Czarnecki, Matthew Muresan, Brian Nugent, Daniel Guyon, Wes Uy, Tirunelveli Sriram, Jesse Wheeler, Alexander Kindle, Philip Parks, Draper; Edward Keefer, Nerves, Inc.; Jonathan Cheng, University of Texas-Southwestern; Steve Tillery, Arizona State University)

162
Inkjet and 3D Printing Technology for Fundamental Millimeter-Wave Wireless Packaging
Bijan Tehrani, Georgia Institute of Technology (Ryan Bahr, Manos Tentzeris)

150
Environmentally Isolating Packaging for MEMS Inertial Sensors 
Michael Kranz, EngeniusMicro (Michael Whitley, Carl Rudd, Robert Dean, George Flowers) 

 

11:30 am - 1:00 pm: Lunch in Exhibit Hall

 


WEDNESDAY AFTERNOON PROGRAM

 

CHIP PACKAGE INTERACTION (CPI)

HIGH PERFORMANCE, RELIABILITY, & SECURITY

ADVANCED PACKAGING & ENABLING TECHNOLOGIES

ADVANCED PACKAGING & SYSTEM INTEGRATION

ADVANCED MATERIALS & PROCESSES

 

Session WP1
Advanced CMOS Nodes

Session Chairs: Urmi Ray, STATS ChipPAC; Rich Rice, ASE

This session will address the complex interplay, both electrical and mechanical, especially related to transistor performances and BEOL integration issues arising out of Chip-Package Interactions.

Session WP2
Power, Batteries and Energy Harvesting

Session Chairs: Ben Leever, USAF; Lyndon Larson, DOW

Development and demonstration of electronics devices and systems for energy harvesting, management, and storage.

Session WP3
LTCC and Ceramic Technologies

Session Chairs: Howard Imhof, Silicon Valley Mats.; Martin Schneider-Ramelow, Fraunhofer IZM

Demonstrated performance driven packaging opportunities in 5G, aerospace, medical, high power, embedded passive elements, and integrated liquid cooling with state of the art LTCC technology.

Session WP4
Wire Bonding

Session Chairs: Lee Levine, Process Solutions Consulting; Tom Green, TJ Green Associates

Wire Bonding remains a major chip and package interconnection method. New materials, process and machine innovations contribute to the continued successful implementation of this process.

Session WP5
Novel Materials/Processes II

Session Chairs: Aric Shorey, Corning;
Carol Putman, Daikin America

During this session of novel materials and processes, we will be focusing on new developments to overcome adhesion challenges between hybrid micro layers in electronic components to ensure reliability on thermal and electrical performance and expected life time. Innovative alternatives for processing on controlled metallization as well as to enhance adhesion on glass substrates will be presented as solutions to the manufacture of multilayer electrical components and their requirements to enhance reliability.

1:00 pm - 1:25 pm

048
Electrical Chip-Board Interaction (e-CBI) of Wafer Level Packaging Technology
Wei Zhao, Qualcomm Technologies (Mark Nakamoto, Karthikeyan Dhandapani, Brian Henderson, Ron Lindley, Riko Radojcic, Urmi Ray, Aurel Gunterus, Mark Schwarz, Ahmer Syed, Vidhya Ramachandran)

088
Optimizing the Segmented Thermoelectric Generator using Taguchi Method
Ravi Anant Kishore, Center for Energy Harvesting Materials and Systems (CEHMS), Virginia Tech (Shashank Priya)

147
The Relevance of Low Temperature Co-fired Ceramic Module Packaging in the 5G Market  
Ton Schless, SIBCO LLC (Frank Chen)

151
Wire Bonding Looping Solutions for High Density System-in-Package (SiP)
Basil Milton, Kulicke & Soffa (Odal Kwon, Cuong Huynh, Ivy Qin, Bob Chylak)

084
Using a Metal Oxide Adhesion Layer and Wet Chemical Cu Metallization for Fine Line Pattern Formation on Glass
Robin Taylor, Atotech Deutschland GmbH (Michael Merschky, Fabian Michalik, Martin Thoms, Diego Reinoso-Cocina, Stephan Hotz, Patrick Brooks)

1:30 pm - 1:55 pm

054
14nm Chip Package Interaction technology development
Lei Fu, Advanced Micro Devices (YS Low, Milind Bhagavat, Ivor Barber)

095
Multiphysics Performance Evaluation of Flexible Substrate Based 1.2kV SiC Half Bridge Intelligent Power Module with Stacked Dies
Xin Zhao, North Carolina State University (K. Jagannadham, Douglas Hopkins)

006
LTCC Based Highly Integrated SiPM Module With Integrated Liquid Cooling Channels for High Resolution Molecular Imaging
Rainer Dohle, Micro Systems Engineering GmbH, an MST company (Ilaria Sacco, Thomas Rittweg, Thomas Friedrich, Gerold Henning, Jörg Gossler, Peter Fischer)

135
High Temperature Storage Reliability of Bond Resistance of Palladium-Coated Copper Ball Bonds
Michael David Hook, University of Waterloo (Michael Mayer, Stevan Hunter)

085
Direct Copper Metallization on TGV (Thru-Glass-Via) for High Performance Glass Substrate
Shigeo Onitake, KoTo Electric Co.,Ltd. (Kotoku Inoue, Masatoshi Takayama)

2:00 pm - 2:25 pm

109
2.5D FPGA-HBM Integration Challenges
Jaspreet Gandhi, Xilinx (Boon Ang, Tom Lee, Henley Liu, Myongseob Kim, Ho Hyung Lee, Gamal Refai-Ahmed, Hong Shi, Suresh Ramalingam, Xilinx)

165
Morphological and Electrical Stability Studies of Pt/Yttria-Stabilized Zirconia Nanocomposite Thin Film Cathodes for Microfabricated Solid Oxide Fuel Cells 
Michael Rottmayer, US Air Force Research Laboratory (Raj Singh, Oklahoma State University; Hong Huang, Wright State University)

029
Direct Sapphire to Ceramic Bonding for CMOS Image Sensor Packaging Using Room Temperature Bonding Technology
Liam Murphy, ESTEC, European Space Agency (Heidi Lundén, Primoceler Inc; Antti Määttänen)

071
Multidimensional Ultrasonic Copper Bonding - New Challenges for Tool Design
Paul Eichwald, University of Paderborn (Simon Althoff, Reinhard Schemmel, Walter Sextro,Andreas Unger, Michael Broekelmann, Matthias Hunstig)

078
A Novel Microvia Process for Below 10 Um Diameter
Abdelghani Renbi, Luleå University of Technology (Jerker Delsing)

2:30 pm - 2:55 pm

110
Next Generation Xeon Server Package Architecture
Raja Swaminathan, Intel (Ram Viswanath, Sriram Srinivasan, Arun Chandrasekhar, Michael Carroll, Krishna Bharath, Wei-Lun Jen, Zhichao Zhang, Rajen Sidhu)

046
Design of 240°C Low Voltage Power Supply
Saurabh Kulkarni, Baker Hughes, Inc. a GE Company

068
Thick Film Materials for High Power Hybrid Circuits on Aluminum Nitride and Silicon Nitride
Matt Sgriccia, Heraeus Electronics (Ryan Persons, Frank Sandoval)

129
Aluminium Wedge-Wedge Bonding Using Capillary and Ball Bonder
Murali Sarangapani, Heraeus Electronics (Ei Phyu Phyu Theint, Hamdan Faizul Fitri, Tan Kean Tiong, Zhang Xi)

076
Glass Solutions for Packaging and IoT
Aric Shorey, Corning Incorporated (Rachel Lu)

3:00 pm - 3:25 pm

017
High Density Tall Cu Pillars for 3D Packaging
Keith Best, Rudolph Technologies (Tom Swarbrick, Kevin Martin)

161
Direct Aerosol Printing of Lithium-ion Batteries
Heng Pan, Missouri University of Science and Technology

142
Precision Embedded Passive Circuit Elements on Low Temperature Co-Fired Ceramic (LTCC) Substrate for Aerospace Electronics 
Devin Smarra, University of Dayton (Guru Subramanyam, Vamsy  Chodavarapu, Sivaram Gogineni, Kenneth Semega, Alireza Behbahani)

166
A Critical Review of Wirebond Visual Inspection Criteria
Thomas Green, TJ Green Associates

2017imaps145
Optimization of Chemistry for a Vapour Phase Process to Deflux No Clean Lead Free Materials on PCBs 
Jonathan Cetier, Inventec Performance Chemicals (Rodrigo Aguilar, Emmanuelle Guene, Aurelie Ducoulombier, Anne Marie Laugt)


3:30 pm - 5:30 pm: Happy Hour in Exhibits



5:30 pm - 7:00 pm: 

International Panel Session & Wine Reception on:
GLOBAL PERSPECTIVES ON PACKAGING REQUIREMENTS
AND TRENDS TOWARDS 2025

MODERATORS:
Jan Vardaman, TechSearch International;
Gabriel Pares, CEA-Leti

Over the next several years new the industry will new trends in electronis including ADAS for automotive, the adoption of 5G systems, and the incorporation of machine learning/artificial intelligence in a variety of segments. How will these trends change the packaging and assembly requirements? What packages might see stronger growth driven by these trends? Are there any key material or equipment requirements? Our international panel will address the trends and help focus on future packaging and assembly requirements.

Panel Format: Panelists will respond to audience questions during this 90-minute session. Q&A moderated by Jan and Gabriel.

PANELISTS:

Asia:
• Yasumitsu Orii, NAGASE Group
• Ton Schless, SIBCO (Packaging Toward 2025 & LTCC Packaging in 5G)

Europe: • Steffen Kroehnert, Amkor Technology (formerly Nanium)
• Eric Bridot, SAFRAN (Strategic Mgr for Packaging)

USA: • David Jandzinski, QORVO
• TBD


Wine Reception Sponsored by NAGASE

Wine Reception Sponsor: Nagase Co. Ltd.
Wine Reception Sponsor: Nagase America Corp.



 


 

THURSDAY, OCTOBER 12, 2017

7:00 AM - 3:00 PM: Registration Open
NO EXHIBITS - Exhibitor Move-Out

 

THURSDAY MORNING PROGRAM

 

CHIP PACKAGE INTERACTION (CPI)

HIGH PERFORMANCE, RELIABILITY, & SECURITY

ADVANCED PACKAGING & ENABLING TECHNOLOGIES

ADVANCED PACKAGING & SYSTEM INTEGRATION

ADVANCED MATERIALS & PROCESSES

 

Session THA1
Process Integration

Session Chairs: Horst Clauberg, Kulicke & Soffa; Rajiv Roy, FormFactor

This session will focus on the process and equipment advances that enable advanced applications and the material sets associated with high performance device packaging and impact Chip-Package Interaction.

Session THA2
Extreme Environment Device Reliability

Session Chairs: Otto Fanini, Baker Hughes, Inc. a GE Company; Bill Marsh, Northrop Grumman

This session is focused on microelectronic device durability and reliability under extreme environmental conditions including high temperature, pressure, vibration, and shock, and exposed to various forms of chemical attack and contamination. Devices and interconnects include sensors, substrates, integrated circuits, wire bonds and other microelectronic assembly and packaging media.

Session THA3
Fanout Wafer Level Packaging

Session Chairs: Rajiv Dunne, Qualcomm; Shamima Afroz, Northrop Grumman

Fan-out Wafer-Level Package (FOWLP) development continues at a rapid pace and is enabling thin/low-cost products and heterogenous SIP integration. This session covers the development of unit processes, metrology and innovative FOWLP packaging process flows/solutions for applications in mobile, IoT and Bio-MEMS areas to name a few.

Session THA4
Antennas & Advanced RF System-Integration

Session Chairs: Ivan Ndip, Fraunhofer IZM; Manos Tenzeris, Georgia Tech PRC; Jim Will, Honeywell, FM&T

The focus of this session is on modeling, design and measurement of antennas and RF components for RF system integration.

Session THA5
Reliability

Session Chairs: Tim Jensen, Indium Corp.; Greg Caswell, DfR Solutions

As electronics technology advances, devices are generating more power in smaller form factors that are going into broader ranges of applications. This session focuses on several facets of electronics reliability.

8:00 am - 8:25 am

120
Automotive IC Probing Challenges - FFI MEMS Technology Meets and Exceeds Expectation
Ashish Bhardwaj, FormFactor Inc. (Amy Leong)

036
Design for Reliability Analysis of Vibration Induced Failures due to Equipment Assembly Bending Load and Vibration Responses
Josh Liew, Baker Hughes, Inc. a GE Company (Otto Fanini)

057
Characterization of Fan-out Wafer Level Packaging
John Lau, ASM Technology Hong Kong Ltd (Ming Li, Tian Dewen, Li Qingqian, Eric Kuah, Nelson Fan)

116
Antenna Systems for Simultaneous Transmit and Receive (STAR) Applications
Dejan Filipovic, University of Colorado Boulder (Mohamed Elmansouri, Ehab Etellisi)

123
Strength Assessment for Direct-sintered Al2O3-to-Cu Joints based on Damage Modeling
Adrian Lis, Osaka University (Koji Asama, Tomoki Matsuda, Tomokazu Sano, Akio Hirose)

8:30 am - 8:55 am

005
Journey to Success for New Analog Technologies for Texas Instruments
Basab Chatterjee, Texas Instruments (Mario Magaña, Rey Javier)

152
Operation of Silicon Carbide Integrated Circuits under High Temperature and Pressure 
A. Matt Francis, Ozark Integrated Circuits, Inc. (Matthew Barlow, Jim Holmes)

055
Effective Inspection Methods for Advanced Packaging Technologies
Julia Brueckner, Quantum Analytics (Michael Schwander, Sentronics Metrology GmbH)

103
Compact Beam Steering Antennas for Wearable Wireless Applications
Mohammod Ali, University of South Carolina (Nowrin Chamok, Md. Nazmul Alam)

063
Design of Experiments Approach to Evaluating the Reliability of System-in-Package Assemblies
Timothy Dittman, Northrop Grumman Mission Systems (Alex Bailey, David Ebner)

9:00 am - 9:25 am

010
Die Placement Error Management for Fan Out Applications Using Projection Lithography
Habib Hichri, SUSS MicroTec Photonic Systems Inc

086
High Temperature Reliability of Wire Bonds on Thick Film
Zhenzhen Shen, Baker Hughes, Inc. a GE Company (Aleksey Reiderman)

083
Technology Development towards a Foldable Fan-out Wafer Level Package
Tanja Braun, Fraunhofer IZM (K.-F. Becker, R. Kahle, L. Georgi, S. Raatz, S. Voges, M. Minkus, J. Bauer, M. Schneider-Ramelow, K.-D. Lang)

041
E-Band 4-Bit Phase Shifter using SP4T Flip Chip Switches
Jia-Chi Samuel Chieh, Space and Naval Warfare Systems Center Pacific (Jason Rowland, Anh-Vu Nguyen, Satish Sharma)

164
Reliability; What’s Right For Your Business?
Rita Mohanty, DfR Solutions

Coffee Break in Foyer: 9:25 am - 9:45 am

9:45 am - 10:10 am

014
Reduction of Thermal Stress - Part I: Passivation Thickness Optimization of Standard Bump Design
Raj Sekar Sethu, X-FAB Semiconductor Foundries AG (Salil Hari Kulkarni, How Ung Ha, Kok Heng Soon)

121
Durability and Reliability of Electro-Mechanical Relays for Oil and Gas
Saeed Rafie, Baker Hughes, Inc. a GE Company

118
Implementation of Wafer Level Packaging KOZ using SU-8 as Dielectric for the Merging of WL Fan Out to Microfluidic and Bio-Medical Applications
Steffen Kroehnert, Amkor Technology (formerly Nanium) (Andre Cardoso, Raquel Pinto, Elisabete Fernandes)

115
Planar Antenna for Terahertz Application in Fan Out Wafer Level Package
Daijiro Ishibashi, FUJITSU Laboratories Ltd.  (Yoshihiro Nakata)

042
Surviving the Heat Wave: A presentation of Thermally Induced Failures and Reliability Risks Created by Advancements in Electronic Technologies
Greg Caswell, DfR Solutions

10:15 am - 10:40 am

015
Reduction of Thermal Stress - Part II: Passivation Thickness Optimization of FLATPV Bump Design
Raj Sekar Sethu, X-FAB Semiconductor Foundries AG (Salil Hari Kulkarni, How Ung Ha, Kok Heng Soon)

047
Thermal & viscoelastic properties of underfills using hexagonal boron nitride (hBN) nanofiller
Sara Abbasirazgaleh, North Carolina A&T State University (Shyam Aravamudhan)

056
Fan-Out Wafer-Level Packaging of Large Chip with Multiple Redistribution-Layers
John Lau, ASM Pacific Technology (Ming Li, Nelson Fan, Eric Kuah, Zhang Li, Kim Hwee Tan, Tian DeWen, Margie Li, Mian Tao, Jeffery Lo, Rozalia Beica, YuHua Chen, CT Ho, Sze Pei Lim, NC Lee, Jiang Ran)

114
Fully Printed Static Gain Reconfigurable Conformal Patch Antenna Arrays
Nolan Grant, University of Massachusetts Lowell (Mahdi Haghzadeh, Alkim Akyurtlu)

087
Modeling Vibration Induced Fatigue Failure of Free Standing Wirebonds
Zhenzhen Shen, Baker Hughes, Inc. a GE Company (James Story, Otto Fanini, Michael Osterman)

10:45 am - 11:10 am

067
Electrochemical Analysis of Aged Copper Plating Bath in Wafer Level Packaging
Michael Pavlov, ECI Technology (Danni Lin, Eugene Shalyt, Isaak Tsimberg)

146
Solderability and Reliability Evolution of No-Clean Solder Fluxes For Selective Soldering
Jonathan Cetier, Inventec Performance Chemicals (Rodrigo Aguilar, Emmanuelle Guene, Aurelie ducoulombier, Richard Anisko, Anne Marie Laugt)

2017imaps058
Polyimide and Photoresist Residue Detection in Advanced Packaging
Jonathan Cohen, Rudolph Technologies (Gurvinder Singh, WooYoung Han, Mike Marshall)

101
Multi-factor product authentication using integrated Quick Response (QR) Code Antenna
John Doroshewitz, Michigan State University  (Jeffrey Nanzer, Premjeet Chahal, Amanpreet Kaur)

167
Reinforced Solder Technology for Increased Reliability
Tim Jensen, Indium Corporation (Sunny Neoh, Adam Murling)

 

11:15 am - 12:55 pm: 
POSTERS & PIZZA
(in Foyer)
Session Chairs: Bill Marsh, Northrop Grumman; Richard Stephenson, Silicon Valley Materials Technology Corp, Inc.

Posters & Pizza Sponsored by:

2017imaps124
Stencil Print solutions for Advance Packaging Applications
Phani Vallabhajosyula, Photo Stencil 

2017imaps040
Rapid Prototyping Tape Stencils for the Application of Solder Paste
Mimi Yang, Stanford University (Karen Dowling, Debbie Senesky, H.-S. Philip Wong)

2017imaps002
High Current Testing and Simulation for Land Grid Array Sockets
Brian Beaman, IBM (Jean Audet)

2017imaps131
Relation between relative humidity and electrical performance of electrochromic displays 
Alexandre Garcia, SINTEF (Huiting Jin, Kjell Olafsen, Sigbjorn Kolberg, Daniel Nilsen Wright, Maaike M. Visser Taklo; SINTEF; Annelie Eveborn, Olle Hagel, Torbjorn Eriksson, Thin Film Electronics)

2017imaps154
Dark Current Leakage in Optoelectronic Hermetic Packages 
Marwan Albarghouti, SEMTECH (Clara Dionet, Kevin Ma)

017imaps098
3D Printed Integrated Microfluidic Cooling for High Power RF Applications 
Premjeet Chahal, Michigan State Univerisity (Michael Craton, Mohd Ifwat Mohd Ghazali, Brian Wright, Kyoung Youl Park, John Papapolymerou)

2017imaps047
Thermal & viscoelastic properties of underfills using hexagonal boron nitride (hBN) nanofiller
Sara Abbasirazgaleh, North Carolina A&T State University (Shyam Aravamudhan)

2017imaps049
Challenges of Large Format Packaging and Some of Its Assembly Solutions 
Eric Kuah, ASM Pacific Technology (Nelson Fan, Li Ming, John Lau, Eric Ng, Tian DeWen, Wu Kai)

2017imaps058
Polyimide and Photoresist Residue Detection in Advanced Packaging
Jonathan Cohen, Rudolph Technologies (Gurvinder Singh, WooYoung Han, Mike Marshall)

2017imaps125
Flip chip reliability and design rules for SIP module
Morard Adrien, SAFRAN SA (Pares Gabriel, Riou Jean-Christophe)

2017imaps146
Solderability and Reliability Evolution of No-Clean Solder Fluxes For Selective Soldering
Jonathan Cetier, Inventec Performance Chemicals (Rodrigo Aguilar, Emmanuelle Guene, Aurelie ducoulombier, Richard Anisko, Anne Marie Laugt)

2017imaps162
Inkjet and 3D Printing Technology for Fundamental Millimeter-Wave Wireless Packaging
Bijan Tehrani, Georgia Institute of Technology (Ryan Bahr, Manos Tentzeris)


 

THURSDAY AFTERNOON PROGRAM

 

CHIP PACKAGE INTERACTION (CPI)

HIGH PERFORMANCE, RELIABILITY, & SECURITY

ADVANCED PACKAGING & ENABLING TECHNOLOGIES

ADVANCED PACKAGING & SYSTEM INTEGRATION

ADVANCED MATERIALS & PROCESSES

 

Session THP1
Materials and Reliability II

Session Chairs: Raja Swaminathan, Intel Corp.; Nick Leonardi, SMART Microsystems

The second session of the two sessions addressing this topic further elaborates ways to analyze and address a variety of CPI that have implications for reliability in advanced packages and focuses on the interactions among critical factors that affect reliability such as assembly processes, thermomechanical stress development, materials properties, and package geometries.

Session THP2
Assuring Device Security - Network and Microelectronic Solutions

Session Chairs: Erica Folk, Northrop Grumman; Wayne Churaman, ARL

Security Strategies using Devices, Packaging, and Software.

Session THP3
Embedded Packaging

Session Chairs: Karl-Friedrich Becker, Fraunhofer IZM; Doug Link, Starkey Hearing

Recent developments in the field of embedding/integrating active component in/on printed circuit boards, covering technological as well as cost aspects.

Session THP4
Panel/Board level System-Integration

Session Chairs: Vanessa Smet, Georgia Tech, PRC; Zhenzhen Shen, Baker Hughes, Inc. a GE Company

This session is focused on technology that enables further miniaturization and heterogeneous board/panel integration, including large area processing and SIP integration.

Session THP5
Additive Manufacturing

Session Chairs: Craig Armiento, University of Massachusetts Lowell; Paul Deffenbaugh, SCIPERIO

Additive technologies are now being applied to the fabrication of electronics and will transform manufacturing processes, enable rapid prototyping and create new form factors for electronic products. This session will review ongoing efforts to apply additive technologies to a variety of electronic applications.

1:00 pm - 1:25 pm

037
Reliable Chip & Bond Wire QA Sampling, Counting & Inspection by Implementing Multiple Magnification AOI
Hector Fonseca, Nordson Yestech, Advanced Technology Systems

112
Supply Chain Hardware Integrity for Electronics Defense (SHIELD) Using Small "Dielets"
Len Chorosinski, Northrop Grumman (Richard Calatayud, Parrish Ralston, Scott Suko, David Fry, Venky Sundaram, Klaus Wolter, Nathanael Ellerhoff)

028
Development of Thinner POP base Package by Die Embedded and RDL Structure
Masahiro Kyozuka, SHINKO Electric Industries Co., Ltd. (Takahiko Kiso, Koichi Tanaka, Tetsuya Koyama)

007
Ultra-fine Cu Wiring Surrounded by Electroless-Plated Ni: Effective Structure for High Insulation Reliable Wiring Applicable to Panel Level Fabrication
Masaya Toba, Hitachi Chemical

107
Prototyping and Production of High-temperature Power Electronic Substrates through Additive Manufacturing Processes
Thomas Stoll, Friedrich-Alexander-Universität Erlangen-Nürnberg (FAU), Institute for Factory Automation and Productions Systems (FAPS) (Joerg Franke, FAU, FAPS; Aarief Syed-Khaja, Heraeus Electronics)

1:30 pm - 1:55 pm

012
Investigation & Resolution of Current Leakage Failure caused by Carbon Black Aggregation in Mold Compound
Akhilesh Singh, NXP Semiconductors (Teck Beng Lau, Nishant Lakhera, Hoffmann James, Boon Yew Low)

138
Secure Tunable LNA Design for Internet of Things 
Bruce Kim, City University of New York/CCNY (Sang-Bock Cho)

050
Cost Comparison of Fan-out Wafer-Level Packaging to Embedded Die Packaging
Chet Palesko, SavanSys Solutions LLC (Amy Lujan)

049
Challenges of Large Format Packaging and Some of Its Assembly Solutions
Eric Kuah, ASM Pacific Technology (Nelson Fan, Li Ming, John Lau, Eric Ng, Tian DeWen, Wu Kai)

149
3D Printed Electronic Processes for the Next Generation of Printed Circuit Structures 
Kenneth Church, Sciperio (Sam LeBlanc, Paul Deffenbaugh)

2:00 pm - 2:25 pm

159
Demonstration of Embedded Cu Trench RDL using Panel Scale Lithography and Photosensitive Dry Film Polymer Dielectrics

Venky Sundaram, Fuhan Liu, Chandra Nair, Rao Tummala (GT), Atsushi Kubo, Tomoyuki Andoh (TOK Japan), Keith Best, Corey Shay (Rudolph Technologies).

160
Nondestructive Imaging of Packaged Microelectronics using Pulsed Terahertz Technology 
Magda El-Shenawee, University of Arkansas (Tyler Bowman)

062
Multichip Module Planarity Requirements Derived From Solder Surface Tension Models
Thomas Marinis, Draper (Joseph Soucy)

1125
Flip Chip Reliability and Design Rules For SIP Module
Morard Adrien, SAFRAN SA (Gabriel Pares, Jean-Christophe Riou)

148
Additive Packaging for Microwave Applications
Craig Armiento, University of Massachusetts Lowell (Susan Trulli, Christopher Laighton, Elicia Harper, Raytheon Integrated Defense Systems; Mahdi Haghzadeh, Alkim Akyurtlu, University of Massachusetts Lowell)

2:30 pm - 2:55 pm

016
Reduction of Thermal Stress - Part III: UBM Thickness and Passivation Thickness Optimization
Raj Sekar Sethu, X-FAB Semiconductor Foundries AG (Salil Hari Kulkarni, How Ung Ha, Kok Heng Soon)

 

153
Next Generation Chip Embedding Technology for High Efficient Mid Power Modules 
Kay Essig, Mark Gerber, ASE Group (CT Chiu, Jarris Kuo, Phidia Chen, Jean-Marc Yannou)

 

158
Direct Write Additive Manufacturing of 'Born Qualified' Ceramic Components 
Adam Cook, Sandia National Labs (Christopher Diantonio, William Reinholtz, Daniel Kammler, Harlan Brown-Shaklee, Fadi Abdeljawad) 

 


Register Online

 

 

 

 


PREMIER Sponsors:

 

    Premier Program Sponsor:
Premier Program Sponsor - Heraeus Materials Technology

    Premier Technology Sponsor:

    Premier Technology Sponsor:
    Premier Technology Sponsor:
Premier Tech Sponsor - NGK NTK
Premier Tech Sponsor - EMD Performance Materials
Premier Tech Sponsor - Amkor Technology
Event Sponsors:
Keynote Sponsor:

Keynote Sponsor: SAMTEC

Exhibit Lunch Sponsor:

Lunch Sponsor: MRSI

Posters & Pizza Sponsor:

Northrop Grumman EC - Poster Session Sponsor

Coffee Break Sponsor:

Break Sponsor: Geib Refining

Coffee Break Sponsor:

Break Sponsor: Pac Tech

Bag Insert Sponsor:

Bag Insert Sponsor: NorCom Systems

Student Programs Sponsor:

Honeywell - Student Programs Sponsor

Student Programs Sponsor:

Applied Materials - Keynote Sponsor
Panel Wine Reception Sponsor:

Wine Reception Sponsor: Nagase Co. Ltd.
Panel Wine Reception Sponsor:

Wine Reception Sponsor: Nagase America Corp.
More sponsorships available
 
Golf Sponsors
EMD Performance Materials - Corporate Sponsor
Technic - Golf Hole Sponsor
Stellar Industries - Golf Hole Sponsor
Golf Hole Sponsor: 
Advance Reproductions
golf holes/sponsors still available
     
Media Sponsors
Media Sponsor: MEMS Journal
Media Sponsor: US Tech
Solid State Technology - Media Sponsor
Media Sponsor: MEPTEC
3D Incites - Media Sponsor
Media Sponsor: Webcom - Antenna Systems & Technology
Media Sponsor: Webcom - Electronics Protection
Media Sponsor: Webcom - Thermal News
Media Sponsor: Chip Scale Review
     

 




CORPORATE PREMIER MEMBERS
  • Amkor
  • ASE
  • Canon
  • EMD Performance Materials
  • Honeywell
  • Indium
  • Kester
  • Kyocera America
  • Master Bond
  • Micro Systems Technologies
  • MRSI
  • NGK NTK
  • Palomar
  • Plexus
  • Promex
  • Qualcomm
  • Quik-Pak
  • Raytheon
  • Specialty Coating Systems