Honeywell

IMAPS 2018 Pasadena

IMAPS 2018 - Pasadena
51st Symposium on Microelectronics
www.imaps2018.org

Conference:
October 9-11, 2018
Exhibition:
October 9-10, 2018
Professional Development Courses:
October 8, 2018
General Chair:
Mark Gerber
ASE US Inc.
General Chair-elect (2019):
Curtis Zwenger
Amkor Technology
Past General Chair (2017):
Dan Krueger
Honeywell FM&T

 
    PREMIER PROGRAM SPONSOR:
 
 
Premier Program Sponsor - Heraeus Materials Technology

 

    PREMIER TECHNOLOGY SPONSOR :

    PREMIER TECHNOLOGY SPONSOR :

   PREMIER TECHNOLOGY SPONSOR:
Bag Insert Sponsor: ASE Group
Premier Tech Sponsor - NGK NTK
Keynote Sponsor: SAMTEC

Professional Development Courses
(PDCs / Short Courses / Tutorials)

REGISTER ONLINE

For Exhibitors
     

 

Monday, October 8: 2-hour formats, by theme/track
8:00 AM-10:00 AM | 10:30 AM - 12:30 PM | 1:00 PM - 3:00 PM | 3:30 PM - 5:30 PM
*Attendees can take ONE PDC during each timeslot*

  Track A:
Intro to Microelectronics Packaging
Track B:
Process and Materials
Track C:
Emerging Technologies
Track D:
Reliability
8:00 AM-10:00 AM

A1: Fundamentals of Microelectronics Packaging - PART 1 - John Pan, Cal Poly University

B1: Polymers Used in Wafer Level Packaging - Jeff Gotro, InnoCentrix

C1: Flexible Ceramics - John Olenick, ENrG Inc.

CANCELLED

D1: Achieving High Reliability Solder Joints for Lead-Free Alloys - Dr. Ning-Cheng Lee, Indium Corporation

10:00 AM-10:30 AM
Coffee / Networking
Open to all PDC participants
10:30 AM - 12:30 PM

A2: Introduction to System in Package (SiP) - The Heterogeneous Integration Driver - Mark Gerber, ASE US, Inc.

B2: Electroplating Processes for Flip Chips - Fred Mueller Consultant, Metal Finishing Instructor

C2: Electronic Packaging for 5G Microwave and Millimeter Wave Systems - Rick Sturdivant, Ph.D., Azusa Pacific University

D2: Package/Board Level Integrity & Solder Joint Reliability - Dr. Jennie S. Hwang, Ph.D., D.Sc. H-Technologies Group

12:30 PM-1:00 PM
Lunch
Open ONLY to PDC participants taking morning AND afternoon courses
1:00 PM-3:00 PM

A3: Fan-Out Wafer/Panel-Level Packaging - John Lau, ASM

B3: Introduction to Solder Flip Chip with an Emphasis on Cu Pillar - Mark Gerber, ASE US, Inc.

C3: MEMS and nanoMEMS Packaging - Slobodan Petrovic, Oregon Institute of Technology

D3: A Methodology for Understanding the Reliability of Electronic Packaging - Greg Caswell, DfR Solutions

3:00 PM-3:30 PM
Coffee / Networking
Open to all PDC participants
3:30 PM-5:30 PM

A4: Fundamentals of Microelectronics Packaging - PART 2 - John Pan, Cal Poly University

B4: Temporary Bonding of Electronics (Wafers, Packages, Displays) - John Moore, Daetec LLC

CANCELLED

C4: Fundamentals of 3D and 2.5D Packaging Integration - Urmi Ray, JCET Group

D4: Thermal Stress Failures in Electronic Packaging: Prediction and Prevention - Ephraim Suhir, Portland State University

5:30 PM-7:30 PM
Welcome Reception
Open to all IMAPS 2018 participants

 

Cost for Each PDC: $300 (on/before 9/12/2018); $400 (after 9/12/2018)
REGISTER ONLINE

 

Get off line and learn Face to Face...Sign up for a PDC!

PDCs (Professional Development Course) are a big part of the Annual IMAPS Symposium each year. Why not plan to take a course on Monday before IMAPS 2018 kicks off and take advantage of the rich learning opportunities available at the IMAPS symposium.

PDCs are all now scheduled for 2-hour lessons. Shorter courses for you to digest great information without being overwhelmed by a 4-8 hour commitments after your travels! The shorter tutorials also allow for you to participate in more topical areas and learn from a variety of instructors! The courses are also now arranged under 4 "TRACK" categories: (A) Introduction to Microelectronics Packaging; (B) Process and Materials; (C) Emerging Technologies; and (D) Reliability.

PDCs create a unique environment whereby students can personally interact with the instructors, and with each other in the classroom and over lunch. It's mentally stimulating and the new found professional connections will prove to be valuable in the long run. Learning on line is fine, but it cannot duplicate hours spent immersed in a specific topic, led by an industry expert in the field and surrounded by like-minded professionals.

This year we've put together another impressive assortment course options Our goal is to make the IMAPS PDCs the premier learning experience; so we ask that you take time to fill out the evaluation form that accompanies each course and give us your feedback on this or any other aspects of the PDCs. Read through the course descriptions on line and pick the course that best suits your company and career objectives. Every PDC includes a full set of comprehensive course notes. Class sizes typically range from ten to thirty students and there is always ample time for questions and networking. We hope you will consider joining us in Pasadena for a learning experience like no other.

Education is a lifelong pursuit, don't miss out on this opportunity!
Curtis Zwenger and Urmi Ray
IMAPS 2018 PDC Organizers

 

Your PDC Registration Fee Includes:

  • Refreshment breaks
  • Hard-copy workbook of course materials (no electronic copies provided)
  • Lunch (ONLY for those taking Morning & Afternoon courses)

PDCs under SESSIONS
during IMAPS 2018 Online Registration

PDC Cancellation policy: IMAPS reserves the right to cancel a course if the number of attendees is not sufficient.
You can transfer to a different course or we will refund you the corresponding amount.

Cost for Each PDC: $300 (on/before 9/12/2018); $400 (after 9/12/2018)
REGISTER ONLINE


 

Early Monday Morning (8:00 AM-10:00 AM) Courses
YOU MAY SELECT ONE OF THESE FOUR COURSES ONLY

Track A:
Intro to Microelectronics Packaging
Track B:
Process and Materials
Track C:
Emerging Technologies
Track D:
Reliability

A1: Fundamentals of Microelectronics Packaging - PART 1

Instructor:
John Pan, Cal Poly University

Course description:

This course will review various electronics package types from common packages DIP, PGA, SOP, QFP, PLCC, BGA, CSP, QFN, and LGA to the latest packages PoP, SiP, TSV, 2D, 2.5D, and 3D packaging. The materials and processes used in wire bonding and flip chip for interconnection will be presented.

Course outline:

- Introduction to Microelectronics Packaging
-- Electronics Packaging Hierarchy and Functions
-- Electronics Package Types
-- Electronics Packaging Trends

- Microelectronics Packaging Materials and Processes
-- Die attachment
-- Wire bonding
-- Flip Chip
-- Encapsulation and Sealing

At the end of this course, participants should be able to:

- Identify various electronics package types from common packages DIP, PGA, SOP, QFP, PLCC, BGA, CSP, QFN, and LGA to the latest packages PoP, SiP, TSV, 2D, 2.5D, and 3D packaging;
- Describe microelectronics and electronic packaging processes including die attachment, wire bonding, flip chip, and encapsulation.

Biography:

Dr. John Pan is a professor in Industrial and Manufacturing Engineering Department at California Polytechnic State University, San Luis Obispo. His research interests include the materials, processes, and reliability of microelectronics packaging. He has authored or co-authored over 40 technical papers. He is a Fellow of IMAPS and a recipient of the 2011 IMAPS Outstanding Educator Award. He is currently the Editor-in-Chief of Journal of Microelectronics and Electronic Packaging and an Associate Editor of IEEE Transactions on Components, Packaging and Manufacturing Technology.

 

B1: Polymers Used in Wafer Level Packaging

Instructor:
Jeff Gotro, InnoCentrix LLC

Course description:

The course will provide an overview of polymers and the important structure-property-process-performance relationships for polymers used in wafer level packaging. The main learning objectives will be:

1) understand the types of polymers used in wafer level packages, including underfills (pre-applied and wafer applied), mold compounds, and substrate materials

2) gain insights on how polymers are used in Fan Out Wafer Level Packaging, specifically mold compounds and polymer redistribution layers (RDL)

3) learn the key polymer and processes challenges in Fan Out Wafer Level Packaging.

Participants are invited to bring problems for discussion.

Biography:

Dr. Jeff Gotro is currently the President of InnoCentrix, LLC, a boutique consulting firm serving clients in the polymers and electronic materials industry. Jeff has consulted with over 40 clients since founding InnoCentrix in 2008. He has over thirty five years experience in polymers for electronic applications having held scientific and leadership positions at IBM, AlliedSignal, Honeywell, and Ablestik Laboratories. He has presented numerous invited lectures and short courses at technical meetings, has over 60 technical publications and 21 patents/patent applications. Jeff is a member of the American Chemical Society (ACS), the Institute for Management Consultants (IMC), Society of Plastics Engineers, the IEEE Electronic Packaging Society, and is a Fellow of the International Microelectronics Assembly and Packaging Society (IMAPS). In 2014, Dr. Gotro received the John Wagnon Technical Achievement award from IMAPS. Jeff holds a Ph.D. in Materials Science with a specialty in polymer science from Northwestern University.

C1: Flexible Ceramics

Instructor:
John A. Olenick, ENrG Incorporated

CANCELLED

D1: Achieving High Reliability Solder Joints for Lead-Free Alloys

Instructor:
Ning-Cheng Lee, Indium Corporation

Course description:

This course covers the reliability of lead-free solder joints. The reliability discussed includes the failure modes, thermal cycling reliability, and fragility of solder joints as a function of material combination, thermal history, and stress history, and novel alloys with reduced fragility will be presented. Also will be introduced is the novel solder alloys designed for wide service temperature range automotive applications, and the mechanisms of achieving high reliability are reviewed. Corrosion, and tin whisker will also be discussed. The emphasis of this course is placed on the understanding of how the various factors contributing to the reliability.

Biography:

Ning-Cheng Lee is Vice President of Technology of Indium Corporation. He has been with Indium since 1986. Prior to joining Indium, he was with Morton Chemical and SCM. He has more than 30 years of experience in the development of fluxes and solder pastes for SMT industries. He received his PhD in polymer science from University of Akron in 1981, and BS in chemistry from National Taiwan University in 1973. He is author of “Reflow Soldering Processes and Troubleshooting: SMT, BGA, CSP, and Flip Chip Technologies”, and co-author of “Electronics Manufacturing with Lead-Free, Halogen-Free, and Conductive-Adhesive Materials”. He was honored as 2002 Member of Distinction from SMTA, 2003 Lead Free Co-Operation Award from Soldertec, 2006 Exceptional Technical Achievement Award and 2007 Distinguished Lecturer from CPMT, 2009 Distinguished Author from SMTA, 2010 Electronics Manufacturing Technology Award from CPMT, 2015 IEEE Senior Member, 2015 Founder’s Award from SMTA, and 2017 IEEE Fellow.

10:00 AM-10:30 AM
Coffee / Networking

Open to all PDC participants

 

Late Monday Morning (10:30 AM - 12:30 PM) Courses
YOU MAY SELECT ONE OF THESE FOUR COURSES ONLY

Track A:
Intro to Microelectronics Packaging
Track B:
Process and Materials
Track C:
Emerging Technologies
Track D:
Reliability

A2: Introduction to System in Package (SiP) - The Heterogeneous Integration Driver

Instructor:
Mark Gerber, ASE US, Inc.

Course description:

This PDC course will introduce the package platform SiP (System-in-Package) and how some companies are diversifying from SOC (System-on-a-Chip) to leverage heterogeneous silicon integration and overall package miniaturization. A short market perspective will be reviewed as well as how industry segments are leveraging SiP and how the OEM market is evolving and creating system level ecosystems to enabling content revenue - a key area of IOT. SiP general process flow details will be covered as well as key process considerations for yield improvements. In addition, a brief overview of some of the tools that may be leveraged to help miniaturize module solutions and improve performance. As SiP has evolved, there has also been interest in Fan Out Wafer level technology and the potential integration of multiple active devices as well as discretes into this technology - a brief overview of this option and considerations will be discussed.

Biography:

Mark Gerber is the Director of Engineering & Technical Marketing at ASE-US Inc, specializing in Flip Chip and Advanced Interconnect package technologies. Mark joined ASE in Feb of 2015, and brings a diverse set of semiconductor experiences from Texas Instruments, Motorola/Freescale, and Dallas Semiconductor, including advanced interconnect & IC package development, as well as a history of new product introductions. Mark holds a bachelors degree in Mechanical Engineering from Texas A&M University, and has worked in the Semiconductor Industry for the last 20 years, has written +20 papers, and currently holds over 30 patents in the area of semiconductor packaging.

 

B2: Electroplating Processes for Flip Chips

Instructor:
Fred Mueller, Consultant, Metal Finishing Instructor

Course description:

- Provides a timely overview of the chemistries of electrolytic: Copper, Lead-free Solder and Indium used in the creation of Flip Chips.

- Discusses the various rectifier wave forms that can be used to improve the deposit/thickness distribution over the whole area to be plated.

- Presents methods for controlling the properties of plating solutions to maximize the deposit properties;

- Highlight the engineering differences and troubleshooting problems in these plating processes.

Biography:

Mr. Mueller is a consultant in metal finishing and has served as a national certified instructor for the American Electroplaters and Surface Finishing Foundation (AESF). He has over twenty-five years experience in the plating industry in printed circuits and plating for electronics. As a Chemist, Fred has conducted experiments and presented technical papers at SurFin on various topics in electroplating. Mr. Mueller has spent time on both sides of the Nadcap Chem Process as an Nadcap auditor and Chem Process Accreditation maintainer. As a consultant, he stresses the importance of controlling of special processes to control the quality of the final product.

C2: Electronic Packaging for 5G Microwave and Millimeter Wave Systems

Instructor:
Rick Sturdivant, Azusa Pacific University

Course description:

Electronic packaging at microwave and millimeter wave frequencies is an important capability required for modern communication systems. This is because performance of the systems depends upon successful interconnections between subsystems, components, and parts. Since 5G systems rely on frequency bands approaching 100GHz, special care must be exercised in their design that is not required for 3G/4G systems.

Therefore, this professional development course will provide attendees with the knowledge required for interconnects and packaging at the integrated circuit, circuit board, and system level. This includes essential information on materials, fabrication methods, transmission lines, interconnection methods, transitions, components, and integration methods such as 3D packaging.

The course will start with specifics on 5G microwave and millimeter-wave communication systems, and major subsystems such as antennas and transmit/receive modules. This will be followed by details of technologies and solutions. The talk will conclude with a short review and predictions on the future directions of packaging technology.

At the end of this course, attendees will have practical knowledge about electronic packaging for 5G systems.

Biography:

Dr. Rick Sturdivant is a recognized expert in the fields of electronic packaging, transmit/receive modules, and phased arrays. He is coeditor of RF and Microwave Microelectronics Packaging II (Springer Publishing, 2017), coauthor of Transmit Receive Modules for Radar and Communication Systems (Artech House, 2015), and author of Microwave and Millimeter-wave Electronic Packaging (Artech House, 2013). He has also contributed several book chapters, numerous journal papers and conference papers, and he holds seven U.S. patents. From 1989 to 2000, he engineered transmit receive modules for Hughes/Raytheon where he received the engineering excellence award for developing the world’s first tile array module. Since the year 2000, he has started several successful technology companies providing solutions for wireless, microwave, millimeter-wave, and high-speed products. He is an Assistant Professor at Azusa Pacific University, and Founder and Chief Technology Officer of Microwave Products and Technology, Inc. He earned a Ph.D. degree from Colorado State University, M.A. degree from Biola University, M.S.E.E. degree from the University of California at Los Angeles, B.S.E.E. degree from the California State University at Long Beach, and the B.A. degree from Vanguard University. For more information, visit his website at ricksturdivant.com.

D2: Package/Board Level Integrity & Solder Joint Reliability

Instructor:
Jennie S. Hwang, Ph.D., D.Sc., H-Technologies Group

Course description:

With the goal to produce reliable products while achieving high yield production, this course provides a holistic overview of product reliability and of critical "players" of the package/board level integrity and solder joint reliability, including the roles of materials, processes and testing/service conditions, as well as the crucial principles behind the product reliability. Recent developments related to lead-free package and board assembly, lead-free solder materials, PCB laminates and surface finishes in relation to manufacturability and reliability will be outlined. The likely solder joint failure modes (interfacial, near-interfacial, bulk, inter-phase, intra-phase, voids-induced, surface-crack and others) will be illustrated. Solder joint reliability fundamentals including fatigue and creep damage mechanisms via ductile, brittle, ductile-brittle fracture will be outlined. To withstand harsh environments, the strengthening metallurgy to further increase fatigue resistance and creep resistance and the power of metallurgy and its ability to anticipate the relative performance will be illustrated by examining the comparative performance in relation to metallurgical phases and microstructures. Parameters for a working life-prediction model will be highlighted. A relative reliability ranking among commercially viable solder systems, the scientific, engineering and manufacturing reasons behind the ranking, and newer solder alloy developments and their impact on product performance and reliability will be summarized. The course also examines the role of intermetallics at-interface and in-bulk (contributing from packages and board surface finish coating) in relation to product reliability. The difference between SnPb and Pb-free solder joint in terms of intermetallic compounds, which in turn is attributed to production-floor phenomena and the actual field failure, will be discussed. From practical perspectives, tin whisker with emphasis on risk mitigation through understanding the factors that affect tin whisker growth and its preventive and remedial solutions will be outlined. Practical tin whisker criteria for reliability implications in the lead-free environment and the relative effectiveness and the order of priority in mitigating measures will be ranked. The course emphasizes on practical, working knowledge, yet balanced and substantiated by science. Attendees are encouraged to bring their own selected systems for deliberation.

Biography:

Dr. Hwang, a long-standing leader in lead-free implementation and SMT manufacturing, brings deep knowledge to this course through both hands-on and advisory experiences. Author of 500+ publications including several internationally-used textbooks and a speaker in innumerable international and national events, she has provided solutions to many challenging problems, ranging from production yield to field failure diagnosis to reliability issues in both commercial and military applications. Received numerous honors and awards (e.g., inductee of International Hall of Fame-Women in Technology, National Academy of Engineering, YWCA Achievement Award, R&D-Stars-to-Watch). Has served on the Board of NYSE Fortune 500 companies and on various civic, government and university boards and committees (e.g., Defense Dept. - Globalization Committee, Forecasting Future Disruptive Technologies Committee, National Materials and Manufacturing Board.) She chairs the Board of the Assessment of Army Research Laboratory, of NIST, National, National Laboratory Assessment Board and the Board of Army Science and Technology. She is a reviewer of various government programs and publications. Her formal education includes Harvard Business School Executive Program and four academic degrees (Ph.D. M.S., M.S., B.S.) in Materials Science & Engineering, Physical Chemistry, Organic Chemistry and liquid Crystal Science. She has held various senior executive positions with Lockheed Martin Corp., IEM Corp. and others. Also an invited distinguished adj. Professor of Engineering School of Case Western Reserve University, and serves on the University's Board of Trustees.

12:30 PM-1:00 PM
Lunch

Open ONLY to PDC participants taking morning AND afternoon courses

 

Early Monday Afternoon (1:00 PM - 3:00 PM) Courses
YOU MAY SELECT ONE OF THESE FOUR COURSES ONLY

Track A:
Intro to Microelectronics Packaging
Track B:
Process and Materials
Track C:
Emerging Technologies
Track D:
Reliability

A3: Fan-Out Wafer/Panel-Level Packaging

Instructor:
John H Lau, ASM Pacific Technology

Course description:

The fundamental and recent advances of the following items will be discussed.

(1) Patents Impacting the Semiconductor Packaging.

(2) Fan-out Wafer/Panel-Level Packaging Formations: Chip-first (die-down); Chip-first (die-up); Chip-last (RDL-first).

(3) RDL Fabrications: Polymer and ECD Cu + Etching; Photosensitive Polymer and ECD Cu + Etching; PECVD and Cu-damascene + CMP.

(4) TSMC InFO-WLP and InFO-PoP.

(5) Wafer vs. Panel Carriers.

(6) Issues of Panel Carrier.

(7) Notes on Dielectric and Epoxy Mold Compound.

(8) Semiconductor and Packaging for IoTs (SiP).

(9) Wafer-Level System-in-Package (WLSiP).

(10) Examples: Amkor's SWIFT; Amkor's SLIM with FOWLP; SPIL's FOWLP with Hybrid RDLs; STATS ChipPac's FOFC eWLB; ASE's FOCoS; MediaTek's RDLs by FOWLP; Heterogeneous Integration by FOWLP; 3D IC Heterogeneous Integration by FOWLP; Assembly of Heterogeneous Integration.

(11) FOWLP Heterogeneous Integration Trends.

Biography:

With more than 40 years of R&D and manufacturing experience in semiconductor packaging, John Lau has published more than 450 peer-reviewed papers, 30 issued and pending US patents, and 18 textbooks on, e.g., Advanced MEMS Packaging, Reliability of RoHS compliant 2D and 3D IC Interconnects, TSV for 3D Integration, 3D IC Integration and Packaging, and Fan-Out Wafer-Level Packaging. John is an elected ASME Fellow, IEEE Fellow, and IMAPS Fellow.

 

B3: Introduction to Solder Flip Chip with an Emphasis on Cu Pillar

Instructor:
Mark Gerber, ASE US, Inc.

Course description:

This PDC course will provide a historical overview and background on Solder Flip Chip technology with an emphasis on Copper Pillar Flip Chip as well as short market perspective. Interconnect structure, process flows, materials and package integration process methods for evolving Flip Chip applications will be discussed in detail. The understanding The trade-offs between The traditional Solder based Flip Chip and Copper Pillar is key in determining The silicon device layout and The type of design rules that can be leveraged for new products. as part of This course, The Solder Bump and Copper Pillar Bump structure formation will be reviewed as well as multiple Cu Pillar Flip Chip attachment methods such as Mass Reflow and Thermo-Compression Non-Conductive Paste (TCNCP) bonding. Reliability aspects such as IMC formations and ways to address will also be covered as a key consideration for Interconnect decisions. Current market trends have led to additional questions regarding the longevity of Flip Chip versus other competing technologies such as Fan Out Wafer Level Packaging (FOWLP) will also be reviewed as well as a comparison between technologies.

Biography:

Mark Gerber is the Director of Engineering & Technical Marketing at ASE-US Inc, specializing in Flip Chip and Advanced Interconnect package technologies. Mark joined ASE in Feb of 2015, and brings a diverse set of semiconductor experiences from Texas Instruments, Motorola/Freescale, and Dallas Semiconductor, including advanced interconnect & IC package development, as well as a history of new product introductions. Mark holds a bachelor's degree in Mechanical Engineering from Texas A&M University, and has worked in the Semiconductor Industry for the last 20 years, has written +20 papers, and currently holds over 30 patents in the area of semiconductor packaging.

C3: MEMS and nanoMEMS Packaging

Instructor:
Slobodan Petrovic, Oregon Institute of Technology

Course description:

This full day course will provide a review of MEMS devices and explore futuristic concepts that combine MEMS and nanoscience. The merging of nanoscience and microelectromechanical systems presents an opportunity for development of next generation technologies for use in computers, wireless communication, biomedicine, and a variety of sensors. The course will start by providing an in-depth overview of the MEMS principles of operation, fabrication methods, and in particular the materials used in building MEMS structures. Variety of MEMS devices will be discussed while a particular emphasis will be placed on MEMS in wireless communication; and sensors and actuators used in industrial, medical, and automotive applications. The introduction to nanoscience will start by evaluating how size can influence the properties of nanoscale systems. The nanomaterial synthesis and characterization methods will be explored next. The highly speculative discussion will offer a possibility for using nanoscale phenomena for technological purposes related to MEMS. The emphasis will be placed on merging the nanoscience with MEMS fabrication principles, design considerations, integration aspects, and packaging. In the third section, the packing and reliability of MEMS and nanoMEMS devices will be discussed. The integration of power supplies and energy storage devices with MEMS and nanoMEMS devices will also be covered. These devices will be the key in the packaging and for autonomous function of future devices.

Biography:

Dr. Slobodan Petrovic is a professor at the Oregon Institute of Technology in Portland, OR. His research interests are in the areas of MEMS fuel cells, packaging Li batteries, sensor media compatibility, and dye-sensitized solar cells. Prior to that, he was at the Arizona State University, where he taught courses in MEMS, Sensors, and alternative energy. Dr. Petrovic also held appointments at Clear Edge Power as a Vice President of Engineering; at Neah Power Systems as Director of Systems Integration; and Motorola, Inc. as a Reliability Manager. Dr. Petrovic has over 30 years of experience in MEMS, sensors, energy systems; fuel cells and batteries; and electrochemical solar cells. He has over 80 journal publications and conference proceedings; 2 book contributions and 35 pending or issued patents.

D3: A Methodology for Understanding the Reliability of Electronic Packaging

Instructor:
Greg Caswell, DfR Solutions

Course description:

Reliability is the measure of a product’s ability to perform its specified function at the customer’s facility, in their use environment, over the desired lifetime. Designing for reliability is the method for ensuring the reliability of a product or system during the design stage, before a physical prototype is produced is paramount. This course will describe the failure modes associated with die attach, wire bonding, and solder joints using a Physics of Failure approach. Strain energy equations will be discussed for the potential failure modes to help the student facilitate prediction of failure. The course will then discuss the relatively new failure mechanism, that of silicon wearout. As gate geometries have continued to shrink, the susceptibility of the device to fail has increased, to a point where some of the newer 14 nm feature devices will not hold up well in high reliability applications. We will look at the intrinsic mechanisms of ICs to understand their susceptibility based on environments. The next module of the course will demonstrate a methodology for using Physics of Failure to assess the failure modes associated with the populated circuit board, looking at issues such as thermo-mechanical fatigue, thermal effects, and the more probabilistic mechanisms like CAF and IMC fracture from mechanical shock. The approach will show how to predict failure at this level. Finally, the course will introduce a method for assessing the microvias in a package to identify the highest stressor points and provide an approach for obviation. Lastly, a short presentation on Electrostatic Discharge (ESD) and how to mitigate it will be presented

Biography:

Greg Caswell, a Senior Member of the Technical Staff for DfR Solutions, is an industry recognized expert in the fields of SMT, advanced packaging, printed board fabrication, circuit card assembly, and bonding solutions using nanotechnology. He has been well-regarded as a leader in the electronics contract manufacturing and component packaging industries for the past 45 years. Prior to joining DfR Greg was the Vice President of Engineering at Reactive Nanotechnology (RNT), where he led application development for the RNT Nanofoil® and ensured a successful transition of product technology to Indium Corporation. His previous appointments include Vice President of Business Development for Newport Enterprises, Director of Engineering for VirTex Assembly Services, and Technical Director at Silicon Hills Design. He has presented over 250 papers at conferences all over the world and has taught courses at IMAPS, SMTA and IPC events. He helped design the 1st pick and place system used exclusively for SMT in 1978, edited and co-authored the 1st book on SMT in 1984 for ISHM and built the 1st SMT electronics launched into space. B.A., Management (St. Edwards University). B.S., Electrical Engineering (Rutgers University)

3:00 PM-3:30 PM
Coffee / Networking

Open to all PDC participants

 

Late Monday Afternoon (3:30 PM - 5:30 PM) Courses
YOU MAY SELECT ONE OF THESE FOUR COURSES ONLY

Track A:
Intro to Microelectronics Packaging
Track B:
Process and Materials
Track C:
Emerging Technologies
Track D:
Reliability

A4: Fundamentals of Microelectronics Packaging - PART 2

Instructor:
John Pan, Cal Poly University

Course description:

This course will present the materials, processes, and reliability of electronic assembly including surface mount assembly, printed circuit board fabrication, organic and ceramic substrates, and flexible hybrid electronics.

Course outline:

Organic PCB Materials & Processes
o PCB Materials o Multi-layer PCB Fabrication Processes
o High-Density Interconnection (HDI)

Electronics Assembly Processes
o Surface Mount Assembly
o Soldering Basic
o Reflow soldering and wave soldering
o Lead-free solder joint reliability

Ceramics Substrate Materials & Processes
o Ceramics Materials
o LTCC
o HTCC

Flexible Hybrid Electronics (FHE)
o Printed organic electronics
o Assembly of ultra-thin silicon chips onto printed organic substrates

At the end of this course, participants should be able to:

- Describe materials and fabrication processes of multi-layer printed circuit boards and high-density interconnections.
- Describe PCB assembly processes and soldering.
- Evaluate different packaging substrate materials such as organic, ceramic, LTCC, and HTCC based on electrical, mechanical, and thermal performance as well as cost and reliability.
- Describe materials and fabrication processes of printed organic electronics and flexible hybrid electronics.

Biography:

Dr. John Pan is a professor in Industrial and Manufacturing Engineering Department at California Polytechnic State University, San Luis Obispo. His research interests include the materials, processes, and reliability of microelectronics packaging. He has authored or co-authored over 40 technical papers. He is a Fellow of IMAPS and a recipient of the 2011 IMAPS Outstanding Educator Award. He is currently the Editor-in-Chief of Journal of Microelectronics and Electronic Packaging and an Associate Editor of IEEE Transactions on Components, Packaging and Manufacturing Technology.

 

B4: Temporary Bonding of Electronics (Wafers, Packages, Displays)

Instructor:
John Moore, Daetec LLC

CANCELLED

C4: Fundamentals of 3D and 2.5D Packaging Integration

Instructor:
Urmi Ray, JCET Group

Course description:

This course will cover the fundamental technology aspects of 3D and 2.5D integration including summaries of key benefits, process flow, test, cost and reliability challenges. The goal of this course is to provide a review of technology status to date and spend additional time on case studies of market and product adoption.

Course outline:

-- Why 3D:
o New architectural & partitioning capabilities
o Package Density and Form Factor
o Improved Performance

-- Types of 3D:
o Via first
o Via middle
o Via last

-- Types of 2.5D
o Si/glass interposer
o Fan Out
o Laminate substrate/embedding

-- Manufacturing process flow for Via-middle

-- Manufacturing process flow for Si interposer

-- Challenges for market adoption
o Cost
o Reliability
o Supply Chain
o Others

-- Case Studies of successful recent product adoption
o HBM memory with TSV
o Graphics processor integration using 2.5D

-- Roadmap

Biography:

Urmi Ray is currently Senior Director at JCET Group focusing on advanced system in package (SIP) technologies. Prior to joining JCET Group, Urmi served as a Principal Engineer in Qualcomm where she had been the technology and program lead in several forward looking programs in 3D and 2.5D and system integration, with particular focus on low cost packaging for mobile industry. She joined Qualcomm in 2006, after spending 10+ years at Lucent Technologies Bell Laboratories in NJ working on advanced materials and reliability for a diverse set of product portfolios, including consumer products to high reliability telecommunications projects. She is currently active in many aspects of advanced packaging technology area. She has a PhD from Columbia University (New York City).

D4: Thermal Stress Failures in Electronic Packaging: Prediction and Prevention

Instructor:
Ephraim Suhir, Portland State University

Course description:

The short course addresses the following major topics:

1) Introduction: Physics of Thermal Stress; 2) Thermal Stress Types in Adhesively Bonded or Soldered Assemblies; 3)Typical Thermal Stress Failures in Adhesively Bonded or Soldered Assemblies; 4) What Could Possibly Be Done to Reduce Thermal Stresses; 5)Thermal Stresses in a Bi-Material Assembly with a Low Yield Stress Bonding Layer; 6) Design Recommendations for Improved Reliability of Electronic Packaging Assemblies Experiencing Thermal Loading; 7) Thermal Stress in Assemblies Bonded at the Ends; 8) Local and Global Interfacial Shearing Thermal Stresses and Their Interaction; 9) Tri-Material Assemblies Subjected to trhe Change in Temperatrure; 10) Flip-Chip Solder Joint Interconnections Should be Modeled as Tri-Material Assemblies; 11) Role of the Underfill and Its Glass Transition Temperature; 12) Assemblies with Low Modulus Bonds at the Ends; 13) Thermal Stress in Assemblies with Identical Adherends; 14) Accelerated Testing of Assemblies Subjected to Thermal Loading; 15) Elevated Stand-Off Heights of Solder Joints Could Relieve Thermal Stress in Them; 16) Thermal Stress in Column-Grid-Array and Ball-Grid-Array Designs; 17) Thermal Stress in Thin Films; 18) Thermal and Lattice Mismatch Stresses; 19) Thermal Stress Induced Bow and Bow-Free Adhesively Bonded or Soldered Assemblies; 20) Thermal Stress in In-homogeneously Bonded Assemblies: Could Inelastic Strains in Them Be Avoided? 21)Thermal Stress in Optical Fibers; 22) Some Other Thermal Stress Related Problems in Electronics; 23) Role of Modeling: FEA and Analytical Models; 24) Conclusion.

Biography:

Dr. Suhir is on the faculty of the Portland State University, Portland, OR, USA, and Technical University, Vienna, Austria, and is also CEO of the Small Business Innovative Research (SBIR) ERS Co. in Los Altos, CA, USA. He is Full Member of the National Academy of Engineering, Ukraine (he was born in that country); IEEE, ASME and IMAPS Life Fellow and Fellow of the American Physical Society, the Institute of Physics, UK, the Society of Optical Engineers, and the Society of Plastics Engineers, and AIAA Associate Fellow. Dr. Suhir is the third "ussian American" (after S.Timoshenko an I. Sikorsky!) who received the prestigious ASME Wocester Reaad Warner medal for outstanding contributions to the permanent literature in engineering

5:30 PM-7:30 PM
Welcome Reception

Open to all IMAPS 2018 participants

Welcome Reception Sponsored by:

 
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Cost for Each PDC: $300 (on/before 9/12/2018); $400 (after 9/12/2018)
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