Honeywell

IMAPS 2018 Pasadena

IMAPS 2018 - Pasadena
51st Symposium on Microelectronics
www.imaps2018.org

Conference:
October 9-11, 2018
Exhibition:
October 9-10, 2018
Professional Development Courses:
October 8, 2018
General Chair:
Mark Gerber
ASE US Inc.
General Chair-elect (2019):
Curtis Zwenger
Amkor Technology
Past General Chair (2017):
Dan Krueger
Honeywell FM&T

 
    PREMIER PROGRAM SPONSOR:
 
 
Premier Program Sponsor - Heraeus Materials Technology

 

    PREMIER TECHNOLOGY SPONSOR :

    PREMIER TECHNOLOGY SPONSOR :

   PREMIER TECHNOLOGY SPONSOR:
Bag Insert Sponsor: ASE Group
Premier Tech Sponsor - NGK NTK
Keynote Sponsor: SAMTEC

TECHNICAL PROGRAM
(Keynote Presentations, Sessions, Posters, and more!)

REGISTER ONLINE

For Exhibitors
     

 

Monday, October 8, 2018

Professional Development Courses (PDCs) - 8:00 AM - 5:30 PM

Monday, October 8: 2-hour formats, by theme/track
8:00 AM-10:00 AM | 10:30 AM - 12:30 PM | 1:00 PM - 3:00 PM | 3:30 PM - 5:30 PM
*Attendees can take ONE PDC during each timeslot*

  Track A:
Intro to Microelectronics Packaging
Track B:
Process and Materials
Track C:
Emerging Technologies
Track D:
Reliability
8:00 AM-10:00 AM

A1: Fundamentals of Microelectronics Packaging - PART 1 - John Pan, Cal Poly University

B1: Polymers Used in Wafer Level Packaging - Jeff Gotro, InnoCentrix

C1: Flexible Ceramics - John Olenick, ENrG Inc.

D1: Achieving High Reliability Solder Joints for Lead-Free Alloys - Dr. Ning-Cheng Lee, Indium Corporation

10:00 AM-10:30 AM
Coffee / Networking
Open to all PDC participants
10:30 AM - 12:30 PM

A2: Introduction to System in Package (SiP) - The Heterogeneous Integration Driver - Mark Gerber, ASE US, Inc.

B2: Electroplating Processes for Flip Chips - Fred Mueller Consultant, Metal Finishing Instructor

C2: Electronic Packaging for 5G Microwave and Millimeter Wave Systems - Rick Sturdivant, Ph.D., Azusa Pacific University

D2: Package/Board Level Integrity & Solder Joint Reliability - Dr. Jennie S. Hwang, Ph.D., D.Sc. H-Technologies Group

12:30 PM-1:00 PM
Lunch
Open ONLY to PDC participants taking morning AND afternoon courses
1:00 PM-3:00 PM

A3: Fan-Out Wafer/Panel-Level Packaging - John Lau, ASM

B3: Introduction to Solder Flip Chip with an Emphasis on Cu Pillar - Mark Gerber, ASE US, Inc.

C3: MEMS and nanoMEMS Packaging - Slobodan Petrovic, Oregon Institute of Technology

D3: A Methodology for Understanding the Reliability of Electronic Packaging - Greg Caswell, DfR Solutions

3:00 PM-3:30 PM
Coffee / Networking
Open to all PDC participants
3:30 PM-5:30 PM

A4: Fundamentals of Microelectronics Packaging - PART 2 - John Pan, Cal Poly University

B4: Temporary Bonding of Electronics (Wafers, Packages, Displays) - John Moore, Daetec LLC

C4: Fundamentals of 3D and 2.5D Packaging Integration - Urmi Ray, JCET Group

D4: Thermal Stress Failures in Electronic Packaging: Prediction and Prevention - Ephraim Suhir, Portland State University

5:30 PM-7:30 PM
Welcome Reception
Open to all IMAPS 2018 participants

 

Cost for Each PDC: $300 (on/before 9/12/2018); $400 (after 9/12/2018)
REGISTER ONLINE

Microelectronics/Packaging Industry Tour - 1:00 PM - 3:30 PM - (Departure approx. 12pm & Return approx. 4pm)
JET PROPULSION LABORATORY

• All US citizens 18 years of age or older visiting JPL MUST present official, government-issued photo identification, such as a driver's license or passport, before being allowed entry.
• All non-US citizens (Foreign Nationals) 18 years of age or older MUST present either a passport or resident visa (green card) before being allowed entry. Individuals without the appropriate identification will NOT be admitted to the facility.
• The tour includes considerable walking and stair climbing. Dress comfortably and appropriately for the weather. Wheelchairs can be accommodated with prior notice. Cameras are allowed on the tour. *Note: All tours are conducted in English*

 

Welcome Reception | 5:30 PM - 7:30 PM
Pasadena Convention Center

Welcome Reception Sponsored by:

 
   Premier Program Sponsor:
 
 
Heraeus Materials Technology - Premier Sponsor, Gold
 

 

 

DIVERSITY Discussion and Networking | 7:00 PM - 8:00 PM
Join IMAPS leaders for a networking discussion on diversity in IMAPS and the microelectronics industry on Monday, October 8th from 7pm-8pm just following the welcome reception. Moderators will lead a question and answer questions about overcoming diversity barriers, using your strengths in a diverse workforce, and promoting cooperation and communication in the work environment, plus additional topics. Come explore options to bridge generational, cultural, and gender communication gaps. All IMAPS attendees are invited to participate!

 


 

TUESDAY, OCTOBER 9, 2018

7:00 AM - 6:00 PM: Registration Open
11:00 AM - 5:00 PM: Exhibit Hall Open

IMAPS 2018 Opening & Plenary Session:
PASADENA CONVENTION CENTER

8:00 AM - 8:20 AM: Welcome, IMAPS Business Meeting, and more
Ron Huemoeller, Amkor Technology - IMAPS President

8:20 AM - 8:45 AM: Welcome to IMAPS 2018 & Intro of Keynotes
Mark Gerber, ASE Group - IMAPS 2018 General Chair

Keynote Session sponsored by:

8:45 AM - 9:30 AM: Keynote Presentation 1

Bridging the Gaps

The packaging industry is facing higher expectations in business enablement due to the increasing complexity of inhomogeneous integration alongside multiple dimensions of business requirements. During his keynote, Dr. Tien Wu will focus on key aspects of future packaging technologies and explore how these might open up new design concepts and business freedoms to ultimately enable better performance and efficiency at the system level.

Keynote Speaker - Tien Wu, ASE

Tien Wu, Ph.D. ASE
President & CEO

Dr Tien Wu is the President and Chief Executive Officer of Advanced Semiconductor Engineering, Inc (ASE) and concurrently the Chief Executive Officer of Universal Scientific Industrial Co (USI). Tien serves as a Board Member of the Global Semiconductor Association (GSA) and SEMI, both of which are global industry associations serving the manufacturing supply chain for the micro- and nano-electronics industries.

Prior to joining ASE, Tien held several management positions within IBM including R&D, manufacturing and sales in the United States, Europe and Asia-Pacific. He holds twelve U.S. patents and has authored over twenty-five articles. Tien holds a BSCE degree from Taiwan University, and also earned MS and Ph.D. degrees in mechanical engineering and applied mechanics respectively from the University of Pennsylvania. In 2015, Tien received an Honorary Degree of Doctor of Science from Binghamton University.

 

9:30 AM - 10:15 AM: Coffee Break in Foyer

Coffee Break Sponsor:

Break Sponsor: Geib Refining

 

 

10:15 AM - 11:00 AM: Keynote Presentation 2

Challenges and Potential Solutions in Heterogeneous Integration from a Foundry Viewpoint

A common need across computing and communication products is integration of different functions that do not integrate well on a single chip for various reasons. The cost of leading-edge integration is also become unaffordable to all but the largest volume devices. One node is not the best solution for all functions. The demand for fast access memory is causing die size to exceed reticle size. Integration of RF devices with antennas will drive 5G products. All this integration must be done at a lower cost than is available today. Multi-chip devices are needed but how will first pass design success be enabled? How will IC interfaces be enabled when they come from different suppliers? These challenges and some solutions will be discussed.

Keynote Speaker - David McCann, GLOBALFOUNDRIES

David McCann, GLOBALFOUNDRIES
Vice President, World Wide Post Fab

David McCann has been at GLOBALFOUNDRIES for seven years, where he is Vice President of Packaging R+D and Operations. He is responsible for GF’s internal bump and probe factories, for packaging and test development for GF’s Foundry, ASIC, and RF businesses, for OSAT partnerships, supply chain qualification and external bump-probe-assembly-test production. He is based at the Fab 8 site, in Malta, New York. He led the GLOBALFOUNDRIES/IBM post-fab process and business integration.

David’s background prior to GLOBALFOUNDRIES was in flip chip technology development and business management in the OSAT industry, and prior to that, flip chip assembly and product development in implantable medical electronics.

 


11:00 AM - 11:15 AM:
This Week’s Program & Future IMAPS Activities
Urmi Ray, JCET Group & IMAPS VP of Technology

 

** IMAPS 2018 EXHIBITS OPEN: 11:00 AM - 5:00 PM **

11:15 AM - 2:00 PM: Lunch Break in Exhibit Hall

Exhibit Lunch Sponsor:

Lunch Sponsor: MRSI

 

 

TUESDAY AFTERNOON PROGRAM

 

SiP/SiM (Systems Solutions)

Track Chairs:
Urmi Ray, JCET Group; Rich Rice, ASE Group

Wafer Level/Panel Level (Advanced RDL)

Track Chairs:
John Hunt, ASE Group; Rajiv Dunne, Qualcomm

High Performance-High Reliability

Track Chairs:
Erica Folk, Northrop Grumman; Ivan Ndip, Fraunhofer IZM

Flip Chip/ 2.5D/3D/Optical (Advanced Package)

Track Chairs:
Karl Friedrich Becker, Fraunhofer-IZM; Sandeep Sane, Intel

Advanced Process & Materials (Enabling Technologies)

Track Chairs:
Habib Hichri, SUSS Microtec; Benson Chan, Binghamton Univ.

 

Session TP1
SYSTEM DESIGN & INTEGRATION

Session Chairs: Venky Sundaram; Dickson Yeung, Huawei

Session TP2
ADVANCED
FAN OUT

Session Chairs: Suresh Jayaraman, Amkor Technology; Kim Yess, Brewer Science

Session TP3
HIGH RELIABILITY IN EXTREME ENVIRONMENTS

Session Chairs: Zhenzhen Shen, Baker Hughes GE; Carl Edwards, Adv Materials Innovations

Session TP4
LARGE BODY / SMALL BODY FLIP CHIP

Session Chairs: Rockwell Hsu, Cisco; Jaimal Williamson, Texas Instruments

Session TP5
SUBSTRATE TECHNOLOGY

Session Chairs: Ton Schless, Sibco; Aric Shorey, Mosaic Microsystems

2:00 pm - 2:25 pm

037
A 3D System-in-Package (SiP) for RF Application
Shihwen "Wayne" Liu, ASE Group (Chanlin Yeh, Gavin Kao, YE Yeh, Harrison Chang)

057
Upscaling panel size for Cu plating on FOPLP (Fan Out Panel Level Packaging) applications to reduce manufacturing cost
Henning Hübner, Atotech Deutschland GmbH (Christian Ohde, Dirk Ruess)

182
Converter-Level Integration for Wide Band-Gap Automotive Power Electronics
C Mark Johnson, University of Nottingham (Jordi Espina, The Thinking Pod Innovations Ltd; Behzad Ahmadi, Jingru Dai, Bassem Mouawad, Lee Empringham, Liliana De Lillo, University of Nottingham; Christina Dimarino, Virginia Tech)

030
Thin Core Substrate Large Size FCBGA Stress and Thermal Challenges and Characterization
PoHsien Sung, Advanced Semiconductor Engineering, Inc. (Ian Hu, Penny Yang, Avis Feng, Shouyi Chin, MengKai Shih, David Tarng, Marwan Wang, CP Hung)

063
A Comparison of the Cu Electromigration Behavior Between Cu Lines with 5 µm L/S Realized by Conventional Semi Additive Process (SAP) and an Innovative Excimer Laser Damascene Process
Robert Gernhardt, Fraunhofer IZM (Friedrich Müller, Karin Hauck, Fraunhofer IZM; Markus Woehrmann, Klaus-Dieter Lang, Technische University of Berlin; Habib Hichri; Markus Arendt, Suss MicroTec Photonic Systems Inc.)

2:30 pm - 2:55 pm

072
A Cross-Domain, System Planning Methodology
Bill Acito, Cadence Design Systems

052
Unlocking the full Potential of Lithography for Advanced Packaging
Jelle van der Voort, Kulicke & Soffa Liteq B.V.

163
Novel Solder Alloy with Wide Service Temperature Capability for Automotive Applications
Ning-Cheng Lee, Indium Corporation (Jie Geng, Hongwen Zhang, Francis Mutuku)

136
fcLGA Package Assembly Qualification for Mobile Applications

Mumtaz Bora, PSEMI

076
Physical and Application Characteristics of Core-Shell Conductive Materials for LTCC in 5G Technology

Richard Stephenson, SVMT LLC

3:00 pm - 3:25 pm

093
Recess in the Motherboard Architectures for Small Form Factor Systems
Tim Swettlen, Intel Corp. (Juan Landeros, Scott Mokler)

120
Advances in Temporary Bonding and Debonding Technologies for use with Wafer-Level System-in-Package (WLSiP) and Fan-Out Wafer-Level Packaging (FOWLP) Processes
Michelle Fowler, Brewer Science, Inc (John Massey, Matthew Koch, Kevin Edwards, Brewer Science, Inc; Tanja Braun, Steve Voges, Robert Germhardt, Markus Wohrmann, Fraunhofer Institute IZM)

036
Power Cycle Tests of High Temperature Ag Sinter Die-attach on Metalized Ceramic Substrate by Using Micro-heater SiC Chip
Dongjin Kim, The Institute of Scientific and Industrial Research, Osaka University (Shijo Nagao, Aiji Suetake, Katsuaki Suganuma, Osaka University; Naoki Wakasugi, Yamato Scientific Co., Ltd.; Yusuyuki Yamamoto, Tokuyama Co., Ltd.; Tetsu Takemasa, Senju Metal Industry Co., Ltd.)

025
Molding Recipe Study for MUF Solder Crack Improvement
Michael Shy, Advanced Semiconductor Engineering, Inc. (Scott Chen, Leander Liang, Pallas Hsu, Tim Tsai, Mason Liang)

035
The Effect of Nickel Oxide Formed in the Interface of ENEPIG Structure for Flip Chip Technology
Chuan Lung Chuang, ASE Global (Min-Fong Shu, Yi-Hsiu Tseng)


Dessert & Coffee Break in Exhibit Hall: 3:25 PM - 4:30 PM

Dessert Break Sponsor:

EMD Performance Materials - Corporate Sponsor

4:30 pm - 4:55 pm

086
Universal Connection Matrix: A Breadboard in a Package
Erik Welsh, Octavo Systems

152
Design, Materials, Process, and Fabrication of Fan-Out Panel-Level Heterogeneous Integration
John Lau, ASM Pacific Technology (Cheng-Ta Ko, Henry Yang, Curry Lin, JW Lin, YH Chen, Unimicron Technology Corp.; Ming Li, Margie Li, Penny Lo, Nelson Fan, Eric Kuah, ASM Pacific Technology; Chieh-Lin Chang, Jhih-Yuan Pan, Hsing-Hui Wu, Chia-Hung Lin, Rozalia Beica, Dow Chemical Company; Tony Chen, Iris Xu, Zhang Li, Kim Hwee Tan, Jiangyin Changdian Advanced Packaging Co., Ltd.; Cao Xi, Huawei Technologies Co. Ltd.; Sze Pei Lim, NC Lee, Indium Corp.; Mian Tao, Jeffery Lo, Ricky Lee, Hong Kong University of Science and Technology)

096
Perspectives of High-Temperature Pb-Free Bonding Materials
Hongwen Zhang, Indium Corporation (Ning-Cheng Lee)

077
Understanding Mold Compound Behavior on Flip Chip QFN Packages
Ruby Ann M. Camenforte, Texas Instruments

123
Result of High Accelerated Stress Test of Organic Substrates made by Integrated Dry Process
Tomoyuki Habu, Ushio Inc. (Shinichi Endo, Shintaro Yabu)

5:00 pm - 5:25 pm

139
System-level Trade-offs and Optimization for Data-Driven Applications
Pushkar Apte, SEMI (Tom Salmon, SEMI; Richard Rice, Mark Gerber, Patricia Macleod, ASE Inc.; Rozalia Beica, Jeff Calvert, Dow Chemical; Dave Hemker, Yezdi Dordi, Manish Ranjan, Lam Research; Suresh Ramalingam, Jaspreet Gandhi, Alireza Kaviani, Xilinx; Subhasish Mitra, Philip Wong, Vincent Lee, Mohamed M. Sabry Aly; Stanford University)

114
Ultra Fine RDL Formation using an Alternative Pattering Solution for Advanced Packaging
Habib Hichri, SUSS MicroTec Photonic Systems Inc

121
3D Printed and Additively Manufactured RoboSiC for Space, Cryogenic, Laser and Nuclear Environments
Bill Goodman, Goodman Technologies LLC

022
FCCSP IMC Growth under Reliability Stress follow Automotive Criteria
Wei-Wei "Xenia" Liu, Advanced Semiconductor Engineering (Berdy Weng, Jerry Li, CK Yeh)

020
Copper Oxidation Effect in the EMC/Cu Interfacial Adhesion Improvement for a Novel Copper Interconnection Substrate Application
Min-Fong Shu, ASE Group (Yi-Hsiu Tseng)

5:30 pm - 5:55 pm

095
Flip Chip Reliability and Intermetallic Compounds for SIP Module
Adrien Morard, SAFRAN Tech (Jean-Christophe Riou, Safran Electronics & Defense; Gabriel Pares, CEA Leti)

186
Fine Pitch(<40μm) Integration Platform for Flexible Hybrid Electronics using Fan-Out Wafer-level Packaging
Amir Hanna, University of California, Los Angeles (Arsalan Alam, Goutham Ezhilarasu, Subramanian Iyer)

138
Solder-Joint Reliability of a Radar Processor for Semi-Autonomous Driving Applications
Mollie Benson, NXP Semiconductors

006
Fluxes Effective in Suppressing Non-Wet-Open at BGA Assembly
Ning-Cheng Lee, Indium Corporation (Fengying Zhou, Fen Chen)

009
Shear Strength and Thermo-mechanical Reliability of Sintered Ag Joints Containing low CTE Non-metal Additives for Die Attach
Guangyu Fan, Indium Corporation (Christine Labarbera, Ning-Cheng Lee, Indium Corporation; Colin Clark, Rochester Institute of Technology)

 

 


 

WEDNESDAY, OCTOBER 10, 2018

7:00 AM - 7:00 PM: Registration Open
11:00 AM - 5:30 PM: Exhibit Hall Open

IMAPS 2018 Plenary Session:
PASADENA CONVENTION CENTER

8:00 AM - 8:15 AM: Day 2 Opening Comments & Intro of Keynote
Mark Gerber, ASE Group - IMAPS 2018 General Chair

Keynote Session sponsored by:

8:15 AM - 9:00 AM: KEYNOTE PRESENTATION 3

Accelerating the Digital Transformation - An Ecosystem View

This keynote will provide an overview of the industry trend that drives the networking bandwidth and performance growth, market transition to more intelligent and intent based networking solutions, and underlying technology and business drivers for highly integrated systems in silicon and package. It will also attempt to share a view on how the emergence of AI and machine learning is shaping the new wave of customer applications, its implication to compute and networking solutions, as well as why it is imperative that we leverage this new technology capability to collaborate and partner much more closely as an ecosystem to jointly tackle some of the common challenges.

Keynote Speaker - Nan Wang, Cisco

Mr. Nan Wang, Cisco Systems, Inc.
Sr. Director, Technology and Quality, Supply Chain Operations

Nan Wang has been with Cisco Systems for 17 years, where he serves as Sr. Director in the Technology and Quality organization within Cisco’s global Supply Chain Operations. He leads the Component Quality and Technology Group, with focus on strategic component technology development for next generation products across Cisco.

In recent years, his team has been focusing on the component technology innovations, such as Silicon Photonics, 2.5D/3D IC, to enable the next generation of the networking applications and accelerate the digital transformation.

 

 

WEDNESDAY MORNING PROGRAM

 

SiP/SiM (Systems Solutions)

Track Chairs:
Urmi Ray, JCET Group; Rich Rice, ASE Group

Wafer Level/Panel Level (Advanced RDL)

Track Chairs:
John Hunt, ASE Group; Rajiv Dunne, Qualcomm

High Performance-High Reliability

Track Chairs:
Erica Folk, Northrop Grumman; Ivan Ndip, Fraunhofer IZM

Flip Chip/ 2.5D/3D/Optical (Advanced Package)

Track Chairs:
Karl Friedrich Becker, Fraunhofer-IZM; Sandeep Sane, Intel

Advanced Process & Materials (Enabling Technologies)

Track Chairs:
Habib Hichri, SUSS Microtec; Benson Chan, Binghamton Univ.

 

Session WA1
CPI and MODELING

Session Chairs: Karthik Dhandapani, Qualcomm; Lei Fu, AMD

Session WA2
WAFER-LEVEL FAN OUT

Session Chairs: Eric Gongora, Enthone; Elvino Da Silveira, Rudolph Technologies

Session WA3
mm WAVE/ HIGH-SPEED PACKAGING

Session Chairs: Ken Kuang, Torrey Hills Technologies; Martin Goetz, Northrop Grumman

Session WA4
ADVANCED INTERPOSER TECHNOLOGIES

Session Chairs: Akash Agrawal, AMD; Manish Dubey, Intel

Session WA5
POLYMER MATERIALS / PROCESSES

Session Chairs: Frank Eberle, Northrop Grumman; Jeff Gotro, InnoCentrix, LLC

9:10 am - 9:35 am

055
Chip Package Interaction: Understanding of Contributing Factors in Back End of Line (BEOL) Silicon / Cu Pillar Design and Applied Process Improvements
Frank Kuechenmeister, GLOBALFOUNDRIES (Dirk Breuer, Holm Geisler, Bjoern Boehme, Kashi Vishwanath Machani, Michael Hecker, Sven Kosgalwies, Jae Kyu Cho, GLOBALFOUNDRIES; Dongming He, Xuefeng Zhang, Lily Zhao, Qualcomm Technologies)

099
Enabling Robust Copper Seed Etching for Fine Line RDL by Electroplating on a Thin PVD Seed Layer
Marvin Bernt, Applied Materials

071
5G Systems and Packaging Opportunities
Rick Sturdivant, MPT, Inc.

061
Cu Diffusion into the Glass Under Bias Temperature Stress Condition for Through Glass Vias (TGV) Applications
Hoon Kim, Corning Research and Development Corp. (Ling Cai, Albert Fahey, Rajesh Vaddi, Bin Zhu, Prantik Mazumder)

040
Smart Passivation Materials with a Microencapsulated Liquid Metal for Self-Healing Conductors in Sustainable Electronic Devices
Kunmo Chu, Samsung Advanced Institute of Technology (Byong Gwon Song, Yongsung Kim, Chang Seung Lee)

9:40 am - 10:05 am

085
System Co-Design Modeling Methodology of a High Speed (25Gbps) Multi-Rate 4-Channel Retimer: Simulation to Measurement Correlation
Tony Tang, Texas Instruments, Inc. (Bridger Wray, Rajen Murugan)

101
Enhancements to Picosecond Acoustic Metrology for application in FO-WLP Process
Johnny Dai, Rudolph Technologies (M. Mehendale, R. Mair, J. Chen, J. Tan, P. Mukundhan, C. Kim, T. Kryman)

151
Systematic Design of Ka-band Transmitter Modules using the M3-Approach
Ivan Ndip, Fraunhofer IZM (Christian Tschoban, Jacob Reyes, Brian Curran, Klaus-Dieter Lang)

080
Processing Through Glass Via (TGV) Interposers for Advanced Packaging

Charles G. Woychik, i3 Electronics, Inc. (John Lauffer, David Bajkowski, Michael Gaige, Robert Edwards, Gordon Benninger, William Wilson )

097
Fabrication of an Advanced Epoxy based Molding Compound with High Thermal Conductivity and Exceptional Mechanical Properties

Nazila Dadvand, Texas Instruments Inc. (Mina Dadvand, Polytechnique de Montreal; Georges Kipouros, Dalhousie University)


Coffee Break in Foyer: 10:05 am - 10:30 am

Coffee Break Sponsor:

Break Sponsor: Pac Tech

10:30 am - 10:55 am

094
A Systematic Approach to the Reliability Characterization of System in Package (SiP)
Karthikeyan Dhandapani, Qualcomm, Inc. (Brian Roggeman, David Rae)

028
Active Optical Magnification Correction Technology as Method for Improved Lithography Overlay Accuracy
Habib Hichri, SUSS MicroTec Photonic Systems Inc.

158
Enabling High-Performance Heterogeneous Integration via Interface Standards, IP Reuse, and Modular Design
Jeffrey Demmin, Booz Allen Hamilton

029
Bumping Process Impact on the Chip Package Interaction (CPI) Reliability
Lei Fu, Advanced Micro Devices (Milind Bhagavat, Ivor Barber)

125
Advanced Build-up Materials for High Speed Transsmission Application
Shiro Tatsumi, AJINOMOTO CO., INC.

11:00 am - 11:25 am

017
System ElectroThermal Co-Design of a Zero-Drift Current-Shunt Monitor with Precision Integrated Shunt Resistor
Jie Chen, Texas Instruments, Inc. (Rajen Murugan, Steven Kummerl, Usman Chaudhry, Edwin Lim, Tatsuhiro Shimizu, Thatcher Klumpp, Jack Grantham)

118
Customization of Chemistry Continues

Eric Gongora, Elie Najjar, MacDermid Enthone Advanced Electronic Solutions

054
Packaging and Integration Strategy for mm-Wave Products
Urmi Ray, JCET Group (NJ Cho, YC Kim, SW Yoon, WK Choi, Pandi Marimuthu, JCET Group)

172
High Frequency Base Materials: Laser-Material Interaction for HDI/ICP Applications
Christopher Ryder, ESI

129
Solderable Polymer Thick-film Conductors for Low Temperature Substrates
Gregory Berube, Heraeus Precious Metals North America

11:30 am - 11:55 am

007
Sn3.2Ag0.7Cu5.5Sb Solder Alloy with High Reliability Performance up to 175C
Ning-Cheng Lee, Indium Corporation (Jie Geng, Hongwen Zhang, Francis Mutuku)

153
Reliability of Fan-Out Wafer-Level Heterogeneous Integration
John H Lau, ASM Pacific Technology (Ming Li, Yang Lei, Margie Li, Wu Kai, Penny Lo, Y. M. Cheung, Nelson Fan, Eric Kuah,ASM Pacific Technology; Iris Xu, Tony Chen, Zhang Li, Kim Hwee Tan, Jiangyin Changdian Advanced Packaging Co., Ltd.; Qing Xiang Yong, Zhong Cheng, Cao Xi, Jiang Ran, Huawei Technologies Co. Ltd.; Rozalia Beica, Dow Chemical Company; Sze Pei Lim, N. C. Lee, Indium Corporation; C. T. Ko, Henry Yang, Y. H. Chen, Unimicron Technology Corporation; Mian Tao, Jeffery Lo, Ricky Lee, Hong Kong University of Science and Technology)

 

193
Status on 3D Stacking Using Direct Hybrid Bonding
Bruno Paing, CEA LETI (Severine Cheramy, Amandine Jouve, Lucile Arnaud)

178
Evaluation of Low Cost, High Temperature Die and Substrate Attach Materials for Silicon Carbide (SiC) Power Modules
Sayan Seal, WolfSpeed, a CREE Company (Brice McPherson, Brandon Passmore)

 

12:00 pm - 1:15 pm: Lunch in Exhibit Hall

Lunch Sponsor:

JCET Group - Supporting Technology Sponsor

 


WEDNESDAY AFTERNOON PROGRAM

 

SiP/SiM (Systems Solutions)

Track Chairs:
Urmi Ray, JCET Group; Rich Rice, ASE Group

Wafer Level/Panel Level (Advanced RDL)

Track Chairs:
John Hunt, ASE Group; Rajiv Dunne, Qualcomm

High Performance-High Reliability

Track Chairs:
Erica Folk, Northrop Grumman; Ivan Ndip, Fraunhofer IZM

Flip Chip/ 2.5D/3D/Optical (Advanced Package)

Track Chairs:
Karl Friedrich Becker, Fraunhofer-IZM; Sandeep Sane, Intel

Advanced Process & Materials (Enabling Technologies)

Track Chairs:
Habib Hichri, SUSS Microtec; Benson Chan, Binghamton Univ.

 

Session WP1
EMBEDDED & HIGH DENSITY

Session Chairs: Trevor Yancey, TechSearch International; Mak Kulkarni, Texas Instruments

Session WP2 PANEL-LEVEL FAN OUT

Session Chairs: Markus Wöhrmann, Fraunhofer IZM; Linda Bal, TechSearch International

Session WP3
RF/WIRELESS COMPONENTS

Session Chairs: Ivan Ndip, Fraunhofer IZM; Ege Engin, San Diego State University

Session WP4
OPTICAL and ENABLING TECHNOLOGIES

Session Chairs: Kevin Demartini, DuPont; Jim Will, Honeywell FM&T

Session WP5
NOVEL MATERIALS / PROCESSES

Session Chairs: Florian Herrault, HRL Laboratories; W. Hong Yeo, Georgia Tech

1:15 pm - 1:40 pm

083
Increase Power Density and Simplify Designs Using 3-D SiP Modules
Steven Kummerl, Texas Instruments (Charles Devries, Usman Chaudhry, Chong Han Lim)

089
Fine Line Panel Level Fan Out changes the SiP Landscape
David Fang, Powertech Technology Inc. (Michael Hsu, CC Chang, KW Chung, Alex Liu, Irving Lin, Daniel Fann)

141
Low-fire Processing and Dielectric Properties of a Binary Crystallizable Glasses+alumina System

Jau-Ho Jean, National Tsing Hua University (Shih-An Tung)

019
Design of Solder Connections for Self-Assembly of Optoelectronic Devices
Thomas Marinis, Charles Stark Draper Laboratory (Joseph Soucy)

111
Reliability of Novel Ceramic Encapsulation Materials for Electronic Packaging
Stefan Kaessner, Robert Bosch GmbH (M. Scheibel, Heraeus Deutschland GmbH & Co. KG; S. Behrendt, Forschungs- und Entwicklungszentrum FH Kiel GmbH; B. Boettge, Fraunhofer IMWS; K. G. Nickel, University of Tuebingen)

1:45 pm - 2:10 pm

117
Design and Demonstration of Glass Panel Embedding for 3D System Packages for Heterogeneous Integration Applications
Siddharth Ravichandran, 3D Systems Packaging Research Center, Georgia Institute of Technology (Fuhan Liu, Vanessa Smet, Venky Sundaram, Rao Tummala, Georgia Tech.; Shuhei Yamada, Murata Manufacturing Co., Ltd.; Tomonori Ogawa, Asahi Glass Company)

164
Integrating a Low Cure Dielectric Material into Panel and Wafer Level Manufacturing Process
Markus Woehrmann, Fraunhofer IZM - Department WLSI

116
Mixed-Mode Hybrid Parameters for High-Speed Differential Lines

A. Ege Engin, San Diego State University (Ivan Ndip, Klaus-Dieter Lang, Fraunhofer Institut IZM; Jerry Aguirre, Kyocera North America)

098
Reversed Pulse Plating of Silver-Cobalt for Connector Applications

Nazila Dadvand, Texas Instruments Inc. (Mina Dadvand, Polytechnique de Montreal; Georges Kipouros, Dalhousie University)

082
Synthesis, Characterization, and Processing of Novel Metallic Core-Shell Materials for Thick-Film Applications
Kyle Bandaccari, SVMT LLC

2:15 pm - 2:40 pm

003
Reliability of an Electronic Product Fabricated of Mass-Produced Components
Ephraim Suhir, Portland State University

148
A Numerical Study on Mitigation of Flying Dies in Compression Molding of Microelectronic Packages
Marc Dreissigacker, TU Berlin

142
Integration of a K-Band Receiver Front-End Using a Copper Core Printed Circuit Board
Brian Curran, Fraunhofer IZM (Jacob Reyes, Christian Tschoban, Ivan Ndip, Klaus-Dieter Lang)

087
X-Ray Advances in Support of Advanced Packaging - Today and Tomorrow
David Bernard, David Bernard Consultancy

185
High Reliable and High Bonding Strength of Silver Sintered Joints on Copper Surfaces by Pressure Sintering Under Air Atmosphere
Ly May Chew, Heraeus Deutschland GmbH & Co. KG (Wolfgang Schmitt)

2:45 pm - 3:10 pm

133
Warpage Behaviors of System-in-Packages on a Substrate Strip

Eric Ouyang, STATS ChipPAC Inc (Billy Ahn, SeonMo Gu, Yonghyuk Jeong, JaeMyong Kim; STATS ChipPAC Korea; Jim Hsu, Susan Lin, Goran Liu, Anthony Yang, CoreTech System (Moldex3D))

068
Lithographic Evaluation of Thin Photoimageable Dielectric Dry Film for Advanced Panel Level Packaging Applications
Roger McCleary, Rudolph Technologies (Keith Best, Sudmun Habib, Rudolph Technologies; Ognian Dimov, Sanjay Malik, Fujifilm Electronic Materials, U.S.A.)

145
A Reusable 3D Printed Cavity Resonator for Liquid Sample Characterization
Saranraj Karuppuswami, Michigan State University (Saikat Mondal, Mohd Ifwat Mohd Ghazali, Premjeet Chahal)

034
The Low Dk and Df Photosensitive Insulation Material for Low Transmission Loss Packages
Shinichiro Abe, Hitachi Chemical Co. Ltd. (Kazuyuki Mitsukura, Yuki Imazu, Masaya Toba, Takashi Masuko, Kazuhiko Kurafuchi)

109
Study on High Temperature Resistant Die Bonding Formed by Al/Ni Nano-particles Composite Paste
Yasunori Tanaka, Waseda University

3:15 pm - 3:40 pm

 

 

194
Dielectric Constant and Loss Tangent Characterization of Alumina Substrate Using Cavity Resonators

Robert B. Paul, San Diego State University (A. Ege Engin, SDSU; Jerry Aguirre, Kyocera North America)

169
Ribbon Ceramic
John Olenick ENrG Incorporated

066
Zinc Oxide Nanowire Sensor Packaging

Bruce Kim, City University of New York (Sang-Bock Cho, Ulsan University)


3:45 pm - 5:30 pm: Happy Hour in Exhibits

Exhibit Lunch Sponsor:

Premier Program Sponsor - Heraeus Materials Technology

 




Panel Session Sponsor:

JCET Group - Supporting Technology Sponsor

PASADENA CONVENTION CENTER
5:30 pm - 7:30 pm: 

Panel Session & Reception on:
ELIMINATING THE AI CONFUSION -
IMPACT ON COMPUTING, COMMUNICATIONS, AND AUTOMOTIVE

Artificial Intelligence (AI) makes it possible for machines to learn from experience, adjust to new inputs and perform human-like tasks. The term “deep learning” or a type of “machine learning” refers to training a computer to perform human-like tasks, such as recognizing speech, identifying images or making predictions. Instead of organizing data to run through predefined equations, deep learning establishes basic parameters about the data and trains the computer to learn on its own by recognizing patterns using many layers of processing. AI or deep learning is expected to be applied to a wide range of applications, including connectivity or Internet of Things (IoT), big data processing and servers, cloud services, autonomous driving, 5G communications, smart factory or Industry 4.0, robotics, AR/VR, cryptocurrency mining, and blockchain.

This panel discussion focuses on the impact of AI on computing, communications, and automotive. The experts on the panel will comment on their understanding of the application of AI and the impact on packaging and assembly. Package choice, design, and materials impact and the importance of co-design will be discussed. A set of experts will address these issues and others in a dynamic discussion setting.

MODERATOR:
Jan Vardaman, President and Founder of TechSearch International, Inc.

PANELISTS:
Ivor Barber - AMD
Aravind Dasu - Intel's Programmable Solutions Group
Rama Divakaruni - IBM
Ron Huemoeller - Amkor Technology
David McCann - GLOBALFOUNDRIES
Raj Pendse - Facebook
Urmi Ray - JCET Group
TBD - ASE

Includes Beer, Wine and Appetizers



 


 

THURSDAY, OCTOBER 11, 2018

7:00 AM - 3:00 PM: Registration Open
NO EXHIBITS - Exhibitor Move-Out

 

IMAPS 2018 Plenary Session:
PASADENA CONVENTION CENTER

8:00 AM - 8:15 AM: Day 3 Opening Comments & Intro of Keynote
Mark Gerber, 2018 General Chair; Curtis Zwenger, General Chair-Elect (2019)

Keynote Session sponsored by:


8:15 AM - 9:00 AM: Keynote Presentation 4

AI Hardware: Packaging to the Core!

AI workloads are strongly driving systems to become much more architecturally diverse. Today's accelerators are composed of a mix of heterogeneous components including CPUs, GPUs, specialized accelerators, and memories. Advanced packaging techniques to enable high inter-connectivity among these components will be crucial for continued progress in AI as this is the key bottleneck for AI Applications. As scaling continues to slow, value at the system level for today's workloads is achieved more by a diversity of parts, connectivity and bandwidth rather than sheer compute power in a monolithically integrated SoC.

Continued increases in compute performance for modern unstructured data will drive technologies for higher bandwidth including but not limited to 3D stacking. While research has explored advanced cooling techniques -- which are viable in a modern data center -- a plethora of form factors which will evolve for different AI workloads and is expected to color the landscape. With the advent of analog-based accelerators --also currently in a research phase - it becomes clear to envision a future where a variety of heterogeneously enabled form factors driving different workloads for inference and training are pervasive in the edge and in the Cloud.

Thus, AI hardware will be truly packaging to the core!

Keynote Speaker - Rama Divakaruni, IBM

Rama Divakaruni, IBM
IBM Distinguished Engineer

Rama Divakaruni received his B.Tech in Electrical Engineering from the Indian Institute of Technology, Madras, India in 1988. He received his Ph.D in Electrical Engineering from the University of California, Los Angeles in 1994. Since 1994, he has been working on advanced semiconductor technologies at IBM. From 1994 through 2003, he worked on DRAM Technology Development and his team introduced the world's first sub-8F2 vertical transistor DRAM trench technology. From 2004 through 2008 he worked on various strained silicon technologies in both SOI and bulk Si semiconductors. These technologies were the basis of the Nintento Wii, XBOX360 and the PlayStation3 game platforms and at 45nm were introduced into the modern mobile semiconductor fabric. From 2008 through 2013, Dr. Divakaruni worked on IBM's unique Hi-K technologies and FINFET technologies. Much of this work culminated with the introduction of mobile technologies by IBM's partners and IBM's SUMMIT Supercomputer earlier this year using 14nm SOI FINFET technology.

Dr. Divakaruni is currently an IBM Distinguished Engineer and is reponsible for IBM Advanced Process Technology Research. His current focus is on AI Hardware technologies for Deep Learning. He is one of IBMs top inventors with over 225+ issued US patents.

 

 

THURSDAY MORNING PROGRAM

 

SiP/SiM (Systems Solutions)

Track Chairs:
Urmi Ray, JCET Group; Rich Rice, ASE Group

Wafer Level/Panel Level (Advanced RDL)

Track Chairs:
John Hunt, ASE Group; Rajiv Dunne, Qualcomm

High Performance-High Reliability

Track Chairs:
Erica Folk, Northrop Grumman; Ivan Ndip, Fraunhofer IZM

Flip Chip/ 2.5D/3D/Optical (Advanced Package)

Track Chairs:
Karl Friedrich Becker, Fraunhofer-IZM; Sandeep Sane, Intel

Advanced Process & Materials (Enabling Technologies)

Track Chairs:
Habib Hichri, SUSS Microtec; Benson Chan, Binghamton Univ.

 

Session THA1
AUTOMOTIVE

Session Chairs: Mark Hoffmeyer, IBM; Rich Rice, ASE Group

Session THA2
WLCSP / WAFER-LEVEL FAN OUT

Session Chairs: Farhad Kiaei, HD MicroSystems; Paul Tiner, Texas Instruments

Session THA3
HIGH RELIABILITY IN BIOMEDICAL

Session Chairs: Tim LeClair; Cerapax; Julia Brueckner, Quantum Analytics

Session THA4
BUMP/
INTERCONNECT

Session Chairs: Adeel Bajwa, UCLA; Karl Friedrich Becker, Fraunhofer-IZM

Session THA5
ADVANCED WIREBOND

Session Chairs: Martin Schneider-Ramelow, Fraunhofer IZM; Michael McKeown, Hesse Mechatronics

9:10 am - 9:35 am

060
Advanced Packaging for Automotive Dashboard Application
Nokibul Islam, JCET Group (HC Choi)

039
Photosensitive Polyimide having Low Loss Tangent for RF Application

Masao Tomikawa, Toray Industries (Hitoshi Araki, Yohei Kiuchi, Akira Shimada)

112
When Failure is Not an Option - Packaging Materials and Technologies for the Reliable Protection of Medical Electronics
Thomas Zetterer, SCHOTT AG (J. Herzberg, J. Baehr, K. Waxman, Jochen Herzberg)

107
Fine Pitch Paste for System-in-Package Applications
Zhang Ruifen, Heraeus Materials Singapore Pte Ltd

105
Ultra-Fine Pitch Wedge bonding for Device Reliability Characterization

Lacey Badger, Intel Corporation

9:40 am - 10:05 am

023
Batch Microwave Plasma Cleaning for Robustification of Automotive Devices: an Alternative to Strip-type Radiofrequency Plasma
Ghizelle Jane E. Abarro, ON Semiconductor Philippines Inc. (Rod Delos Santos Jr., Alvin Denoyo, Manny Ramos)

137
Novel Low Temperature Curable Photo-patternable Polyamide with High Planarity for Wafer Level Fan-Out Packaging (WLFO)

Daniel Nawrocki, MicroChem Corp / Nippon Kayaku (Andrew Cooper, Takanori Koizumi, Shinya Inagaki, Naoki Kawamoto, Nao Honda, Kristina Markt, Milton Bernal)

162
Sequence-Specific Nucleic Acid Detection at 1 aM; Microfluidics Device
Harold G. Monbouquette, University of California, Los Angeles

012
Elevated Stand-Off Heights in Solder Joint Interconnections of Surface Mounted IC Packages Result in Appreciable Stress and Warpage Relief
Ephraim Suhir, Portland State University (Sung Yi, Portland State University; Jennie Hwang, H-Technologies Group; R. Ghaffarian, Jet Propulsion Laboratory, California Institute of Technology)

108
Process Development of Al-alloy Wire Bonding for High-Temperature Power Electronics

Omid Niayesh, Kulicke & Soffa Industries, Inc. (Tao Xu, Xuan Che, Jason Fu)

Coffee Break in Foyer: 10:05 am - 10:20 am

Coffee Break Sponsor:

Coffee Break Sponsor: ORS Oneida Research Services & Silicon Cert Labs

Oneida Research Services &
Silicon Cert Labs

10:20 am - 10:45 am

033
A New Photosensitive Dielectric Material for High-Density RDL with Ultra-Small Photo-Vias and High Reliability
Daichi Okamoto, TAIYO INK MFG. CO. (Yoko Shibasaki, Daisuke Shibata, Tadahiko Hanada)

103
Study of Sub-micron Fan-out Wafer Level Packaging Solutions

Yoshio Goto, Canon (Kosuke Urushihara, Bunsuke Takeshita, Ken-Ichiro Mori)

170
Glass Encapsulation for Wireless Highly Miniaturized Implantable Devices
Jim Ohneck, GlencaTec AG

070
Fatigue Cycling of Electrical Interconnects Dispensed on Flexible Substrate

Mohammed Alhendi, Binghamton University (J.P. Lombardi III, G. S. Khinda, M.Z. Kokash, D. L. Weerawarne, P. Borgesen, M. D. Poliks)

113
Intelligent Production of Wire Bonds using Multi-Objective Optimization – Insights, Opportunities and Challenges
Michael McKeown, Hesse Mechatronics (Andreas Unger, Matthias Hunstig, Michael Brökelmann, Hesse GmbH; Tobias Meyer, Fraunhofer IWES; Walter Sextro, Paderborn University)

10:50 am - 11:15 am

079
Inspection and Metrology of Wet Print
Sebastian Stenger, EPP Germany

092
Implementation of a Temperature Ramp Rate Requirement and Impact on the Packaging Processes
Randy Hamm, Honeywell KCP (Daren Withlock, Elizabeth Brown, Ryan Eatinger, Honeywell KCP; Jeremy Stearns, Samuel Ringwood, Sandia National Laboratories)

100
Flexible PET Substrate for Higher Definition Printing of Polymer Thick Film Conductive Pastes
Art Dobie, Ikonics/Chromaline

165
Analysis of Ultrasonic Welding of Mechanically Coupled Small Area Contacts for a Silicon Carbide Power Module
Kuldeep Saxena, CREE (Aryn Hays, Ivan Kao, Zach Cole)

106
Growth of Intermetallics at Coated Silver Wire Bond Interfaces

Sarangapani Murali, Heraeus Materials Singapore Pte Ltd

11:20 am - 11:45 am

154
Highly Reliable Solderless Contact with Press-fit Technology for Power Modules
Minoru Egusa, Mitsubishi Electric Corporation (Hidetoshi Ishibashi, Yoshitaka Otsubo, Masao Kikuchi, Mitsubishi Electric Corporation; Yoshihiro Kashiba, Osaka University)

192
Novel Low Temperature Curable Photosensitive Negative-tone PI with Higher Resolution and Reliability
Daisaku Matsukawa, Hitachi Chemical DuPont MicroSystems, Ltd. (Hiroko Yotsuyanagi, Shiori Sakakibara, Noriyuki Yamazaki, Tetsuya Enomoto, Takeharu Motobe)

SOON

187
Characterization of Fine Pitch Interconnections (<=10µm) on Silicon Interconnect Fabric for Heterogeneous Integration
SivaChandra Jangam, University of California, Los Angeles (Adeel Bajwa, Kannan K. Thankappan, Premsagar Kittur, Subramanian Iyer)

168
Wire Bonding Advances for Multi-Chip and System in Package Devices
Hui Xu, Kulicke and Soffa Industries, Inc. (Aashish Shah, Basil Milton, Ivy Qin)

 

11:45 am - 1:15 pm: 
POSTERS & PIZZA
(in Foyer)
Session Chairs: Erica Folk, Northrop Grumman; Andre Rouzaud, CEA Leti; Gabriel Pares, CEA Leti

(POSTER SETUP FROM 10:30 AM UNTIL 11:40 AM)

Posters & Pizza Sponsored by:

021
Comparisons of Soldering Alloys in Large Ceramic Substrate to Metal Heatsink Attachment Application
Frank Fan Wang, Crane Aerospace & Electronics

011
A New Method for Non-Destructive Characterization of Through Holes in Printed Circuit Boards
Sarah Czaplewski, IBM (Joe Doman, Joe Kuczynski)

056
Microstrucuture and Mechanical Properties of Pressureless Sintered Silver Die-attach Materials
Masafumi Takesue, Bando Chemical Industries (Tomofumi Watanabe, Keisuke Tanaka)

069
Investigation Towards the Optimum of Power Capability, Ageing Stability and Costs Effectiveness on Thick Film Resistor Pastes for AlN Ceramics
Richard Schmidt, Fraunhofer Institute for Ceramic Technologies and Systems

081
Thermal Shrinkage Management of Silver Core-shell Conductive Layers with A6 and L8 LTCC Architectures
Richard Stephenson, SVMT LLC

128
Aqueous Washable Thermal Resistant Coatings and Adhesives
John Moore, Daetec LLC

130
High Performance Etchable RoHS Compliant Thick Film Gold Conductor
Gregory Berube, Heraeus Precious Metals (Samson Shahbazi, Stephanie Edwards, Ryan Persons, Caitlin Shahbazi)

140
Novel Formaldehyde-free Electroless Copper for Plating on Next Generation Substrates
Christian Wendeln, Atotech Deutschland GmbH

161
Low-temperature Sintering IMC-nano-solder for High Temperature Interconnect
Ying Zhong, University of California at San Diego

146
Investigation of a Proactive Glass Filler Removal in IC Substrate Build up Films and its Effect on Topography and Copper Adhesion Reliability
Stefan Kempa, Atotech Deutschland GmbH

078
Development of a Mechanical Cycling Reliability Test Program for Evaluating Thermal Interface Materials for Semiconductor Test and Burn-in Requirements
David Saums, DS&A LLC (Tim Jensen, Carol Gowans, Seth Homer, Ron Hunadi, Indium Corporation)

173
Optimization of Cupric Chloride Subtractive Etching for Cu High Density Interconnects
Oliver Chyan, University of North Texas (Alexander Lambert, Goutham Issac, Ashish Salunke, Luwen Lu, University of North Texas; Oscar Ojeda, Jeremy Ecton, Arnab Roy, Hsin-Wei Wang, Leonel Arana, Intel)

183
Explore High Bonding Reliability of Cu Wire Bonded Devices under Extreme Halide Contaminated Environments
Oliver Chyan, University of North Texas (M. Asokan, J. Caperton, A. Salunke, University of North Texas, Interfacial Electrochemistry and Materials Research Lab; Fei Xu, Changzhou Ruize Microelectronics Co., Ltd.)

176
Development of High Temperature Tantalum Polymer Capacitors
Antony P. Chacko, KEMET Electronics Corporation (James Chen, Chris Stolarski, Cristina MotaCaetano, Philip Lessner)

181
Development of skills and tools for micro opto-electrical integration on wafer level
Saskia Schröder, Fraunhofer Institute for Silicon Technology (Vanessa Stenchly, Hans-Joachim Quenzer, Wolfgang Reinert)

188
A Network for Silicon Interconnect Fabric
Boris Vaisband, University of California, Los Angeles (Adeel Bajwa, Subramanian Iyer)

189
Dynamically Controlled Flow Loop to Benchmark Rapid Transient Cooling Utilizing Flash Boiling for High Heat Flux Electronic Systems
Ujash Shah, University of California, Los Angeles (Chen Ling, Timothy Fisher)

190
Integrated Sensor Nodes for Industry 4.0 Applications
P. Fruehauf, Fraunhofer IZM (M. Heimann, S. Nerreter, R. Blank, S. Gottwald, A. Hofmeister, M. Schmied, D. Schütze, B. Schröder, S. Voges, K.-F. Becker, M. Kreitmeier, W. Neifer)

191
Application of Portable Nanogenerator Using Friction Charging
Dongseob Kim, KITECH (Banseok Kim, Jihoon Chung, Haksung Moon, Sangmin Lee, Chung-Ang University)

 

 

**ALSO IN SESSION WA4**
172
High Frequency Base Materials: Laser-Material Interaction for HDI/ICP Applications
Christopher Ryder, ESI

**ALSO IN SESSION TP5**
009
Shear Strength and Thermo-mechanical Reliability of Sintered Ag Joints Containing low CTE Non-metal Additives for Die Attach
Guangyu Fan, Indium Corporation (Christine Labarbera, Ning-Cheng Lee, Indium Corporation; Colin Clark, Rochester Institute of Technology)


 

THURSDAY AFTERNOON PROGRAM

 

SiP/SiM (Systems Solutions)

Track Chairs:
Urmi Ray, JCET Group; Rich Rice, ASE Group

Wafer Level/Panel Level (Advanced RDL)

Track Chairs:
John Hunt, ASE Group; Rajiv Dunne, Qualcomm

High Performance-High Reliability

Track Chairs:
Erica Folk, Northrop Grumman; Ivan Ndip, Fraunhofer IZM

Flip Chip/ 2.5D/3D/Optical (Advanced Package)

Track Chairs:
Karl Friedrich Becker, Fraunhofer-IZM; Sandeep Sane, Intel

Advanced Process & Materials (Enabling Technologies)

Track Chairs:
Habib Hichri, SUSS Microtec; Benson Chan, Binghamton Univ.

 

Session THP1
WEARABLE /
TEST

Session Chairs: Urmi Ray, JCET Group; Curtis Zwenger, Amkor Technology

Session THP2
MEMS & SENSORS

Session Chairs: Gabriel Pares, CEA-LETI; Marco Del Sarto, ST Microelectronics

Session THP3
HIGH RELIABILITY IN DEFENSE and AEROSPACE

Session Chairs: Erica Folk, Northrop Grumman; Daniel Fisher, GLOBAL FOUNDRIES

Session THP4
3D & ENABLING TECHNOLOGIES

Session Chairs: Nokibul Islam, JCET Group;

Session THP5
ADVANCED EQUIPMENT /ADDITIVE MANUFACTURING

Session Chairs: Doug Shelton, Canon USA; Douglas Hopkins, NC State University

1:15 pm - 1:40 pm

Latest Packaging Developments in Wearable Electronics
Jan Vardaman, TechSearch International, Inc.

160
Scalable Hybrid Microelectronic-Microfluidic Integration of Highly Sensitive Biosensors for Point of Care Applications

Karl-Friedrich Becker, Fraunhofer IZM (Patrick Reinecke, Tanja Braun, Martin Schneider-Ramelow, Klaus-Dieter Lang, Technical University of Berlin; Marie-Theres Putze, Leopold Georgi, Ruben Kahle, Fraunhofer IZM; David Kaiser, Daniel Hüger, Andrey Turchanin, Friedrich Schiller University; Pavel Livshits, Jens Weidenmüller, Fraunhofer IMS; Thomas Weimann, Physikalisch-Technische Bundesanstalt)

018
The Impact of PWB Glass Style and Orientation on the Reliability of SMT Components
Maxim Serebreni, DfR Solutions (Greg Caswell)

053
3D Integration: 300mm MOCVD Copper Seed Layer Deposition for High Aspect Ratios TSV
Sabrina Fadloun, SPTS Technologies

047
Productivity Comparison of Wafer Transport Architectures in PVD Tools Used for Fan-Out Packaging RDL Barrier/Seed Formation
Paul Werbaneth, Intevac, Inc. (Terry Bluck, Chris Smith)

1:45 pm - 2:10 pm

008
Smart and Connected Bioelectronics for Persistent Human-Machine Interfaces
Woon-Hong Yeo, Georgia Institute of Technology (Yun-Soung Kim)

132
Glass Packaging for RF MEMS
Raj Parmar, Corning Inc. (Aric Shorey, Jay Zhang, Corning Inc.; Chris Keimel, Menlo Microsystems)

065
Reliability & Characterization of Wide Band Gap Power Modules using POL-kW Packaging Technology
Christopher Kapusta, General Electric

149
Electrical Characterization of Low Temperature PECVD Oxides for TSV Applications
Piotr Mackowiak, Fraunhofer IZM (Rachid Abdallah, Martin Wilke, Klaus-Dieter Lang, Martin Schneider-Ramelow, Ha-Duong Ngo, Fraunhofer IZM; Jash Patel, Huma Ashraf, Keith Buchanan, SPTS Technologies)

075
Ultra-Wideband High Gain Vivaldi Antennas Using Additive Manufacturing

Mohd Ifwat Mohd Ghazali, Michigan State University (Premjeet Chahal)

2:15 pm - 2:40 pm

115
The Evolution of a Clinical Grade Wearable Vital Signs Monitor and the Role of Advanced Microelectronic Packaging Techniques to Increase Functionality

Jim Ohneck, AEMtec

091
Electrochemical Capacitance based Method Applied to Epoxy Molded Devices
Paolo Rolandi, STMicroelectronics (Luca Magagnin, Politecnico di Milano; Carlo Valzasina, Daniele De Pascalis, Alessandro Tocchio, Audrey Betty Marie Garnier, Giuseppe Filoni, Francesco Pecchia, STMicroelectronics)

171
Laser Power Supply Thermo-Structural Analysis for the Mars 2020 Rover
Juan Cepeda-Rizo, Jet Propulsion Laboratory, NASA / Californian Institute of Technology (David Tuman)

032
High Performance EMI Shielding Materials and Spraying Process Parameters for High Frequency FCBGA Application

Kisu Joo, Ntrium Incorporation (Kyu Jae Lee, Jung Woo Hwang, Jin-Ho Yoon, Yoon-Hyun Kim, Se Young Jeong)

059
Laser Bonding - a Novel Solution for Numerous Application Challenges

Dominic Sha, F&K DELVOTEC GmbH

2:45 pm - 3:10 pm

015
Screen Printing Fine Pitch Stretchable Silver Inks onto a Flexible Substrate for Wearable Application
Jianbiao Pan, CalPoly

067
Assessment of Wave-Guided Ultrasonic Transducer System for Erosion-Corrosion Detection in Nuclear Applications
Aparna Aravelli, Florida International University (Dwayne McDaniel, Clarice Davila)

174
RF Test Article Experiment on the Impact of Non-Hexavalent Chromium-Based Conversion Coatings on Electrical Assemblies
Josh Petko, Northrop Grumman Corporation

122
Applicability of Selective Laser Reflow for Thin Die Stacking
Luke Arthur Wentlent, Universal Instruments Corp. (James Wilcox, Universal Instruments Corp.; Mohammed Genanu, Binghamton University)

179
Additive Manufacturing for Multi-chip Modules

Zhenzhen Shen, Baker Hughes GE (Aleksey Reiderman)

 


Register Online

 

 

 

 


PREMIER Sponsors:

 

    Premier Program Sponsor:
Premier Program Sponsor - Heraeus Materials Technology

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    Premier Technology Sponsor:
Bag Insert Sponsor: ASE Group
Premier Tech Sponsor - NGK NTK
Keynote Sponsor: SAMTEC
Event Sponsors:

Supporting Technology Sponsor:

JCET Group - Supporting Technology Sponsor

Networking Sponsor:

EMD Performance Materials - Corporate Sponsor

Exhibit Lunch Sponsor:

Lunch Sponsor: MRSI

Posters & Pizza Sponsor:

Northrop Grumman EC - Poster Session Sponsor

Keynote/Plenary Sponsor:

Student Programs Sponsor:

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Coffee Break Sponsor:

Break Sponsor: Geib Refining

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Break Sponsor: Pac Tech

Coffee Break Sponsor:

Coffee Break Sponsor: ORS Oneida Research Services & Silicon Cert Labs

Bag Insert Sponsor:

Bag Insert Sponsor: NorCom Systems

Supporting Sponsor:

American Elements, global manufacturer of high purity metals, semiconductors, nanomaterials, sputtering targets & evaporation materials for optoelectronics, sensors, thin films, MEMS devices & Microelectronics Materials

     
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Media Sponsor: MEPTEC
Media Sponsor: Webcom - Electronics Protection
Media Sponsor: US Tech

 




CORPORATE PREMIER MEMBERS
  • Amkor
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