KemLab

IMAPS 2019 Boston

Conference:
October 1-3, 2019
Exhibition:
October 1-2, 2019
Professional Development Courses:
September 30, 2019
SiP / SiM / CPI
(System Solutions)
Wafer Level /
Panel Level (Advanced RDL)
High Performance /
High Reliability
Advanced Package
(Flip Chip, 2.5D, 3D, Optical)
Advanced Process & Materials (Enabling Technologies)
General Chair:
Curtis Zwenger
Amkor Technology
General Chair-elect (2020):
Habib Hichri
SUSS Microtec
Past General Chair (2018):
Mark Gerber
ASE US Inc.

Professional Development Courses
(PDCs / Short Courses / Tutorials)

 

 

Monday, September 30: 2-hour formats, by theme/track
8:00 AM-10:00 AM | 10:30 AM - 12:30 PM | 1:00 PM - 3:00 PM | 3:30 PM - 5:30 PM
*Attendees can take ONE PDC during each timeslot*

  Track A:
Wire Bonding & Flip Chip
Track B:
Failure Analysis & Thermal
Track C:
Packaging Integration & Design
Track D:
Heterogeneous Integration & Fan Out

8:00 AM - 10:00 AM

Hynes Convention Center - ROOM 201

A1: Understanding the Wire Bonding Process - Lee Levine, Process Solutions Consulting, Inc.

Hynes Convention Center - ROOM 202

B1: Introduction to Failure Analysis in Semiconductor Package Assembly - Tom Dory, Fujifilm Electronic Materials USA

Hynes Convention Center - ROOM 203

C1: Passive Components and Integration for High-Bandwidth Computing and Communication - P M Raj, Florida International University/Georgia Tech PRC

Hynes Convention Center - ROOM 204

D1: Fan-Out Wafer/Panel-Level Packaging - John Lau, Unimicron Technology Corporation

10:00 AM-10:30 AM

Coffee / Networking
Open to all PDC participants

10:30 AM - 12:30 PM

 

Hynes Convention Center - ROOM 201

A2: Introduction to Solder Flip Chip with an Emphasis on Cu Pillar - Mark Gerber, ASE US, Inc.

Hynes Convention Center - ROOM 202

B2: Thermal and Dynamic Stress Failures in Electronic and Photonic Packaging: Prediction and Prevention - Ephraim Suhir, Portland State University

C2: Achieving High Reliability for Lead-Free Solder Joints - Materials Consideration - CANCELLED

Hynes Convention Center - ROOM 204

D2: Evolution to Advanced Fan Out - John Hunt, ASE US Inc

12:30 PM - 1:00 PM

Lunch
Open ONLY to PDC participants taking morning AND afternoon courses

1:00 PM - 3:00 PM

Hynes Convention Center - ROOM 201

A3: Flip Chip Package Technology and Assembly Processes - Tom Dory, Fujifilm Electronic Materials USA

Hynes Convention Center - ROOM 202

B3: Preventing Product Failure - Jennie Hwang, H-Technologies Group

Hynes Convention Center - ROOM 203

C3: Fundamentals of 3D and 2.5D Packaging Integration - Urmi Ray, Consultant

Hynes Convention Center - ROOM 204

D3: Heterogeneous Integrations - John Lau, Unimicron Technology Corporation

3:00 PM - 3:30 PM

Coffee / Networking
Open to all PDC participants

3:30 PM - 5:30 PM

Hynes Convention Center - ROOM 201

A4: Understanding the Role of Intermetallic Formation in Gold and Copper Wire Bonding - Lee Levine, Process Solutions Consulting, Inc.

Hynes Convention Center - ROOM 202

B4: Thermal Management using Thermal Interface - Rita Mohanty, Henkel Corporation

Hynes Convention Center - ROOM 203

C4: 5G/mmWave Package Development Requirements and Solutions - Urmi Ray, Consultant

Hynes Convention Center - ROOM 204

D4: Introduction to System in Package (SiP) - The Heterogeneous Integration Driver - Mark Gerber, ASE US, Inc.

5:30 PM-7:00 PM

Welcome Reception
Open to all IMAPS 2019 participants

Hynes Convention Center - 3RD FLOOR Boylston Hallway

 

Cost for Each PDC: $325 (on/before 8/29/2019); $425 (after 8/29/2019)

 

Get off line and learn face to tace...sign up for a PDC!

PDCs (Professional Development Course) are a big part of the Annual IMAPS Symposium each year. Why not plan to take a course on Monday before IMAPS 2019 kicks off and take advantage of the rich learning opportunities available at the IMAPS symposium.

PDCs are all now scheduled for 2-hour lessons. Shorter courses for you to digest great information without being overwhelmed by a 4 or 8 hour commitments after your travels! The shorter tutorials also allow for you to participate in more topical areas and learn from a variety of instructors! The courses are also now arranged under 4 "TRACK" categories: Track A: Wire Bonding & Flip Chip; Track B: Failure Analysis & Thermal; Track C: Packaging Integration & Design; and Track D: Heterogeneous Integration & Fan Out.

PDCs create a unique environment whereby students can personally interact with the instructors, and with each other in the classroom and over lunch. It's mentally stimulating and the new found professional connections will prove to be valuable in the long run. Learning on line is fine, but it cannot duplicate hours spent immersed in a specific topic, led by an industry expert in the field and surrounded by like-minded professionals.

This year we've put together another impressive assortment course options. Our goal is to make the IMAPS PDCs the premier learning experience; so we ask that you take time to fill out the evaluation form that accompanies each course and give us your feedback on this or any other aspects of the PDCs. Read through the course descriptions on line and pick the course that best suits your company and career objectives. Every PDC includes a full set of comprehensive course notes. Class sizes typically range from ten to thirty students and there is always ample time for questions and networking. We hope you will consider joining us in Boston for a learning experience like no other.

Education is a lifelong pursuit, don't miss out on this opportunity!
Habib Hichri
IMAPS 2019 PDC Organizer

 

Your PDC Registration Fee Includes:

  • Refreshment breaks
  • Hard-copy workbook of course materials (no electronic copies provided)
  • Lunch (ONLY for those taking BOTH Morning & Afternoon courses)

PDCs under SESSIONS
during IMAPS 2019 Online Registration

PDC Cancellation policy: IMAPS reserves the right to cancel a course if the number of attendees is not sufficient.
You can transfer to a different course or we will refund you the corresponding amount.

Cost for Each PDC: $325 (on/before 8/29/2019); $425 (after 8/29/2019)


 

Early Monday Morning (8:00 AM-10:00 AM) Courses
YOU MAY SELECT ONE OF THESE FOUR COURSES ONLY

Track A:
Wire Bonding & Flip Chip
Track B:
Failure Analysis & Thermal
Track C:
Packaging Integration & Design
Track D:
Heterogeneous Integration & Fan Out

A1: UNDERSTANDING THE WIRE BONDING PROCESS

Hynes Convention Center - ROOM 201

Instructor:
Lee Levine, Process Solutions Consulting, Inc.

Course description:

Wire Bonding is a welding process that is the dominant chip interconnection method. More than 15 trillion wires are bonded annually. In the past gold wire was predominant but in 2015 copper and palladium coated copper wire captured more than 51% of the total market. Copper provides benefits in cost, improved conductivity, stiffness and reliability. However, it is significantly harder than gold and achieving a robust, reliable process is a challenge. Wire bonding high-volume lead-frame often experiences defect rates below 10ppm, this presents a significant barrier to entry for any process competitor but copper is meeting the challenge. The flexibility, reliability and yield of wire bonding make it a process worthy of careful study. Today’s wire bonding equipment is capable of producing 24 wires/second (48 welds) with bond placement accuracy of ±2.0µm. During the descent of the tool the bond head has an acceleration of >300g. Achieving highly repeatable bonds with the stated bond placement accuracy and yet accelerating at 300g requires exceptional engineering design. The wire bonder has evolved into one of the worlds most advanced machines. It requires high speed pattern recognition, ultra-light bond head (for speed and acceleration), stiff (for accuracy and repeatability) sub-assemblies (imagine trying to achieve the same speed and accuracy with a graphite fishing rod), and state-of-the-art control systems.

The course will cover:
-- Introduction
-- A snapshot of some microelectronic packages
-- Size of the market
-- Cost of a wire bond
-- Ultrasonic Welding
-- Intermetallics
-- Bond Testing
-- Copper wire bonding
-- Looping and Ball Formation
-- Wire
-- Fine Pitch Bonding
-- Plating
-- Wire Bond variations (ball bumping)

Biography:

Lee Levine is a consultant for Process Solutions Consulting, Inc. where he provides process engineering consultation, SEM/EDS analysis, and wire bond training. Lee’s previous experience includes 20 years as Principal and Staff Metallurgical Process Engineer at Kulicke & Soffa and Distinguished Member of the Technical Staff at Agere Systems. He has been awarded 4 patents, published more than 70 technical papers, and has won both the John A. Wagnon Technical Achievement award and the Daniel C. Hughes award from the International Microelectronics and Packaging Society (IMAPs). Major innovations include copper ball bonding, loop shapes for thin, small outline packages (TSOP and TSSOP, and CSPs) and introduction of DOE and statistical techniques for understanding semiconductor assembly processes. He is an IMAPs Fellow and a senior, life member of IEEE. Lee is a graduate of Lehigh University, Bethlehem, Pa where he earned a degree in Metallurgy and Materials Engineering.

 

B1: INTRODUCTION TO FAILURE ANALYSIS IN SEMICONDUCTOR PACKAGE ASSEMBLY

Hynes Convention Center - ROOM 202

Instructor:
Tom Dory, Fujifilm Electronic Materials USA

Course description:

The PDC participants will receive an overview of failure analysis methods and reliability testing in assembly. Quickly finding and eliminating package defects and failures due to assembly issues is critical. Package reliability directly affects manufacturing yield, time to market, product performance, customer satisfaction and cost. A thorough understanding of product and technology reliability principles and mechanisms of failure is essential for assembly FA and integration engineers. Knowledge of defects and failure mechanisms enables a high yielding successful assembly process through material choices, package design, process optimization, and thermo-mechanical considerations. Each engineer needs to understand the impact of their choices and methods on the final product. This PDC will discuss, using examples, mechanical and thermal failure mechanisms in assembly and detection methods.

Biography:

Dr. Tom Dory has extensive experience in microelectronics covering semiconductor fab processing and assembly, hybrid circuits, and package assembly & test. Dr. Dory retired from Intel Corporation in the Assembly and Test Technology Development Research division after 20 years in R&D. As Pathfinding Integration Manager of the Intel Substrate Technology Research Labs, he was responsible for development of advanced packaging technology in the areas of MEMS including wafer level bonding, stacked die packages, and line pitch reduction designs. He specialized in packaging and assembly, focusing on high density substrate manufacturing, and chip assembly including flip chip and stacked die and 3D packaging. He was awarded ten patents while at Intel in the areas of embedded package capacitors, underfill applications, and package design.

C1: PASSIVE COMPONENTS AND INTEGRATION FOR HIGH-BANDWIDTH COMPUTING AND COMMUNICATION

Hynes Convention Center - ROOM 203

Instructor:
P M Raj, Florida International University/Georgia Tech PRC

Course description:

Passive component advances and integration is becoming the key to realize ultra-thin and high-performance electronic and bioelectronic systems. This short course will review advances in integrated passives in all three categories - surface-assembled ultra-thin IPDs, package-inserted or fan-out embedded IPDs and package- or wafer-embedded thinfilm passives.

Inductors and capacitors are critical storage components in power converters. Their large size is, however, a major bottleneck for module integration and efficient power management. High-density passives can migrate the power converter close to the load. This can lead to lower losses and more efficient and granular power delivery. The first part of the presentations deals with advances in power passives for high efficiency and power handling.

Passive-active integration for emerging RF (1-77 GHz) packaging will be covered in the second part of the short course. Advanced ceramics, glass and laminates provides unique opportunities for High Q passives in diplexer IPDs and embedded matching networks. Integrated nonreciprocal components, tunable components, EMI shielding or noise isolation with 3D copper and nanomagnetic structures can further enhance the component densities and realize true heterogeneous system integration. Advances in passive integration with additive manufacturing techniques such as inkjet and 3D printing with lower cost and higher on-demand customization will also be reviewed.

Biography:

Dr. P. M. Raj’s expertise is in packaging of electronic and bioelectronic systems, power-supply and RF passive component integration in flex and rigid packages and high-density packaging. He is an Associate Professor with Biomedical Engineering and ECE (Electrical and Computer Engineering) at FIU, Miami. He is an Adjunct Professor with the Georgia Institute of Technology, ECE Department and Packaging Research Center. He co-led several technical thrusts in electronic packaging, working with the whole electronic ecosystem, which includes semiconductor, packaging and material, tool, and end-user companies. He is widely recognized for his contributions in integrated passive components and technology roadmapping, component integration for bioelectronic, power and RF modules.

D1: FAN-OUT WAFER / PANEL-LEVEL PACKAGING

Hynes Convention Center - ROOM 204

Instructor:
John Lau, Unimicron Technology Corp.

Course description:

Fan-out wafer-level packaging (FOWLP) has been getting lots of tractions since TSMC used their InFO to package the application processor for the iPhone 7. In this lecture, the following topics will be presented and discussed. Emphasis is placed on the fundamentals and latest developments of these areas in the past three years. Their future trends will also be explored.

CONTENTS:
(1) Formation of FOWLP: Chip-first (die face-down), Chip-first (die face-up), and Chip-last (RDL-first);
(2) Fabrication of Redistribution Layers (RDLs): Polymer and ECD Cu + Etching, PECVD and Cu damascene + CMP, and Hybrid RDLs;
(3) Warpages: Kinds of Warpages, and Allowable of Warpages;
(4) Reliability of FOWLP: Thermal-Cycling Test, Thermal-Cycling Simulations, Drop Test, and Drop Simulations;
(5) TSMC InFO: InFO-PoP for Smartphones, InFO_AiP for 5G Millimeter Wave, and InFO for HBM;
(6) Samsung PLP: PoP for Smartwatches, and SiP SbS for Smartphones;
(7) Formation of FOPLP: PCB + SAP, PCB + LDI, PCB + TFT-LCD, and PCB/ABF/SAP + LDI;
(8) Wafer vs. Panel: Application Ranges of FOWLP and FOPLP and Critical Issues of FOPLP;
(9) Fan-Out RDL for High Performance Applications: STATSChipPac’s FOFC-eWLB, ASE’s FOCoS, MedieTed’s FO-RDLs, Samsung’s Si-Less RDL Interposer, and TSMC’s InFO_oS;
(10) Trends in FOWLP and FOPLP, and
(11) Summary

Biography:

With more than 39 years of R&D and manufacturing experience in semiconductor packaging, John Lau has published more than 470 peer-reviewed papers, 30 issued and pending US patents, and 20 textbooks on, e.g., Fan-out Wafer-Level Packaging, Heterogeneous Integrations, TSV for 3D Integration, Advanced MEMS Packaging, Reliability of RoHS compliant 2D and 3D IC Interconnects, and 3D IC Integration and Packaging. John is an elected ASME Fellow, an IEEE Fellow, and IMAPS Fellow.

10:00 AM-10:30 AM
Coffee / Networking

Open to all PDC participants

 

Late Monday Morning (10:30 AM - 12:30 PM) Courses
YOU MAY SELECT ONE OF THESE FOUR COURSES ONLY

Track A:
Wire Bonding & Flip Chip
Track B:
Failure Analysis & Thermal
Track C:
Packaging Integration & Design
Track D:
Heterogeneous Integration & Fan Out

A2: INTRODUCTION TO SOLDER FLIP CHIP WITH AN EMPHASIS ON CU PILLAR

Hynes Convention Center - ROOM 201

Instructor:
Mark Gerber, ASE US, Inc.

Course description:

This PDC course will provide a historical overview and background on Solder Flip Chip technology with an emphasis on Copper Pillar Flip Chip as well as short market perspective. Interconnect structure, process flows, materials and package integration process methods for evolving Flip Chip applications will be discussed in detail. Understanding the trade-offs between the traditional Solder based Flip Chip and Copper Pillar is key in determining the silicon device layout and the type of design rules that can be leveraged for new products. As part of this course, the Solder Bump and Copper Pillar Bump structure formation will be reviewed as well as multiple Cu Pillar Flip Chip attachment methods such as Mass Reflow and Thermo-Compression Non-Conductive Paste (TCNCP) bonding. Reliability aspects such as IMC formations and ways to address will also be covered as a key consideration for Interconnect decisions. Current market trends have led to additional questions regarding the longevity of Flip Chip versus other competing technologies such as Fan Out Wafer Level Packaging (FOWLP) will also be reviewed as well as a comparison between technologies.

Biography:

Mark Gerber is the Director of Engineering & Technical Marketing at ASE-US Inc, specializing in Flip Chip and Advanced Interconnect package technologies. Mark joined ASE in Feb of 2015, and brings a diverse set of semiconductor experiences from Texas Instruments, Motorola/Freescale, and Dallas Semiconductor, including advanced interconnect & IC package development, as well as a history of new product introductions. Mark holds a bachelors degree in Mechanical Engineering from Texas A&M University, and has worked in the Semiconductor Industry for the last 20 years, has written +20 papers, and currently holds over 30 patents in the area of semiconductor packaging.

 

B2: THERMAL AND DYNAMIC STRESS FAILURES IN ELECTRONIC AND PHOTONIC PACKAGING: PREDICTION AND PREVENTION

Hynes Convention Center - ROOM 202

Instructor:
Ephraim Suhir, Portland State University

Course description:

Thermal and dynamic (shocks, vibration) stress failures are the major failure modes in electronics and photonics. The most typical mechanical stress failures caused by thermally induced and/or dynamic loadings are addressed and discussed, and possible solutions to the typical reliability problems are suggested. The emphasis is on the role of analytical (“mathematical”) predictive modeling. The major concepts are illustrated by practical numerical examples.

Biography:

Ephraim Suhir is on the faculty of the Portland State University, Portland, OR, USA, and Technical University, Vienna, Austria. He is also CEO of the Small Business Innovative Research (SBIR) ERS Co. in Los Altos, CA, USA. Ephraim is Foreign Full Member (Academician) of the National Academy of Engineering, Ukraine (he was born in that country); IEEE Life Fellow of the Institute of Electrical and Electronics Engineers (IEEE), the American Society of Mechanical Engineers (ASME), the Society of Optical Engineers (SPIE), and the International Microelectronics and Packaging Society (IMAPS); and Fellow of the American Physical Society (APS), the Institute of Physics (IoP), UK, and the Society of Plastics Engineers (SPE). He is Associate Fellow of the American Institute of Aeronautics and Astronautics (AIAA). Ephraim has authored 400+ publications (patents, technical papers, book chapters, books), presented numerous keynote and invited talks worldwide, and received many professional awards.

C2: ACHIEVING HIGH RELIABILITY FOR LEAD-FREE SOLDER JOINTS - MATERIALS CONSIDERATION

Instructor:
Ning-Cheng Lee, Indium Corporation

CANCELLED

D2: EVOLUTION TO ADVANCED FAN OUT

Hynes Convention Center - ROOM 204

Instructor:
John Hunt, ASE US Inc

Course description:

Fan Out technology has evolved as an alternative package to meet the need for miniaturization of electronics, while also providing improved electrical interconnectivity. Until around 2016, Fan Out was considered primarily a solution for low density packaging requirements.

The wide use of mobile and many IOT devices coming into use has driven the need for increased capability of data centers. Fan Out technology is now in production for many of these applications. It also enables the heterogeneous integration of die and memory with improved electrical performance and lower cost than traditional 2.5 packaging for these data center requirements.

We will review how the integration of wafer level processing technologies; substrate evolution and Flip Chip packaging structures have come together into recent advances in high density Fan Out packaging. These packages are for advanced mobile and server applications. They have higher levels of integration and sophistication than has ever been possible in the past. A brief overview of the concept of Fan Out packaging and history of its evolution, and Fan Out developments to meet high end applications will be included in this course.

Biography:

John Hunt is Senior Director, Engineering, Technical Promotion, at ASE (U.S.) Inc., and provides technical support for the Introduction, Engineering, Marketing, and Business Development activities for Advanced Wafer Level and Fan Out Packaging Technologies at ASE. John has more than 45 years of experience in various areas of manufacturing, assembly and testing of electronic components and systems, with emphasis on the development of new technologies and processes. He has a B.S. from Rutgers and an M.S. from the University of Central Florida.

12:30 PM-1:00 PM
Lunch

Open ONLY to PDC participants taking morning AND afternoon courses

 

Early Monday Afternoon (1:00 PM - 3:00 PM) Courses
YOU MAY SELECT ONE OF THESE FOUR COURSES ONLY

Track A:
Wire Bonding & Flip Chip
Track B:
Failure Analysis & Thermal
Track C:
Packaging Integration & Design
Track D:
Heterogeneous Integration & Fan Out

A3: FLIP CHIP PACKAGE TECHNOLOGY AND ASSEMBLY PROCESSES

Hynes Convention Center - ROOM 201

Instructor:
Tom Dory, Fujifilm Electronic Materials USA

Course description:

The objective of this PDC is to provide an improved understanding of current flip chip package options and assembly flows. This workshop will begin with a discussion of current flip chip assembly including fanout wafer level packaging (FOWLP) and 2.5 & 3D package assembly. We will then discuss the newer technology options and issues. Flip chip packaging assembly is not new, but newer device requirements require more connections between the die and package, a tighter bump pitch and more functionally in the package. Laptop computers, tablets and smart phones, using flip chip packaging with thinned die and thin packages are driving new assembly requirements. All new technology drivers bring new challenges that will be discussed in this PDC. These assembly challenges include copper pillar bonding, bump stack material changes, tighter bump pitch, underfill flow and no-flow options, new under fill materials, thermal management with improved thermal interface materials (TIM), embedded passives, and die attach films. Also discussed are current wafer thinning process options including bonding and debonding to a carrier. Dicing and handling thin wafers and die will be covered. Newer bump materials will be discussed with their impact to flip chip or stacked die package assembly.

Biography:

Dr. Tom Dory has extensive experience in microelectronics covering semiconductor fab processing and assembly, hybrid circuits, and package assembly & test. Dr. Dory retired from Intel Corporation in the Assembly and Test Technology Development Research division after 20 years in R&D. As Pathfinding Integration Manager of the Intel Substrate Technology Research Labs, he was responsible for development of advanced packaging technology in the areas of MEMS including wafer level bonding, stacked die packages, and line pitch reduction designs. He specialized in packaging and assembly, focusing on high density substrate manufacturing, and chip assembly including flip chip and stacked die and 3D packaging. He was awarded ten patents while at Intel in the areas of embedded package capacitors, underfill applications, and package design.

 

B3: PREVENTING PRODUCT FAILURE

Hynes Convention Center - ROOM 202

Instructor:
Jennie Hwang, H-Technologies Group

Course description:

This course will address two of likely product failure processes that are induced or aggravated by time, temperature and/or stress - intermetallic compounds and tin whisker. Intermetallic compounds (IMCs) play an increasingly critical role to the performance and reliability of solder interconnections in the chip level, package level and board level of lead-free electronics. Relevant and important aspects of intermetallic compounds (scientific fundamentals and practical application scenarios) will be discussed. The course also examines the presence and formation of IMCs before, during and after solder joint formation (in storage and service), and the IMCs at-interface and in-bulk (contributing from packages and board surface finish coating) in relation to product reliability.

The difference between SnPb and Pb-free solder joint in terms of intermetallic compounds, which in turn is attributed to production-floor phenomena and the actual field failure, will be discussed.

Concerns about tin whisker have been intensifying recently, although the potential issues of tin whisker have been recognized for more than six decades in electronic, electrical and industrial applications. Metal “whiskering” is an intricate, atomic level process. While understanding of tin whisker has advanced, yet the myth exists. This course offers a holistic coverage, from practical perspectives, of all important aspects of tin whisker with emphasis on mitigating the risk by considering the factors that affect tin whisker growth and examining the preventive and remedial solutions. The distinctions of tin whisker from metal dendrites, electro-migration, tin pest and other processes, as well as the practical tin whisker criteria for reliability implications in both SnPb and lead-free environments will be highlighted.

From practical perspectives, tin whisker with emphasis on risk mitigation through understanding the factors that affect tin whisker growth and its preventive and remedial solutions will be outlined. Practical tin whisker criteria for reliability implications in the lead-free environment and the relative effectiveness and the order of priority in mitigating measures will be ranked.

Main topics:
-- Role of intermetallic compounds vs. product reliability
-- Intermetallic compounds - definition, fundamentals, characteristics;
-- Phase diagrams of Pb-free solders in contrast with SnPb;
-- Intermetallic compounds in the intrinsic material- Pb-free vs. SnPb;
-- IMCs formation and growth during production process and in product service life;
-- Different types of intermetallic compounds - effects on solder joint reliability;
-- Intermetallic compounds - at-interface vs. in-bulk;
-- IMCs - effects from substrate compositions (hybrid module thick film pads, PCB surface finish) + component surface coating;
-- Tin whisker vs. tin pest vs. dendrites;
-- Whisker-resistant vs. whisker-proof;
-- Tin whisker - definition, clarification, reference point;
-- Tin whisker - physical phenomena, causes and factors;
-- Tin whisker - concerns, reliability implications, testing challenges;
-- Tin whisker - mitigation remedies, relative effectiveness, plausible theory;
-- Summary - product reliability, principles, best practices.

Biography:

Dr. Hwang, a long-standing leader in lead-free implementation and SMT manufacturing, brings deep knowledge to this course through both hands-on and advisory experiences. Author of 500+ publications including several internationally-used textbooks and a speaker in innumerable international and national events, she has provided solutions to many challenging problems, ranging from production yield to field failure diagnosis to reliability issues in both commercial and military applications. Received numerous honors and awards (e.g., inductee of International Hall of Fame-Women in Technology, National Academy of Engineering, YWCA Achievement Award, R&D-Stars-to-Watch). Has served on the Board of NYSE Fortune 500 companies and on various civic, government and university boards and committees (e.g., Defense Dept. - Globalization Committee, Forecasting Future Disruptive Technologies Committee, National Materials and Manufacturing Board.) She chairs the Board of the Assessment of Army Research Laboratory, of NIST, National Laboratory Assessment Board and the Board of Army Science and Technology. She is a reviewer of various government programs and publications. Her formal education includes Harvard Business School Executive Program and four academic degrees (Ph.D. M.S., M.S., B.S.) in Materials Science & Engineering, Physical Chemistry, Organic Chemistry and liquid Crystal Science. She has held various senior executive positions with Lockheed Martin Corp., IEM Corp. and others. Also an invited distinguished adj. Professor of Engineering School of Case Western Reserve University, and serves on the University’s Board of Trustees.

C3: FUNDAMENTALS OF 3D AND 2.5D PACKAGING INTEGRATION

Hynes Convention Center - ROOM 203

Instructor:
Urmi Ray, Consultant

Course description:

- Why 3D:
o New architectural & partitioning capabilities
o Package Density and Form Factor
o Improved Performance

- Types of 3D:
o Via first
o Via middle
o Via last

- Types of 2.5D
o Si/glass interposer
o Fan Out
o Laminate substrate/embedding

- Manufacturing process flow for Via-middle

- Manufacturing process flow for Si interposer

- Challenges for market adoption
o Cost
o Reliability
o Supply Chain
o Others

- Case Studies of successful recent product adoption
o HBM memory with TSV
o Graphics processor integration using 2.5D

- Roadmap

Biography:

Urmi Ray is an experienced semiconductor professional who works with industry organizations such as iNEMI, IMAPS, SEMI and others on driving advanced packaging and integration strategies. She has worked at JCET Group focusing on advanced system in package (SIP) technologies and Qualcomm as the technology and program lead in several forward looking programs in 3D and 2.5D and system integration, with particular focus on low cost packaging for mobile industry. She joined Qualcomm in 2006, after spending 10+ years at Lucent Technologies Bell Laboratories in NJ working on advanced materials and reliability for a diverse set of product portfolios, including consumer products to high reliability telecommunications projects. She has a PhD from Columbia University (New York City).

D3: HETEROGENEOUS INTEGRATIONS

Hynes Convention Center - ROOM 204

Instructor:
John Lau, Unimicron Technology Corp.

Course description:

Heterogeneous integration contrasts with SoC. Heterogeneous integration uses packaging technology to integrate dissimilar chips, photonic devices, and/or components (side-by-side and/or stack) with different materials and functions, and from different fabless design houses, foundries, wafer sizes, feature sizes and companies into a system or subsystem. For the next few years, we will see more implementations of a higher level of heterogeneous integration, whether it is for time-to-market, performance, form factor, power consumption or cost.

CONTENTS:

(1) System-on-Chip (SoC): A10, A11, and A12;
(2) Heterogeneous Integrations or SiPs: Definitions and Classifications;
(3) Heterogeneous Integrations vs. SoC;
(4) Heterogeneous Integrations on Organic Substrates: Amkor’s Automotive, ASE/Apple’s Smartwatches, Intel’s Knights Landing with HMCs, Intel/AMD’s CPU/GPU on PCB, Cisco’s Chipset on Organic Interposer, Shinko’s i-THOP, SMT, and Flip Chip on Board;
(5) Heterogeneous Integrations on Silicon Substrates (TSV-Interposers): SoW (System-on-Wafer), CoWoS (Chip-on-Wafer-on-Substrates), TSV-Interposers, Fabrication of TSVs, Fabrication of RDLs, Xilinx/TSMC’s CoWoS, and NVidia/TSMC’s CoWoS-2;
(6) Heterogeneous Integrations on Silicon Substrates (TSV-less Interposers, e.g., Bridges): Intel’s EMIB, Imec’s Bridge, and ITRI’s TSH Bridge;
(7) Heterogeneous Integrations on Fan-Out RDL Substrates;
(8) Heterogeneous Integration of PoP (package-on-package): iPhone’s Application Processor with Solder Bumped Flip Chip, Qualcomm’s Application Processor with Solder Bumped Flip Chip, iPhone’s Application Processor with TSMC’s InFO, and Samsung’s Smartwatches with WFPLP;
(9) Heterogeneous Integration of Memory Stacks: Memory Stack with wirebonding and Memory Stack with Low Temperature Bonding;
(10) Heterogeneous Integration of Chip-to-Chip Stacks: Face-to-Face Bonding with TSVs and Face-to-Face Bonding without TSVs;
(11) Heterogeneous Integration of CIS (CMOS Image Sensor) and Logic Chip: Sony’s CIE and ASIC Bonding with TSV, Sony’s CIS and ASIC Cu-Cu Hybrid Bonding without TSV, and STMicroelectronics’s CIS and Logic Bonding with TSV;
(12) Heterogeneous Integration of LED (light-emitting diode) and TSV-Interposers: LED and TSV Interposer Bonding and LED and TSV Interposer Heterogeneous Integration;
(13) Heterogeneous Integration of MEMS (microelectromechanical systems) and Logic Chip: MEMS and TSV Interposer Bonding, MEMS and Logic Bonding, and Logic Wafer with MEMS and Cap Wafer Bonding;
(14) Heterogeneous Integration of VESCL and PD: Embedded Heterogeneous Integration of VESCL and PD and Embedded 3D Heterogeneous Integration of VESCL and PD; and
(15) Trends in Heterogeneous Integrations.

Biography:

With more than 39 years of R&D and manufacturing experience in semiconductor packaging, John Lau has published more than 470 peer-reviewed papers, 30 issued and pending US patents, and 20 textbooks on, e.g., Fan-out Wafer-Level Packaging, Heterogeneous Integrations, TSV for 3D Integration, Advanced MEMS Packaging, Reliability of RoHS compliant 2D and 3D IC Interconnects, and 3D IC Integration and Packaging. John is an elected ASME Fellow, an IEEE Fellow, and IMAPS Fellow.

3:00 PM-3:30 PM
Coffee / Networking

Open to all PDC participants

 

Late Monday Afternoon (3:30 PM - 5:30 PM) Courses
YOU MAY SELECT ONE OF THESE FOUR COURSES ONLY

Track A:
Wire Bonding & Flip Chip
Track B:
Failure Analysis & Thermal
Track C:
Packaging Integration & Design
Track D:
Heterogeneous Integration & Fan Out

A4: UNDERSTANDING THE ROLE OF INTERMETALLIC FORMATION IN GOLD AND COPPER WIRE BONDING

Hynes Convention Center - ROOM 201

Instructor:
Lee Levine, Process Solutions Consulting, Inc.

Course description:

Wire bonding is a high-speed, automatic process used to manufacture approximately 90% of all semiconductor interconnections. Trillions of fine diameter (median diameter approximately 20µm) wires are welded to both the semiconductor die and to the package or substrate leads at rates approaching 25 wires/second. Defect rates often (for well controlled high-volume packages) are <10ppm by wire.

During thing welding process the wire and device or substrate bond pad are joined to form an intermetallic alloy. This alloy (the weld “nugget”) is initially a simple mixture of the two materials but it quickly transforms (transformation is the conversion of one intermetallic compound into another by diffusion) into a compound. As the intermetallic ages (temperature, time) additional intermetallic forms by diffusion and compounds transform within the intermetallic.

Intermetallic stability and growth play an important role in the long-term reliability of semiconductor devices. In the Au-Al system the formation of Kirkendall voids is often the limiting factor in the life of a device. In the Cu-Al system Kirkendall voids do not occur. Intermetallic growth is much slower and requires a significantly higher temperature to form making Cu-Al a good choice for many devices. However, Cu-Al has different failure mechanisms. Cu-Al is susceptible to corrosion. Encapsulation of Cu-Al bonds is much more critical than Au-Al bonds. Moisture absorption and encapsulant pH, trace contamination is critical for Cu-Al. Understanding the formation and growth of intermetallic compounds is key to the reliability of packaging.

Biography:

Lee Levine is a consultant for Process Solutions Consulting, Inc. where he provides process engineering consultation, SEM/EDS analysis, and wire bond training. Lee’s previous experience includes 20 years as Principal and Staff Metallurgical Process Engineer at Kulicke & Soffa and Distinguished Member of the Technical Staff at Agere Systems. He has been awarded 4 patents, published more than 70 technical papers, and has won both the John A. Wagnon Technical Achievement award and the Daniel C. Hughes award from the International Microelectronics and Packaging Society (IMAPs). Major innovations include copper ball bonding, loop shapes for thin, small outline packages (TSOP and TSSOP, and CSPs) and introduction of DOE and statistical techniques for understanding semiconductor assembly processes. He is an IMAPs Fellow and a senior, life member of IEEE. Lee is a graduate of Lehigh University, Bethlehem, Pa where he earned a degree in Metallurgy and Materials Engineering.

 

B4: THERMAL MANAGEMENT USING THERMAL INTERFACE

Hynes Convention Center - ROOM 202

Instructor:
Rita Mohanty, Henkel Corporation

Course description:

Electronics industry continue to move towards highly integrated devices with smaller feature sizes and higher currents to meet the demand of consumers for higher functionality with smaller footprint devices. Higher functionality comes with the price of high heat generation due to higher power dissipation. Design engineers must consider appropriate thermal management approach to meet today’s stringent requirements for device reliability. This is a two part course designed to give the design engineers an overview of fundamentals of passive thermal management using Thermal Interface Materials (TIM). Attendees will learn:

1. Thermal management basics
2. Method of transferring heat from a package or device
3. Types of TIM
4. Characteristics critical to design
5. How to choose the right TIM for your application
6. How to apply TIM
7. How to test TIM before and after application
8. Case study to demonstrate the above topics

Biography:

Dr. Rita Mohanty is the Director of Application Engineering and Technical Customer Service at Henkel Corporation, Thermal Division (former Bergquist Co.). She is an industry recognized expert in the electronics industry with expertise from PCB fabrication and assembly to system level reliability. She has over 20 years of R&D and manufacturing experience in electronics materials and processes. Prior to joining Henkel, she had worked at various leadership capacities at DfR Solutions, McDermidEnthone, ITW Speedline and Alpha Semiconductor Packaging Materials. She is a certified Lean Six Sigma Master Black Belt instructor and taught at Dartmouth College. She has authored and edited books on electronics and numerous technical papers and holds technical patents. She is an active participant with IMAPS, SMTA, iNEMI and IPC. Dr. Mohanty received her BS-PhD from University of Rhode Island in Chemical Engineering.

C4: 5G/mmWAVE PACKAGE DEVELOPMENT REQUIREMENTS AND SOLUTIONS

Hynes Convention Center - ROOM 203

Instructor:
Urmi Ray, Consultant

Course description:

The fifth Generation (5G) mobile communication era is expected to address the insatiable need for data communication by introducing mmWave technology and protocols. The unprecedented latencies offered by 5G Networks will enable users to indulge in gigabit speed immersive services regardless of geographical and time dependent factors. The key to enabling this architecture is packaging and system integration, especially involving an effective antenna structure and RFIC communication in cost-effective, small form-factor packages. As full speed development, demonstration and qualification of mmWave systems have accelerated in 2017, different design and packaging architectures are emerging. This PDC will provide a comprehensive landscape of package development options including LTCC, eWLB/FOWLP as well as laminate based packaging. The specific requirements of materials and process needs (low dielectric material, copper roughness requirements) are discussed. Multiple different package structures are presented as case studies to demonstrate comparative performance of eWLB vs laminate packages. Product application spaces ranging from mobile/handheld to network infrastructures and automotive/satellite radars are highlighted. Key aspects and guidelines towards a cost/performance trade-off analysis will be summarized.

Biography:

Urmi Ray is an experienced semiconductor professional who works with industry organizations such as iNEMI, IMAPS, SEMI and others on driving advanced packaging and integration strategies. She has worked at JCET Group focusing on advanced system in package (SIP) technologies and Qualcomm as the technology and program lead in several forward looking programs in 3D and 2.5D and system integration, with particular focus on low cost packaging for mobile industry. She joined Qualcomm in 2006, after spending 10+ years at Lucent Technologies Bell Laboratories in NJ working on advanced materials and reliability for a diverse set of product portfolios, including consumer products to high reliability telecommunications projects. She has a PhD from Columbia University (New York City).

D4: INTRODUCTION TO SYSTEM IN PACKAGE (SIP) - THE HETEROGENEOUS INTEGRATION DRIVER

Hynes Convention Center - ROOM 204

Instructor:
Mark Gerber, ASE US, Inc.

Course description:

This PDC course will introduce the package platform SiP (System-in-Package) and how some companies are diversifying from SOC (System-on-a-Chip) to leverage heterogeneous silicon integration and overall package miniaturization. A short market perspective will be reviewed as well as how industry segments are leveraging SiP and how the OEM market is evolving and creating system level ecosystems to enabling content revenue- a key area of IOT. SiP general process flow details will be covered as well as key process considerations for yield improvements. In addition, a brief overview of some of the tools that may be leveraged to help miniaturize module solutions and improve performance. As SiP has evolved, there has also been interest in Fan Out Wafer level technology and the potential integration of multiple active devices as well as discretes into this technology- a brief overview of this option and considerations will be discussed.

Biography:

Mark Gerber is the Director of Engineering & Technical Marketing at ASE-US Inc, specializing in Flip Chip and Advanced Interconnect package technologies. Mark joined ASE in Feb of 2015, and brings a diverse set of semiconductor experiences from Texas Instruments, Motorola/Freescale, and Dallas Semiconductor, including advanced interconnect & IC package development, as well as a history of new product introductions. Mark holds a bachelors degree in Mechanical Engineering from Texas A&M University, and has worked in the Semiconductor Industry for the last 20 years, has written +20 papers, and currently holds over 30 patents in the area of semiconductor packaging.

5:30 PM-7:00 PM
Welcome Reception

Open to all IMAPS 2019 participants

Hynes Convention Center - 3RD FLOOR Boylston Hallway

 

 

 

Cost for Each PDC: $325 (on/before 8/29/2019); $425 (after 8/29/2019)

 

 

 
PREMIER Sponsors:

 

    Premier Program Sponsor:
Premier Sponsor - SemiDice / Analog Devices

    Premier Technology Sponsor:

    Premier Technology Sponsor:
    Premier Technology Sponsor:
Bag Insert Sponsor: ASE Group
Premier Tech Sponsor - NGK NTK
Premier Tech Sponsor - 3M
Networking / Event Sponsors:

Lunch & Break Sponsor:

EMD Performance Materials - Corporate Sponsor

Lunch Sponsor:

Lunch Sponsor: MRSI

Keynote/Plenary Sponsor:

Keynote Sponsor: SAMTEC

Posters & Pizza Sponsor:

Northrop Grumman EC - Poster Session Sponsor

Student & Diversity Programs Sponsor:

Honeywell - Student Programs Sponsor

Coffee Break Sponsor:

Break Sponsor: Geib Refining

Coffee Break Sponsor:

Break Sponsor: Spectrum Semiconductor Materials

Bag Insert Sponsor:

Bag Insert Sponsor: NorCom Systems

   
Golf Sponsors
Technic - Golf Hole Sponsor
Golf Hole Sponsor: Amkor Technology
Stellar Industries - Golf Hole Sponsor

Break Sponsor: Geib Refining

Media Sponsors
3D Incites - Media Sponsor
Media Sponsor: MEPTEC
Media Sponsor: US Tech
Media Sponsor: Semiconductor Digest
Media Sponsor: Electronics Cooling

 


CORPORATE PREMIER MEMBERS
  • Amkor
  • ASE
  • Canon
  • Corning
  • EMD Performance Materials
  • Honeywell
  • Indium
  • Kester
  • Kyocera America
  • Master Bond
  • Micro Systems Technologies
  • MRSI
  • NGK NTK
  • Palomar
  • Promex
  • Qualcomm
  • Quik-Pak
  • Raytheon
  • Rochester Electronics
  • Specialty Coating Systems
  • Spectrum Semiconductor Materials
  • Technic