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April 10, 2007

   IMAPS EVENTS
Button Military, Aerospace, Space and Homeland Security Workshop and Tabletop Exhibition - Registration/Hotel Deadlines on April 11 (read more...)

Button IMAPS/ACerS 3rd International Conference and Exhibition on Ceramic Interconnect and Ceramic Microsystems Technologies (CICMT) Just Two Weeks Away - Registration Closes Next Wednesday, April 18 (read more...)

   CHAPTER ACTIVITIES (events listed in chronological order)
Bullet International Conference on Electronics Packaging (ICEP) 2007 (read more...)

Bullet UCSD Presents Nanowires, Nanotubes, Nanotechnology on April 24, 2007, at 6:00pm (read more...)

Bullet Indiana Chapter Vendor's Day and Mini-Symposium on April 30 (read more...)

Bullet New England Chapter 34th Symposium and Expo In Just 3 Short Weeks
(read more...)

Bullet Arizona Chapter Lunch Meeting on Thursday, May 10, Featuring a Presentation from Sandia National Labs on 3D Packaging (read more...)

Bullet Garden State Chapter Spring Symposium on May 15 (read more...)

Bullet SoCal’07 Symposium and Exhibition to Offer Stellar Program, Tabletop Exhibition and Golf Tournament (read more...)

Bullet Metro Chapter to Offer Two Courses This May - Hybrid Pre Cap Visual Inspection; and Process Certification and Defect Recognition: Hybrids, Microcircuits and RF/MMIC Modules (read more...)

Bullet French Chapter SIP-SOC Technical Meeting, CAEN, May 24 (read more...)

Bullet EMPC 2007 - 16th European Microelectronics and Packaging Conference & Exhibition (read more...)

   MEMBERSHIP
Bullet Society Awards 2007 Deadline: May 15th (read more...)


IMAPS Events (view full Web Calendar)

Military, Aerospace, Space and Homeland Security Workshop and Tabletop Exhibition - Registration/Hotel Deadlines on April 11    ^ Top
The Topical Workshop and Tabletop Exhibit on Military, Aerospace, Space and Homeland Security (MASH): Packaging Issues and Applications will be held May 8 - 10, 2007, at the Radisson Plaza Lord Baltimore Hotel, 20 W. Baltimore Street, Baltimore, MD 21201. The technical program, tabletop exhibit information and registration forms are available on-line at www.imaps.org/mash.The registration discounts expire April 11, as does the hotel block. The hotel cannot guarantee pricing or availability after April 11.

IMAPS/ACerS 3rd International Conference and Exhibition on Ceramic Interconnect and Ceramic Microsystems Technologies (CICMT) Just Two Weeks Away - Registration Closes Next Wednesday, April 18   ^ Top
The 3rd International Conference on Ceramic Interconnect and Ceramic Microsystems Technologies (CICMT) is being April 23-26, 2007, in Denver, Colorado. On-line registration will close Wednesday, April 18 at noon eastern. Avoid the long lines on-site, visit www.cicmt.org to make your reservations today.

This three day event will bring together experts from Asia, Europe, North and South America to present and discuss the latest advances in ceramic interconnect and ceramic microsystems technologies. Coming from more than 60 different organizations including universities as well as industrial R&D, the conference will provide a wide spectrum of interests reflected in 60 contributed papers in 14 sessions. This year’s keynote speakers will focus on: Molecular Medical Diagnostics, Microsystems and Microfluidics and Terabit Wireless Devices.

Finally, to provide an opportunity for those involved in development and manufacturing to meet suppliers who support the industry, space has been set aside for tabletop exhibits. To facilitate networking, these exhibits will be located in the same room used for breaks and meals. To reserve space, visit www.cicmt.org or contact Ann Bell (abell@imaps.org; 202-548-8717).

 

Chapter Activities (events listed in chronological order)
International Conference on Electronics Packaging (ICEP) 2007    ^ Top
Sponsored by:
IMAPS Japan / JIEP
IEEE CPMT Society Japan

Supported by
IMAPS Asia-ALC

April 18 -20, 2007
Shinagawa Prince Hotel, Tokyo, Japan

Technical Topics for Conference Papers:

Advanced Packaging, Area Array Packages, Board EMC Evaluation, Built-up Substrates, Bump Formation, Environmental Aspects, EPD/EAD Technology, Flip Chip Technology, High Speed Board Design, Interconnections, LCD Module Packaging, Lead Free Soldering, Manufacturing, Materials, MCM, MEMS Packages, Nano Technology, Optoelectronics, Reliability and Testing, Stacked Structure, Substrate/Interposer, System in Package, Thermal Management, Thin Film Technologies, Trend and Education, Underfilling, VLSI Packaging, Wafer Level Packaging, etc.

Registration Fees:

Speaker 40,000 yen. (Including Reception and Proceedings)

Organizing Committee:

General Chair: Y. Shimada (NEC),
Vice General Chair: H. Nishida (NEP Tech.), M. Nakamura (Hitachi)

Contact:
Secretariat of ICEP 2007
IMAPS Japan / JIEP (Japan Institute of Electronics Packaging)
3-12-2 Nishiogikita, Suginami-ku
Tokyo 167-0042, Japan
Tel: +81-3-5310-2010, Fax: +81-3-5310-2011
E-mail: imaps-j@jiep.or.jp or icep@jiep.or.jp
URL: http://www.jiep.or.jp/icep/

UCSD Presents Nanowires, Nanotubes, Nanotechnology on April 24, 2007, at 6:00pm    ^ Top
Location: UCSD @ Price Center, The Cove Room
Time: 6:00 Social Pizza Hour, 7:00 Presentations

Seating is limited, so make your reservations today by emailing or call Dave Virissimo at 619-464-5430.


SPEAKERS:

Deli Wang, Professor
Overview of Research Activities


Joined in 2004 after his postdoctoral research at Harvard Univ.
Current research revolves around rational growth of new nanomaterials (semiconductor nanowires and nanowire heterostructures); investigation of fundamental electronic, optical and optoelectronic properties of nanostructures; design and development of functional nanoelectronic and nanophotonic systems, for communications, sensing, information storage, biological detection and medicine.

Shadi A. Dayeh, PhD Candidate
Electrical and Computer Engineering Department


1) Controlling the Growth and Transport Properties of III-V Semiconductor Nanowires for Electronic Applications
III-V semiconductor nanowires (NWs) are engineered one-dimensional structures with unusual electronic and optoelectronic properties that hold great promise for next generation nanoelectronic devices (ITRS roadmap).1 To realize their potential, full understanding of and control over nanowire growth, electronic, and optical properties are required.

Jeongwon Park, PhD Candidate
Materials Science and Engineering Program


2) Electrical Properties and Structure Analysis of Y-junction Carbon Nanotubes
Carbon nanotubes (CNTs) show promise for a new molecular electronics based technology due to unique electronic properties and extraordinary mechanical properties. CNTs can be synthesized to be either semiconducting or metallic. Consequently, they can be used in a wide variety of electronics including diodes, transistors, and high frequency devices.

Dr. Bin, Xiang, Postdoctoral Fellow
Electrical and Computer Engineering


3) The Growth of ZnO Nanowire Arrays & Potential Applications
We successfully synthesized high-quality p-type and n-type ZnO nanowire arrays using simple chemical vapor deposition method in a conventional tube furnace, where phosphorus pentoxide has been used as the dopant source in the p-type ZnO nanowire growth process.

:: Read more ::

Indiana Chapter Vendor's Day and Mini-Symposium on April 30    ^ Top
Larry Wallman, Hi-Tek Sales, Vendor's Day Chair
Ray Fairchild, Delphi Electronics and Safety, Technical Chair

The Indiana Chapters of IMAPS and SMTA are joining together to sponsor their annual Vendor’s Day program on Monday, April 30, 2007. It will be held in Indianapolis, Indiana at the Holiday Inn Select – Indianapolis International Airport.

The vendor displays will be open from 4:30 P.M. to 7:00 P.M. and will include a cash bar, door prizes and free hors d’oeuvres for all. A joint IMAPS and SMTA technical symposium begins at 1:00 P.M., featuring presentations by a variety of industry leaders, engineers and inventors. Admission to both events is FREE to all attendees.

Vendor tables are $190 per six-foot table. To reserve a table please contact Vendor’s Day Chairman Larry Wallman at 317-887-2564, or at lwallman@sbcglobal.net. Table registrations will be accepted until April 20.

Schedule of Speakers and Topics:

Time

Speaker

Company

Presentation Title

1:05

Dean Buzby

Heraeus, Inc.

Our Next Generation Multilayer Dielectrics for High Reliability Multilayer Circuits

1:30

Phil Fisher

CIS Microelectronics

New Developments in the LTCC Arena

1:55

Ray Thomas

Sonoscan, Inc.

Finding Defects using Acoustic Microscopy Imaging

2:20

Brian Iverson

Purdue University

Enhanced Electro-Hydrodynamic Micropumping

2:45

 

BREAK

 

3:00

Dr. Gary Bernstein

University of Notre Dame

Keynote Address: Quilt Packaging:  A Novel Interchip Communications Method

3:30

Manuel J. Solis

Foresite, Inc.

Spot Extraction of Contamination on Printed Circuit Assemblies

3:55

Eddie Borzabadi

Delphi Electronics & Safety

Plate Level Packaging / Calibration Alternative for Silicon Based Automotive MAP Sensor

4:20

Dr. Ronald M. Cosby

Ball State University

Nanotechnology Research at Ball State University

New England Chapter 34th Symposium and Expo In Just 3 Short Weeks    ^ Top
The New England Chapter's 34th Symposium and Expo is being held Tuesday, May 1st a
t the Holiday Inn Boxborough Woods, Boxborough MA.

80 Exhibitors / 500 Attendees are expected

Technical Symposium -  Vendor Technical Presentation

Come join us for this Premier Regional Microelectronics Event where this year’s theme is 007 Technology Shaken Not Stirred.

Technical Program

Register On-line - Exhibitors and Attendees

Exhibitor Registration (pdf)
Attendee Registration Form (word)

Arizona Chapter Lunch Meeting on Thursday, May 10, Featuring a Presentation from Sandia National Labs on 3D Packaging    ^ Top

Date: Thursday, May 10, 2007
Schedule: Registration and Lunch at 11:30 – 12:00
Presentation at 12:00
Location: Mesa City Library
Dobson Ranch Branch
2425 S. Dobson Road
Mesa, AZ 85202
Cost:
Luncheon and presentation - $10.00
!!! Special - No Charge for pre-registered attendees !!! 

Vendor display tables available for $15.00

RSVP: RSVP by May 5th to: greg.clemons@intel.com 
Or
Register On-line at No Charge Until May 5

 

Garden State Chapter Spring Symposium on May 15    ^ Top

Date: May 15, 2007
Time: 1:00 P.M.
Location:

Lucent Technologies, Murray Hill, NJ
600 Mountain Avenue
Murray Hill, NJ 07974

Prices:

Exhibit - $175.00 (before May 1, 2007 - $150.00)

Attendee - $20.00 member, $30.00 non-member

Prices include breaks and dinner reception

Session 1:  Flip Chip Packaging

Session 1 continues the trend for the Garden State IMAPS symposium by focusing on Flip Chip Packaging advances and techniques.  The Flip Chip industry is still expanding due to the increased demands for higher performance interconnects between the silicon die and the chip carrier.  Presentations will cover process enhancements, materials and reliability.

Session 2:  Advanced Packaging

Session 2 will explore some of the most advanced electronic packaging being developed in our industry.  Pressures for high performance, as well as integration, is driving some novel uses of materials and packaging techniques.  Presentations will cover embedded active and passive devices, high speed connectors, organic optical wave guides and various strictures, materials and process.

Visit http://www.imaps-gs.org for more information.

SoCal’07 Symposium and Exhibition to Offer Stellar Program, Tabletop Exhibition and Golf Tournament    ^ Top
SoCal’07 Technical Symposium and Tabletop Exhibition, sponsored by IMAPS Southern California Chapters, will be held on May 16, 2007 at the Anaheim Hills Golf Course. We will be having a Golf Tournament in the morning, with papers presented from 10am until 5 pm. Come for some, or come for all! We will have door prizes through out the event.

Time:  Golf Tournament 7 to 11 am
Presentations:  10 to 11, 1 to 2:30, 3:30 to 5pm
Exhibits: 

10 to 12 & 1 to 4 pm  

Note: Table top only.  Exhibitors are encouraged to have their table top setup but are not expected to be "manning" it until after lunch.

Fees:  Attendees: Free.  Lunch is provided
Exhibitors: Contact Exhibits Chair, Bill Gaines
Golf :  $75 Through April 27, $100 after
Register On-Line

Golf Tournament:
This year we are adding a benefit Golf event. This was very popular at National and the SoCal event in San Diego. Proceeds go to The Microelectronics Foundation.

We have a limited number of slots, so get your reservation in early! You can RSVP for the Symposium, or Golf at http://www.imaps.org/registration/socal2007.htm.

Golf Benefit Chairman: Larry Driscoll
21146 Ventura Blvd., Suite 202, Woodland Hills, CA 91364
Tel:    818-704-9087 x100  email:lmdriscoll@sctsinc.com

The following papers will be presented:

  • FLUX-FREE AND VOID-FREE VACUUM SOLDERING PROCESS FOR ADVANCED MICROELECTRONICS PACKAGING
    Paul W. Barnes, SST INTERNATIONAL
  • CARBON COMPOSITE BRINGS THERMAL AND STRUCTURAL BENEFITS TO THE PRINTED CIRCUIT BOARD
    Kris Vasoya, STABLCOR Inc
  • Lithography-Grade Controlled Expansion Substrates for Wafer Level Packaging
    Greg Rudd and Bob Cronk, SMI (Spectra-Mat, Inc.)
  • WEEE & RoHS Directive: What Does It All Mean?
    Gil White, Dynamic Details Inc Solid Micro Via Buildup Technology Gil White, Dynamic Details Inc
  • PCTF Technology Enables Cost Effective SMT Packaging Solutions For RF Components And Modules
    Nahum Rapoport, David Suconick, Moshe Kushnir Remtec, Inc.
    Presented by Stu Weinshanker, Advanced Packaging Associates
  • Thermally Enhanced Interface Adhesives As Replacements For Leaded And Lead-Free Solder
    Steve Anagnostopoulos, Terry Hartman – Diemat, Inc.
    Presented by Stu Weinshanker, Advanced Packaging Associates
  • LED Packaging
    Heraeus

Register On-Line For SoCal 2007

General Chair
Bill Gaines, Northrop Grumman
Email: William.gaines@ngc.com, Tel. (626)812-2199

Metro Chapter to Offer Two Courses This May - Hybrid Pre Cap Visual Inspection; and Process Certification and Defect Recognition: Hybrids, Microcircuits and RF/MMIC Modules    ^ Top
The Metro Chapter of IMAPS is pleased to offer the following courses.

Hybrid Pre Cap Visual Inspection (1 Day)

Date:

May 21, 2007

Time: 8:00 AM-4:30 PM
Location:

Holiday Inn Ronkonkoma
3845 Veterans Highway
Ronkonkoma, NY 11779
Ph: 631-585-9500

Cost:

$350.00 - 1-5 attendees
$300.00 - 5+ attendees

Includes Continental Breakfast and Lunch. Space is limited so reserve early

Reservations:

For reservations or additional information, Contact:
Steve Lehnert
(631) 345-3100
slehnert@mdipower.com

Please make checks payable to Metro IMAPS

Mail To:
Steve Lehnert
C/O Modular Devices
One Roned Road
Shirley, NY 11967

Hybrids/MCMs/RF Modules all require a visual inspection step just prior to encapsulation or hermetic seal. This is a critical process step that requires a high degree of operator skill and understanding of what to look for and reject as part of the inspection process. This course defines the inspection criteria based on traditional Mil Spec documents in conjunction with industry accepted best commercial practices.  Over 200 color photographs of actual production defects are reviewed and discussed in detail.  The students are exposed to a variety of defects and how the defects relate to the materials and process flow.  Inspection checklists are used to simply the criteria and focus on the major problem areas. 

  • Understand what to look for as part of a pre cap visual inspection
  • Learn how to interpret and apply traditional Mil Spec visual inspection guidelines

The course is intended for quality assurance personnel, inspectors, lead operators and others responsible for inspection of the hardware prior to the final package sealing process.

Course Outline:

Hybrid  Materials and Processing Overview
  • Review of Terminology

General Inspection Guidelines and Procedures

Visual Inspection Requirements Flowdown

  • MIL-PRF-38534
  • MIL-STD-883    

Pre Cap Visual Inspection Criteria

  • Defects related to wafer fab, saw and break, probe test etc.
  • Thick Film/Thin film substrate defects e.g cracks, chipouts
  • Laser Trim defects
  • Epoxy die attach, fillet criteria, typical problems encountered
  • Eutectic solder attach
  • Epoxy attach of chip capacitors and chip resistors                    
  • Wirebond defects (e.g.  Excessive squash out, heel cracks, misplaced bonds etc.)

Foreign Material Identification and Contamination Control

Rework and Repair Limitations

External Visual Inspection

Summary and Course Critique

Process Certification and Defect Recognition - Hybrids, Microcircuits and RF/MMIC Modules

Date:

May 22-25, 2007

Time: 8:00 AM-4:30 PM - May 22-24
8:00 AM-1:00 PM - May 25
Location:

Holiday Inn Ronkonkoma
3845 Veterans Highway
Ronkonkoma, NY 11779
Ph: 631-585-9500

Cost:

$1750.00 - 1-5 attendees
$1500.00 - 5+ attendees

Includes Continental Breakfast, Lunch and Comprehensive Student Workbook (250 pages). Space is limited so reserve early

Reservations:

For reservations or additional information, Contact:
Steve Lehnert
(631) 345-3100
slehnert@mdipower.com

Please make checks payable to Metro IMAPS

Mail To:
Steve Lehnert
C/O Modular Devices
One Roned Road
Shirley, NY 11967

How You Will Benefit:

After completing this course you will:

  • Advance your understanding of the basic materials and processing steps used in the assembly of Hybrids, Microcircuits and RF/MMIC Modules.
  • Know what you’re looking at and what constitutes a “reject” in the production flow along with the technical rationale to support the decision.
  • Be able to explain to others visual defects that result from the basic manufacturing processes: i.e. wirebond, component attach, thick and thin film processing etc.
  • Learn how to interpret and apply the visual inspection criteria contained in the "Workmanship Standards for Hybrids, Microcircuits and RF/MMIC Modules” 2002 Edition*

Who Should Attend:

This course is a must for process engineers, design engineers, manufacturing engineers and senior technicians. Inspectors and experienced operators looking to broaden their knowledge base and understanding of visual inspection criteria would also benefit.  The course is also suited for newly assigned engineers and QA personnel looking to learn the basic terminology and key concepts vital to the manufacturing floor. Trained instructors with years of industry experience deliver the material in a straightforward and easy to understand format.

About this Course:

Most companies struggle to introduce new lines and waste countless manhours and resources resolving old problems on the manufacturing floor. Much of this waste is directly tied to the knowledge and training level of the responsible individuals.  This course is designed teach the fundamental materials and processes used in microelectronics manufacturing and develop an understanding of the relevant visual inspection criteria.  “Knowing what to do” is the first step towards lower costs, improved quality and faster throughput. Multimedia powerpoint presentations and video clips introduce the basics in a classroom setting.

Seminar Instructor:

Thomas J Green has over twenty five years of experience in the microelectronics industry at Lockheed Martin Astro Space and USAF Rome Laboratories and as an Adjunct Professor at the National Training Center for Microelectronics.  During that time period he was a Staff engineer responsible for the materials and manufacturing processes used in building custom high reliability space qualified microcircuits (Hybrids, MCMs and RF modules) for military and commercial communication satellites. Tom has demonstrated expertise in wirebonding, component attach, and seam sealing processes. He has conducted and analyzed numerous statistically designed experiments, which increased first past yield, reduced costs and improved product quality. At Rome Labs he worked as a senior reliability engineer and analyzed component failures from AF avionic equipment along with providing technical support for a variety of Mil specs and standards (e.g. MIL-PRF-38534 and MIL-STD-883). Tom is an active member of the IMAPS (International Microelectronics and Packaging Society) at both the regional and national levels and serves on the IMAPS National Technical Program Committee. Tom has a Masters degree in Industrial Engineering and a B.S. in Metallurgy and Material Science from Lehigh University.  He's published numerous technical papers and in recent years has completed many successful in plant consulting projects.

Course Outline:

DAY 1

Introduction to Manufacturing Processes

  • Terminology and product definitions
  • Hybrids…MCMs…RF/MMIC Modules

Manufacturing Assembly Process Overview

  • Basic manufacturing process flows

Visual Inspection Source Requirements

Semiconductor Processing Overview

GaAs MMIC wafer Fab overview

  • Wafer saw and probing

Foreign material identification and control

  • What is acceptable?

Cleanroom Requirements and Industry Protocols

Commercial vs Military Visual Inspection Requirements

Incoming High Power wafer/chip inspection

Workmanship Standards* Semiconductor Fab related defects (Incoming Visual Inspection)

High Powered Inspection

  • Monolithic silicon die
  • Air bridges, mask defects, voids, metal defects
  • Probe defects, scribing defects,  edge cracks and chipouts
DAY 2

Thick Film Processes  

  • Substrate fabrication and materials overview
  • Screen printing machine variables and controls

The drying and firing process

  • Thickness measuring techniques
  • Cofired ceramics LTCC

Thin Film Processes

  • Sputtering vs vapor deposition
  • Photolithography, coat and etch

Plating operations

  • Electrolytic vs   electroless plating

Laser trimming processes

  • Thick and thin film resistors

Review of Workmanship Standards*Substrate Related Defects

  • Cracks and Chip outs
  • Scratches, voids and other defects
  • Defects related to laser trimming
  • Plating defects and metal lift

Processing fundamentals for Component Attach           

  • Automated handling and assembly of bare die

Material properties overview

Fluid Dispensing

  • Critical processing parameters

DAY 3

Die and substrate attach

Solder attach of GaAs chips

Overview of Common Cleaning Processes

  • Wet chemicals, Plasma cleaning

Review of Workmanship Standards* related to component attach

  • Looking for the proper fillet
  • Component to pad alignment issues
  • Epoxy bleed and runout
  • Flux contamination
  • Excessive solder
  • F/M resulting from the cure process and their effect on wirebonding

Wirebonding Process Overview

  • Ultrasonic/thermosonic bonding
  • Thermocompression bonding
  • Ribbon bonding

Material properties of bonding wire

Wire bonding tools

Factor that affect the wirebond process

Wire bonding reliability and yield problems

Review of Workmanship Standards* Interconnects (Pre Cap Visual Inspection)

  • Overdeformed bonds
  • Underdeformed bonds
  • Bond placement issues

Intermetallic growth and what to look for

  • Defective bond pad metal and platings
  • Misplaced bonds
  • Lifted bonds
DAY 4

Hermetic Packaging Process Overview

  • Seam sealing, Laser welding, Solder sealing
  • Gross and fine leak testing
  • Optical Leak testing techniques

Review of Workmanship Standards* (External Visual Inspection)

  • Cracked seals
  • Poor  welds    
  • Plastic delamination
  • Marking Defects

Course Summary

Student Examination, Test and Review

French Chapter SIP-SOC Technical Meeting, CAEN, May 24    ^ Top
For its 2006 regional meeting, IMAPS France organised, last May in Grenoble, an international workshop on the packaging solutions for system integration. The compared benefits and limitations of System In a Package (SIP) and System On a Chip (SOC) were emphasised and the main semiconductor manufacturers in Europe presented roadmaps for the implementation of their preferred solutions.

The success of the 2006 event incited IMAPS France to keep the same topic, for the 2007 meeting, with an application oriented approach. The workshop will be held, on May 24, in Caen in the frame of a partnership with NXP the former semiconductor branch of Philips.

After the registration of the participants, in the NXP facilities, our partners will present the company and their own SIP/SOC strategy. Then, several industrial actors will disclose their experience returns and the resulting impact on the development of new products, in different market areas including medical, automotive, smart card and wireless systems. They will explain as well how those technologies help to fit in with emerging social needs as assistance, security or identification.

In addition, demonstrations of CAD tools, a poster session and, in the afternoon, the visit of several laboratories or industrial sites will be proposed to the participants according to one’s preference.

For registration or information:

Please contact Florence Vireton at the IMAPS France office, imaps.france@imapsfrance.org
Phone: 33-(0)1-39 67 17 73    Fax: 33-(0)1-39 02 71 93

Or visit the chapter web site,    www.imapsfrance.org

EMPC 2007 - 16th European Microelectronics and Packaging Conference & Exhibition    ^ Top
We warmly invite you to the 16th European Microelectronics and Packaging Conference and Exhibition: EMPC2007. EMPC2007 takes place in the high-tech city of Oulu, Finland, June 17 - 20.

EMPC2007 is the bi-annual IMAPS EUROPE conference, this time organized by IMAPS-NORDIC, the Nordic Chapter of IMAPS. EMPC2007 is co-sponsored by IEEE-CPMT Europe, SMTA and NOKIA.

The EMPC conference addresses "everything in electronics between the chip and the system” welcoming everyone working with or designing products that need to be small, compact, cost effective, reliable and still having complex functionality.

  • More than 150 presentations on opto, nano, micro, MEMS, 3D packaging, SIP, embedded components, applications, medical, RF, thermal management, ceramics, laminates & flex, etc.
  • EU, NAMIS, GBC special sessions
  • 6 short courses
  • A very focused busy exhibition

Please find more details at the conference website: www.empc2007.org. We look forward to meeting you all in Oulu.

Membership Tips

Society Awards 2007 Deadline: May 15th    ^ Top
Every year IMAPS members are asked to point out the Society’s members who have done such notable work that they deserve the distinction of one of our awards to publicly acknowledge their accomplishments.  We have many deserving members, who have given their time, energy, and expertise to ensure our industry has a robust future; you can make sure they are recognized by nominating them for one of our prestigious awards – but it must start with YOU!  The opportunity is here to let that special member know that you value their dedication and that his/her hard work has not gone unnoticed.  The Society Award nominations are now open.The 2007 Awards Nominating Committee is actively seeking nominations for these awards: the Daniel D. Hughes, Jr. Memorial Award; the William D. Ashman Achievement Award; the John A. Wagnon Technical Achievement Award; the Outstanding Educator Award; the Sidney J. Stein International Award; the Corporate Recognition Award; and the Fellow of the Society Award.  The Lifetime Achievement Award is also an individual award, but will be awarded only occasionally when a deserving individual is identified and nominated. Visit http://www.imaps.org/awards/index.htm for details and to nominate that special member. Nominations will be accepted until May 15, 2007.

National Training Center For Microelectronics

Ceramic Interconnect and Ceramic Microsystems Technologies (CICMT 2007)
April 23-26, 2007
Denver, CO

*Exhibitors contact abell@imaps.org

Military, Aerospace, Space and Homeland Security (MASH): Packaging Issues and Applications (MASH)
May 8-10, 2007
Baltimore, MD

*Exhibitors contact abell@imaps.org

IMAPS 2007 - 40th International Symposium on Microelectronics
November 11-15, 2007
San Jose, CA

*Exhibitors contact abell@imaps.org

Integrated/Embedded Passives
November 15-17, 2007
San Jose, CA

^ Top

 
 
 
 
 
 
 
 
 
 
 
 
 
 

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