New England Chapter Technical Meeting – Next Tuesday, February 20 2007 ^
|| Marlborough Marriott
(Formerly the Radisson)
Marlborough, MA 508-480-0015
Route 495 to Exit 24B. Take first right off exit. 75 Felton Street (just before Shell station),
(Times are approximate)
|5:30 p.m. Registration, Socializing, Networking & Cash Bar
6:30 p.m. Dinner
7:30 p.m. Presentation by Joe Belmonte - Speedline Technologies - Franklin, MA
Can High Volume Electronics Manufacturing Technology be used in a High Volume Fuel Cell Manufacturing Process?
During the last several years there has been and continues to be an enormous investment by both governments and industry in the development and manufacture of fuel cells. There are several technical challenges to developing cost effective fuel cells. One of the key areas to reduce fuel cell cost is the manufacturing cost. At Speedline Technologies, we have completed a fuel cell manufacturing process development project using electronics manufacturing industry screen-printing and reflow soldering technologies. Our research indicated that high volume electronics manufacturing technology could be used to develop and implement high volume fuel cell manufacturing. This presentation will focus on the results obtained from this study.
Joe Belmonte is the Advanced Process Development Manager at Speedline Technologies focusing on state of the art process development and training program. Joe has over 30 years of electronic process development experience and holds leadership position at various industry groups, such as SMTA, iNEMI, and IPC.
There's no charge for the Technical Meeting, only for dinner. You may attend without eating dinner.
Dinner Choices: 1) Baked Boston Scrod with Cracker Topping, 2) Chicken Marsala
Pre-registration must be received by Monday February 19th! Send Registrations to:
96 Grant Way
Lancaster, MA 01523-3112
Printable PDF Meeting Notice
SEND NO MONEY! But BRING checks payable to “IMAPS New England” At-door registration is an additional $5.00. If you make a reservation and can’t make the meeting, please cancel by Monday, February 19th or the Chapter is billed for your meal.
Tri-Valley Chapter Dinner Meeting Next Tuesday Featuring Presentation by IMAPS President-Elect, Steve Adamson, Asymtek, and Two Technical Presentations on Implantable Medical Devices ^
Tuesday February 20, 2007, the Tri-Valley Chapter of IMAPS will hold a dinner meeting at the Holiday Inn in Woodland Hills, CA. Steve Adamson, Market Manager, Asymtek, and IMAPS President Elect for 2007, will be introduced and address the meeting. The meeting will start at 6:00 PM. This is a special night with speakers discussing their areas of the implantable medical electronic devices.
Mr. Paul Meadows, Senior Principal Engineer at Advanced Bionics, will speak about the development and packaging of spinal cord and nerve stimulator medical implants that have made his company a leader in this field.
Dr. Nick Talbot, Director of Engineering, and Boozarjomehr (Boozer) Faraji, Microelectronics Reliability and Packaging Principal Engineer of the Second Sight company, will speak about their product developments in the field of sight restoration.
The meeting will commence with dinner at 6:00 PM and end at 9:30 PM
Send checks to
21146 Ventura Blvd. S. 202,
Woodland Hills, CA 91364
Meal Choice: Chicken or Beef
*******Please select with your reservation*******
No Host Bar at 6:00 PM Dinner 6:30
The Holiday Inn is between Canoga and DeSoto Avenues on Ventura Blvd. just south of the 101 Frwy in Woodland Hills. Ph: 818 883-6110
Please let us know ASAP, the room is adequate but if the response is good a larger room is available at this time. So please don't wait to make a reservation this is going to be an interesting evening.
Email to: Larry Driscoll at: email@example.com or call 818 704-9087 to reserve a place. Guests are welcome.
San Diego Chapter February 27 Dinner Meeting Featuring Presentation on Electronics in Extreme Environments of NASA Missions ^
The San Diego Chapter of IMAPS invites you to attend its February 27 Dinner Meeting, at the Holiday Inn, 3805 Murphy Canyon Rd., San Diego. The after dinner talk by Elizabeth Kolawa of the Jet Propulsion Laboratory, will be on electronics in extreme environments of NASA missions.
Social hour is at 5:30 p.m., with dinner at 6:30 and the talk at 7:15. The cost is $7(RSVP’d Students), $15(RSVP’d Members) or $20(Others). For information or to RSVP, contact Dave Virissimo at (619) 464-5430 or firstname.lastname@example.org.
During the next 20 years, NASA is challenged to develop the necessary technologies to support missions to extremely diverse environments. In one extreme, Venus Surface Exploration missions require systems that are able to survive and operate in high temperature (486 C) and high pressure (90 bar) environment. Survivability in extreme high temperatures and high pressures is also required for deep atmospheric multi-probes to Giant planets. On the other extreme, Comet Nucleus Sample Return, Titan, Europa and Moon exploration will require systems able to survive in extremely cold environments in the -140 to –230 C temperature range. In addition, Europa mission presents a challenge of surviving in extremely cold temperatures (-160 C) and high radiation environment. Missions to Mars present the challenge of surviving extreme temperature cycling (-120 to +20 C).
Challenges for development of integrated circuits for these robotic systems deal with the reliable operation of these systems under extreme planetary environments. These challenges are compounded by a complementary set of packaging and assembly issues that address the reliability of the system from the mechanical point of view. Without exception, integrated electronics developed for space systems will have to use existing commercial device and VLSI manufacturing technologies. Because of the severe difference between the extreme environment of the solar system planets and earth, IC designers of space systems have to examine the performance of all the devices in the extreme environment conditions and define a new set of design rules and models that predicts the performance and life cycle of these technologies.
Elizabeth Kolawa has about twenty years of technical experience in the research and development of advanced electronic devices, electronic packaging, thin film materials, miniaturization and integration of electronic systems and sensor technologies. She is currently focused on the development of materials and electronics for operation and survivability in extreme environments of NASA planetary missions. Three years ago, together with her co-workers, she started Technologies for Extreme Environments Consortium that includes 11 universities, industrial members and FFRDCs. The goal of the consortium is to coordinate and focus technology development in the area of low, high, and radiation tolerant electronics and packaging toward NASA needs. For the last four years she is also leading the development of integrated electronics and packaging technologies that are able to survive in the extreme environment of Mars. She is an author of over 130 papers and has ten patents.
Elizabeth Kolawa is presently a Manager of Extreme Environments and Space Avionics Technology Office in the Space Exploration Technology Program at the Jet Propulsion Laboratory.
United Kingdom Chapter Unveils Speaker Program for its Annual Conference - MicroTech 2007 ^
IMAPS UK has announced the speaker program for its MicroTech 2007 conference and exhibition. Starting on March 6th, the two-day conference will focus on advanced microelectronics interconnections, allowing delegates to explore the future challenges and technologies of the industry.
Speakers will include Indro Mukerjee, CEO of C-MAC MicroTechnology, who will be speaking on the panel at the Market Watch session, discussing the issue: "Is the supply chain broken?". Indro will outline the current challenges facing the UK engineering industry to recruit and retain skilled engineering students. With reference to recent research from C-MAC on the state of the UK engineering skills gap, he will articulate the role that academics, industry bodies, and companies should play in inspiring the next generation of British engineers.
Additional speakers on the panel will be Chris Bailey from the University of Greenwich; Dr. Kathryn Walsh, Director of the Electronics Enabled Products, KTN; Mike Trenchard, from the Components Obsolescence Group; and Aubrey Dunford from AFDEC.
David Lowrie, Conference Chairman of IMAPS UK, commented: "The IMAPS UK annual conference is now in its 35th year, and provides a fantastic platform for discussing all facets of the electronic industry's supply chain. In particular, the current skills crisis we are facing is at the top of the agenda and I am confident that this year's event will stimulate inspiring discussions about what the industry can do to reverse the current trend."
Indro Mukerjee commented: "As the head of a company with a long and proud British engineering and manufacturing heritage, I am extremely concerned about the future of British engineering if the apparent decline of engineering studies is not combated. It is imperative that the industry and academia recognises that a collaborative effort is required to shape the future of UK engineering, and the IMAPS conference will provide an invaluable contribution in bringing this issue to the forefront of the industry ."
MicroTech is taking place at the Hellidon Lakes Conference Centre, Daventry, Northamptonshire on 6th & 7th March 2007.
For further information, or if you would like to attend the event, please contact:
+44 (0)1522 575 212
International Conference on Electronics Packaging (ICEP) 2007 ^
IMAPS Japan / JIEP
IEEE CPMT Society Japan
April 18 -20, 2007
Shinagawa Prince Hotel, Tokyo, Japan
Technical Topics for Conference Papers:
Advanced Packaging, Area Array Packages, Board EMC Evaluation,
Built-up Substrates, Bump Formation, Environmental Aspects,
EPD/EAD Technology, Flip Chip Technology, High Speed Board Design,
Interconnections, LCD Module Packaging, Lead Free Soldering,
Manufacturing, Materials, MCM, MEMS Packages, Nano Technology, Optoelectronics, Reliability and Testing, Stacked Structure,
Substrate/Interposer, System in Package, Thermal Management,
Thin Film Technologies, Trend and Education, Underfilling,
VLSI Packaging, Wafer Level Packaging, etc.
Speaker 40,000 yen. (Including Reception and Proceedings)
General Chair: Y. Shimada (NEC),
Vice General Chair: H. Nishida (NEP Tech.), M. Nakamura (Hitachi)
Secretariat of ICEP 2007
IMAPS Japan / JIEP (Japan Institute of Electronics Packaging)
3-12-2 Nishiogikita, Suginami-ku
Tokyo 167-0042, Japan
Tel: +81-3-5310-2010, Fax: +81-3-5310-2011
E-mail: email@example.com or firstname.lastname@example.org
Metro Chapter to Offer Two Courses This May - Hybrid Pre Cap Visual Inspection; and Process Certification and Defect Recognition: Hybrids, Microcircuits and RF/MMIC Modules ^
The Metro Chapter of IMAPS is pleased to offer the following courses.
Hybrid Pre Cap Visual Inspection (1 Day)
May 21, 2007
||8:00 AM-4:30 PM
Holiday Inn Ronkonkoma
3845 Veterans Highway
Ronkonkoma, NY 11779
$350.00 - 1-5 attendees
$300.00 - 5+ attendees
Includes Continental Breakfast and Lunch. Space is limited so reserve early
For reservations or additional information, Contact:
Please make checks payable to Metro IMAPS
C/O Modular Devices
One Roned Road
Shirley, NY 11967
Hybrids/MCMs/RF Modules all require a visual inspection step just prior to encapsulation or hermetic seal. This is a critical process step that requires a high degree of operator skill and understanding of what to look for and reject as part of the inspection process. This course defines the inspection criteria based on traditional Mil Spec documents in conjunction with industry accepted best commercial practices. Over 200 color photographs of actual production defects are reviewed and discussed in detail. The students are exposed to a variety of defects and how the defects relate to the materials and process flow. Inspection checklists are used to simply the criteria and focus on the major problem areas.
- Understand what to look for as part of a pre cap visual inspection
- Learn how to interpret and apply traditional Mil Spec visual inspection guidelines
The course is intended for quality assurance personnel, inspectors, lead operators and others responsible for inspection of the hardware prior to the final package sealing process.
Hybrid Materials and Processing Overview
General Inspection Guidelines and Procedures
Visual Inspection Requirements Flowdown
Pre Cap Visual Inspection Criteria
- Defects related to wafer fab, saw and break, probe test etc.
- Thick Film/Thin film substrate defects e.g cracks, chipouts
- Laser Trim defects
- Epoxy die attach, fillet criteria, typical problems encountered
- Eutectic solder attach
- Epoxy attach of chip capacitors and chip resistors
- Wirebond defects (e.g. Excessive squash out, heel cracks, misplaced bonds etc.)
Foreign Material Identification and Contamination Control
Rework and Repair Limitations
External Visual Inspection
Summary and Course Critique
Process Certification and Defect Recognition - Hybrids, Microcircuits and RF/MMIC Modules
May 22-25, 2007
||8:00 AM-4:30 PM - May 22-24
8:00 AM-1:00 PM - May 25
Holiday Inn Ronkonkoma
3845 Veterans Highway
Ronkonkoma, NY 11779
$1750.00 - 1-5 attendees
$1500.00 - 5+ attendees
Includes Continental Breakfast, Lunch and Comprehensive Student Workbook (250 pages). Space is limited so reserve early
For reservations or additional information, Contact:
Please make checks payable to Metro IMAPS
C/O Modular Devices
One Roned Road
Shirley, NY 11967
How You Will Benefit:
After completing this course you will:
- Advance your understanding of the basic materials and processing steps used in the assembly of Hybrids, Microcircuits and RF/MMIC Modules.
- Know what you’re looking at and what constitutes a “reject” in the production flow along with the technical rationale to support the decision.
- Be able to explain to others visual defects that result from the basic manufacturing processes: i.e. wirebond, component attach, thick and thin film processing etc.
- Learn how to interpret and apply the visual inspection criteria contained in the "Workmanship Standards for Hybrids, Microcircuits and RF/MMIC Modules” 2002 Edition*
Who Should Attend:
This course is a must for process engineers, design engineers, manufacturing engineers and senior technicians. Inspectors and experienced operators looking to broaden their knowledge base and understanding of visual inspection criteria would also benefit. The course is also suited for newly assigned engineers and QA personnel looking to learn the basic terminology and key concepts vital to the manufacturing floor. Trained instructors with years of industry experience deliver the material in a straightforward and easy to understand format.
About this Course:
Most companies struggle to introduce new lines and waste countless manhours and resources resolving old problems on the manufacturing floor. Much of this waste is directly tied to the knowledge and training level of the responsible individuals. This course is designed teach the fundamental materials and processes used in microelectronics manufacturing and develop an understanding of the relevant visual inspection criteria. “Knowing what to do” is the first step towards lower costs, improved quality and faster throughput. Multimedia powerpoint presentations and video clips introduce the basics in a classroom setting.
Thomas J Green has over twenty five years of experience in the microelectronics industry at Lockheed Martin Astro Space and USAF Rome Laboratories and as an Adjunct Professor at the National Training Center for Microelectronics. During that time period he was a Staff engineer responsible for the materials and manufacturing processes used in building custom high reliability space qualified microcircuits (Hybrids, MCMs and RF modules) for military and commercial communication satellites. Tom has demonstrated expertise in wirebonding, component attach, and seam sealing processes. He has conducted and analyzed numerous statistically designed experiments, which increased first past yield, reduced costs and improved product quality. At Rome Labs he worked as a senior reliability engineer and analyzed component failures from AF avionic equipment along with providing technical support for a variety of Mil specs and standards (e.g. MIL-PRF-38534 and MIL-STD-883). Tom is an active member of the IMAPS (International Microelectronics and Packaging Society) at both the regional and national levels and serves on the IMAPS National Technical Program Committee. Tom has a Masters degree in Industrial Engineering and a B.S. in Metallurgy and Material Science from Lehigh University. He's published numerous technical papers and in recent years has completed many successful in plant consulting projects.
Introduction to Manufacturing Processes
- Terminology and product definitions
- Hybrids…MCMs…RF/MMIC Modules
Manufacturing Assembly Process Overview
- Basic manufacturing process flows
Visual Inspection Source Requirements
Semiconductor Processing Overview
GaAs MMIC wafer Fab overview
Foreign material identification and control
Cleanroom Requirements and Industry Protocols
Commercial vs Military Visual Inspection Requirements
Incoming High Power wafer/chip inspection
Workmanship Standards* Semiconductor Fab related defects (Incoming Visual Inspection)
High Powered Inspection
- Monolithic silicon die
- Air bridges, mask defects, voids, metal defects
- Probe defects, scribing defects, edge cracks and chipouts
Thick Film Processes
- Substrate fabrication and materials overview
- Screen printing machine variables and controls
The drying and firing process
- Thickness measuring techniques
- Cofired ceramics LTCC
Thin Film Processes
- Sputtering vs vapor deposition
- Photolithography, coat and etch
- Electrolytic vs electroless plating
Laser trimming processes
- Thick and thin film resistors
Review of Workmanship Standards*Substrate Related Defects
- Cracks and Chip outs
- Scratches, voids and other defects
- Defects related to laser trimming
- Plating defects and metal lift
Processing fundamentals for Component Attach
- Automated handling and assembly of bare die
Material properties overview
- Critical processing parameters
Die and substrate attach
Solder attach of GaAs chips
Overview of Common Cleaning Processes
- Wet chemicals, Plasma cleaning
Review of Workmanship Standards* related to component attach
- Looking for the proper fillet
- Component to pad alignment issues
- Epoxy bleed and runout
- Flux contamination
- Excessive solder
- F/M resulting from the cure process and their effect on wirebonding
Wirebonding Process Overview
- Ultrasonic/thermosonic bonding
- Thermocompression bonding
- Ribbon bonding
Material properties of bonding wire
Wire bonding tools
Factor that affect the wirebond process
Wire bonding reliability and yield problems
Review of Workmanship Standards* Interconnects (Pre Cap Visual Inspection)
- Overdeformed bonds
- Underdeformed bonds
- Bond placement issues
Intermetallic growth and what to look for
- Defective bond pad metal and platings
- Misplaced bonds
- Lifted bonds
Hermetic Packaging Process Overview
- Seam sealing, Laser welding, Solder sealing
- Gross and fine leak testing
- Optical Leak testing techniques
Review of Workmanship Standards* (External Visual Inspection)
- Cracked seals
- Poor welds
- Plastic delamination
- Marking Defects
Student Examination, Test and Review
French Chapter SIP-SOC Technical Meeting, CAEN, May 24 ^
For its 2006 regional meeting, IMAPS France organised, last May in Grenoble, an international workshop on the packaging solutions for system integration. The compared benefits and limitations of System In a Package (SIP) and System On a Chip (SOC) were emphasised and the main semiconductor manufacturers in Europe presented roadmaps for the implementation of their preferred solutions.
The success of the 2006 event incited IMAPS France to keep the same topic, for the 2007 meeting, with an application oriented approach. The workshop will be held, on May 24, in Caen in the frame of a partnership with NXP the former semiconductor branch of Philips.
After the registration of the participants, in the NXP facilities, our partners will present the company and their own SIP/SOC strategy. Then, several industrial actors will disclose their experience returns and the resulting impact on the development of new products, in different market areas including medical, automotive, smart card and wireless systems. They will explain as well how those technologies help to fit in with emerging social needs as assistance, security or identification.
In addition, demonstrations of CAD tools, a poster session and, in the afternoon, the visit of several laboratories or industrial sites will be proposed to the participants according to one’s preference.
For registration or information:
Please contact Florence Vireton at the IMAPS France office, email@example.com
Phone: 33-(0)1-39 67 17 73 Fax: 33-(0)1-39 02 71 93
Or visit the chapter web site, www.imapsfrance.org