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October 30, 2007

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   IMAPS EVENTS
Button IMAPS 2007 On-line Registration Ends Next Wednesday, November 7 (read more...)

Button Registration Ends Tomorrow for IMAPS Lunch and Learn Webcast Series on Stud Bumping: Expanding Flip Chip Into New Applications (read more...)

IMAPS Lunch and Learn Webcast on Stud Bumping: Expanding Flip Chip Into New Applications - Nov 1, 2007 - Sponsored by Kulicke & Soffa

   CHAPTER ACTIVITIES (events listed in chronological order)
Bullet TONIGHT: San Diego Chapter Dinner Meeting Featuring SDSU Advanced Materials Presentations (read more...)

Bullet Metro Chapter Dinner Meeting Next Wednesday, November 7 (read more...)

Bullet IMAPS-Benelux Autumn Event Next Thursday, November 8, 2007, on Latest trends in Electronic Assembly (read more...)

Bullet Third European ATW on Micropackaging and Thermal Management, January 29-31, 2008 La Rochelle, France (read more...)

   PRODUCTS AND PUBLICATIONS
CD-Rom of Technical Presentations from the 2007 Thermal Management Workshop Now Available (read more...)

IMAPS Events (view full Web Calendar)

IMAPS 2007 On-line Registration Ends Next Wednesday, November 7    ^ Top
The 40th International Symposium on Microelectronics will be held November 11-15, 2007, at the McEnery Convention Center in San Jose, California. For more information, and to register, visit www.imaps40th.org.

On-line registration ends on Wednesday, November 7 at 5pm Eastern. Avoid the lines in San Jose, register on-line at www.imaps40th.org.

IMAPS 2007 will feature...

Three World-Renown Keynote Presentations
Stephen M. R. Covey
CoveyLink Worldwide
Author of
The SPEED of Trust
James Miller
Cisco Systems, VP of Product Operations
Dr. Dongkai Shangguan
Flextronics, VP Assembly Technology and Platform Realization
An Unmatched, Global Technical Program
30 Sessions, 200+ Papers
6 Technical Tracks
addressing:
RF, Automotive and Translated Sessions; Systems/Design; Materials; Signal Integrity; Relability and Advanced Technologies
(Program at a Glance)
Interactive Track
14 Professional Development Courses Intro to Microelectronics Packaging...; Low Temp Co-fired Ceramics; Biomedical Materials...; Screen Printing; Advanced Thermal...; Wire Bonding...; and many more.
Translated Sessions: 1 Japanese-to-English and 2 Chinese-to-English Jisso Trend on Automotive Electronics in Japan; Microelectronics Packaging in China I and II
State-of-the-Art Exhibition and Technology Showcase More than 200 booths displaying new products and concepts. Booth space is limited - reserve before it's too late.
Global Business Council Marketing Forum Lighting Your Path to the Future-LED, FPD & IC Market Analysis, Supply Chain Opportunities & Emerging Technology

...and that's only the technical side of the Symposium! There are also a lot of other exciting activites planned for you -- the 13th Annual Golf Classic, the Spouse/Companion Tour, to name only a few.

And we hope to see you at the 40th Anniversary Celebration. Help us celebrate your colleagues and friends who helped shape the Society and all the memories from the past 40 years.

Register Ends Tomorrow for IMAPS Lunch and Learn Webcast Series on Stud Bumping: Expanding Flip Chip Into New Applications    ^ Top

Thursday, November 1, 2007
12:00 noon - 12:30 pm EST
Registration: $25 IMAPS Members / $50 Non-Members

Sponsored by Kulicke & Soffa Industries, Inc.

Webcast Sponsor - Kulicke & Soffa Industries, Inc.
Kulicke & Soffa Industries Inc.
1005 Virginia Drive
Fort Washington, PA 19034 USA
215-784-6000 | 215-659-7588 (F)
www.kns.com

Program Description

Some years ago, SAW Filter manufacturers needed an interconnect methodology that performed better than the formerly used wedge bonding methodology. They turned to flip chip technology, using wafer level stud bumpers and thermosonic flip chip attach machines.  These first-generation flip chip machines worked well for SAW filters, which, by and large, represented most of the installed base. The technology was also used in a few smaller-scale applications as well as at various labs. 

In 2004/2005, a new generation of flip chip equipment was introduced with more features and greater speed, driving down the customer’s COO (cost of ownership). At the same time, other applications were eyeing flip chip because of its better performance connection - the shorter electrical path resulted in lower resistance and inductance.  Most flip chip applications are still processed using solder bumps or electroplated bumps. In many applications, though, stud bumping is now the most cost effective way to bump a wafer.  The combination of wafer mapping of Known Good Die, better flip chip machines and more options for second level assembly has increased designers’ confidence in using stud bumping. 

Now a few years later, the application base is expanding into a broader range of markets. While SAW Filters still play an important role, CMOS image sensors, high brightness LEDs and RFID tags are among applications continuing to stimulate flip chip popularity. A more broad-based industry adoption of stud bumping is forecast for the future.

Presenter

Vince McTaggart is the Product Marketing Manager for Kulicke and Soffa's Microelectronics group located in Fort Washington, PA.  He has been with K&S for 14 years in various positions.  His present responsibilities as a product manager include the company's stud bumper, large area ball bonder, and wedge bonder product lines.  Prior to joining K&S, Vince was employed at Quad Systems and GE Astro.  Mr. McTaggart holds a bachelor's degree in mechanical engineering from Drexel University, Philadelphia, PA. He can be contacted at vmctaggart@kns.com.

Register On-line
Registration Deadline: Tuesday, October 30, 2007

Chapter Activities (events listed in chronological order)

TONIGHT: San Diego Chapter Dinner Meeting Featuring SDSU Advanced Materials Presentations    ^ Top

Date: Tuesday, October 30 , 2007
Schedule: Social Hour 6:00 pm
Dinner & Presentation 7:00 pm
Location: SDSU Aztec Center
Casa Real Room
(Across from Starbucks)
Parking: Structure 6 ($1 / hour)
College Ave. Exit, South of I-8
Map: https://sunspot.sdsu.edu/map/SDSU_MAP.pdf
Cost:

Members and others: $15.00
Students: $5.00

Registration:

To RSVP, contact Dave Virissimo at (619) 464-5430 or dvirissimo@sempck.com. For more information, visit http://sdchapters.org.

PROGRAM:

Dr. Eugene Olevsky
Director SDSU-UCSD Joint Doctoral Program in Engineering Sciences
Distinguished Professor of Mechanical Engineering

Novel Manufacturing Principle for Fabrication of Advanced Composite Materials

A novel technique for the fabrication of complex shape composite materials with functionally distributed properties will be presented. The technique is based on the electrophoretic deposition of powders which allows continuous manufacturing of three-dimensional objects - particle-by-particle, layer-by-layer. The developed technological approach enables the net-shape production of functionally-graded components which have applications in thermal management of electronic circuitry.

Gordon Brown
PhD Candidate
Computational Science Department

3-D Solar Cell Finite Element Sintering Simulation

The sintering process is ubiquitous in manufacturing, but so far no standard simulation or modeling program exists to model the deformation that occurs in this process. An application of the Skorohod Olevsky Viscous Sintering constitutive equation in a finite element model is developed and used to model a solar cell manufacturing problem. Material properties are measured and a solar cell is then modeled using these properties. Simulation results are compared to experimental results and analysis has been made to evaluate the adequacy and usefulness of this approach.

Evan Khaleghi
PhD Candidate
Mechanical Engineering Department

Enhanced microstructure in dye-sensitized solar cells for improved absorption properties

Dye-sensitized solar cells (DSSCs) are a potential alternative to semiconductor solar cells, because of their lower cost and ease of manufacture. However, their performance is not on par with their semiconductor rivals. Through the enhancement of the microstructure of the titanium dioxide layer of the DSSCs through various methods, improved absorption properties have been measured. Some of the enhancement methods may have applications in other areas.

Chaowei Wang
PhD Candidate
Mechanical Engineering Department

Mechanism and Applications of Spark Plasma Sintering

Spark-Plasma Sintering (SPS), also known as Electric-Discharge Sintering (EDS), Pulsed Electric Current Sintering (PECS), and Field-Assisted Sintering (FAS), is a process for rapid heating of powder by electric current, with simultaneous application of external pressure. Compared with conventional hot-pressing, SPS has many advantages; such as high heating rate, less holding time, more uniform heating condition, and intrinsic field effects on mass transport. Various materials have been processed and synthesized by SPS.

Yen-Shan Lin
PhD Candidate
Mechanical Engineering Department

Analysis of natural cutting and piercing tools for biomimetic applications

Biomimetics is the process of replicating a natural material using synthetic materials and methods. By analyzing how nature creates certain tools, particularly with the scanning electron microscope and mechanical testing, we can apply these same principles to improve modern tools. Examples include studying the teeth of the great white shark, the proboscis of the mosquito, and the tooth of the Piranha.

Metro Chapter Dinner Meeting Next Wednesday, November 7    ^ Top

Date: November 7 , 2007
Schedule: Registration/Networking 5:00 pm - 6:30pm
Dinner Buffet 6:30 pm - 7:15 pm
Technical Presentation 7:15 pm - 8:00 pm
Location: Holiday Inn Ronkonkoma
3845 Veterans Highway
Ronkonkoma, NY 11779
Ph: 631-585-9500
Cost:

Members: $30.00 if Pre-Registered November 5, 2007
$35.00 After November 5,2007

Non-Members: $35.00 if Pre-Registered by November 5, 2007
$40.00 After November 5, 2007

Student Members: $10.00 if Pre-Registered before November 5, 2007 $20.00 after November 5, 2007

Exhibits: There are a limited number of vendor tables available for this meeting at a cost of $200.00 or 2 for 300.00. Please contact Steve Lehnert (slehnert@mdipower.com) or Scott Baldassarre (sbaldassarre@miteq.com) if you are interested.
Registration:

Email: sbaldassarre@miteq.com
Phone: Scott Baldassarre: (631) 436-7400 X 9853
WEB: www.imaps.org/chapters/metro

Evaluation of Wire Bond Systems for Manufacturability

Presented by Student Members from Farmingdale College of the State University of NY:

Tim Resig & Christian Grigoleit
Facilitated by: Mike McKeown Orthodyne

Abstract:

As automotive electronics evolve, interconnects between logic processor units and the remote sensors or actuator components play a critical role in assuring reliability and low manufacturing cost of major control systems. These interconnects are typically aluminum wires attached by ultrasonic wire bonding. Several types of substrates are used to mount the logic microprocessors, and facilitate the wire bonding attachment operation.

This paper evaluates two different substrates/coatings for optimal wire bonding characteristics. The substrates/ coatings are aluminum inlay and electroplated nickel phosphorous. Wire bond evaluations included pull testing, shear testing and bond remnants characterization for each of the substrates. Additionally, wire diameter was varied to identify process manufacturing parameters that consistently and repeatedly produced functional wire bonds.

PowerRibbon™ Bonding - An Alternative Interconnect Process for Present & Future Electronics Applications

Presented by Mike McKeown Orthodyne & Tim Resig

Large wire bonding is used in automotive electronics packaging since the mid-1970s. It is used as the interconnect of choice between the module housing as well as the power device and the electronic substrate. Large wire bonding is also the most commonly used interconnect for industrial power modules. It’s flexibility paired with benefits of being an environmentally friendly and robust process performed at room temperature made it the perfect interconnect choice for these complex applications with high reliability requirements. Electronic power steering and hybrid drives are only two of many examples in modern automotive applications which need increasingly higher current capabilities, requiring high power module packaging technology. To address these applications, manufacturers have historically increased the number of large aluminum wires per device or moved to alternative technologies. This posted a growing challenge for large wire bonding. Even though well established and accepted, in both areas, industrial and automotive power modules, the ever larger numbers of wires to be bonded virtually defect-free in a high volume environment under significant cost common for automotive applications, required a fresh review of the interconnect process and the equipment used. Where multiple wires only impact productivity, alternate technologies are less flexible or less reliable than wire bonding and can require extensive re-qualification efforts and investments in new capital equipment. Orthodyne's new PowerRibbon™ Technology was developed to meet the current and future interconnect needs of the power module market. PowerRibbon™ is a new technology designed to work in existing aluminum wire bonding applications, as well as new designs specified for PowerRibbonTM bonding. It requires little change in many of today's existing designs and utilizes the same environmentally friendly room temperature ultrasonic process as aluminum wire bonding. PowerRibbon™ combines the flexibility and robustness of the large aluminum wire bonding process with a higher productivity and in many applications an improved product performance. This paper will discuss wire and ribbon bonding design and performance aspects in present and future automotive applications.

IMAPS-Benelux Autumn Event Next Thursday, November 8, 2007, on Latest trends in Electronic Assembly    ^ Top
The IMAPS Benelux Chapter will hold its Autumn 2007 event on Thursday, November 8, 2007, at TBP Electronics bv, Vlakbodem 10, 3247 CP Dirksland, The Netherlands.

PDF of Program/Registration Form

PROGRAM:

9.00        Registration, coffee, exhibition

9.30        Welcome by the chairman
Nienke Bruinsma, Philips Applied Technologies, NL

9.35        Roadmap assembly technology – trends and challenges
Boris Leekens, TBP Electronics nv, BE
TBP electronics will react to its new era of assembly in which logistics, quality, traceability, technology and flexibility are leading. Therefore the choices in manpower, equipment and software are of essential importance. The challenge is to reach the highest level in automation.

10.00      Packaging technology trends for future circuits – Opportunities of new interconnect types
Bernd Römer, Infineon Technologies AG, DE
S
ystem integration is becoming more and more mainstream for a wide range of applications, from consumer to high performance applications. Semiconductor components for system integration originate from different front end technologies (e.g. silicon ICs, passive chip, power, MEMS, etc.). The use of advanced packaging is an efficient and cost effective way for heterogeneous system integration. Packaging technologies offer many opportunities to integrate different chips, passive components, including separately optimized systems to a system-in-package. 3D integration techniques applying various types of stacked structures and wafer level assembly offer an excellent way to address high electrical performance, e.g. less delay time at higher miniaturization. An overview on different approaches will be given with focus on the future opportunities and collaboration needs to enable such designs.

10.50      Coffee, exhibition

11.20      Through wafer interconnect technologies for 3D system-in-package
Eric van Grunsven, Philips Applied Technologies, NL
Philips and NXP have developed a SB-SiP platform (silicon based system in package) to enable heterogeneous integration. Next generations of modules in the platform, especially in the application of cellular RF transceivers, require a three dimensional interconnect. This paper presents technologies that recently have been studied. First, an overview of different through wafer interconnect technologies, developed within Philips and NXP, will be given. Next, the considerations for through wafer interconnect will be discussed, with special attention on via forming by means of deep reactive ion etching. Third, the first results of a recently developed concept for via filling, by means of paste printing, will be presented.
 
11.45      Fine pitch components and lead free assembly: trends and production issues
Bart Allaert, Connectronics, division of IPTE nv, BE
The introduction of lead-free manufacturing has led to several production issues.  At the same time, the diversity of packages is growing, and the evolution towards finer pitch components is continuing.  The combination of these trends asks for specific assembly processes and a better manufacturing control.  In this presentation the trends regarding fine pitch components and new packages will be given and typical problems with lead free assembly of fine pitch components will be discussed.

12.10      Lunch, exhibition, followed by factory tour

13.30      Die and  Flip Chip Bonding Equipment for advanced Technologies
Christian Ossmann, Datacon Technology GmbH, AT
Requirements of present packages are mainly driven by two factors. These are on one side the packaging cost and on the other side the increased functionality at highest possible fill factor.
This presentation will show some trends as they are seen by a leading equipment supplier. Solutions to handle thin dice as well as different solutions for stacked die packages will be presented. These techniques are already state of the art for the production of memory devices.

To follow the trend towards higher integration, direct contact bonding of stacked dice will be the next stage. Especially the up coming through hole via (TSV) and the flip chip type solid face to face technology require dedicated equipment with a high alignment accuracy at a significant speed. The state of the art equipment for the production will be discussed, as well as the impact of these technologies on future generations of equipment.

14.20      Het omschakelen naar RoHS (loodvrije) productie in het midden - en klein bedrijf.
Gerrit Versteeg, Global Electronics, NL
Toegespitst op assemblage voor derden. Wat komt er op ons af? Waar liggen onze verantwoordelijkheden? Welke informatie is er beschikbaar en waar? Waar en waarom is er externe kennis benodigd? Al deze vragen hebben op logistieke - evenals productiezaken betrekking.

Waar zijn we gestart in 2004 en waar staan wij op dit moment? Welke nieuwe ontwikkelingen komen er nog op ons af? Deze omschakeling is een keten verantwoordelijkheid en de Keten bepaalt het uiteindelijke succes.

14.45      Inspection and Metrology for HDI substrates
Pieter Vandewalle, ICOS Vision Systems, BE
The CI-T120S/CI-T130S is an automated metrology and inspection tool dedicated to High Density Interconnect substrates. The machine combines very advanced inspection technology with very fast substrate handling and sorting capabilities. The innovative 4-in-1 inspection concept combines surface and warpage inspection with the latest COSSAP confocal metrology: bump metrology with metrological accuracy of less than 1 micron, substrate warpage and pad inspection, top surface inspection and bottom surface inspection. 

The high throughput of the machine enables substrate manufacturers to perform 100% inspection and metrology in a production environment.

15.10      Tea, exhibition

15.30      Combination of experiments and simulations in board level reliability
Hans de Vries, Philips Applied Technologies, NL
Several trends in modern electronic applications require a different approach to reliability assessment. Among other things the combination of experiments and model simulations are necessary to save time and costs in reliability tests. In particular the ongoing trend in portable applications requires new types of packages such as HV-QFN, and testing methods, such as board level drop tests and cyclic bending. In this contribution examples will be given of experiments and simulations mutually supporting each other.

15.55      PBA DfX in the RoHS era: Specify the requirements!
Geert Willems, IMEC, BE
From experience we know that a typical PBA design is incomplete with regard to the specification of PCB substrate, components and assembly variables when the design leaves the design department and enters the electronic supply chain. The missing parameters are filled in by the different players in the supply chain such as purchasing departments, PCB manufacturing, component suppliers, assembly contractors, etc. The robust SnPb soldering with its relatively large process window and benign process temperatures was relatively forgiving for this rather nonchalant way of working. However, those days are over since we have entered the RoHS era. The increased material, processing and logistical complexity, the reduced process windows and increased temperatures combined with new and reinforced failure mechanisms both increases the chance on as well as the gravity of PBA failure. Something even Microsoft has experienced recently. In this presentation we discuss what needs to be specified and what may happen if you don't.

16.20      Informal meeting, drinks will be served

17.15      Closing

REGISTRATION:

Register as (includes lunch and coffee) :

Non-Benelux IMAPS member                               80 EUR
membership nr #  ……………………. 

Only for IMAPS Benelux members :                      140 EUR
workshop fee includes 2008 membership fee
membership nr #................................ 

Non member                                                         150 EUR
workshop fee includes 2008 membership fee

Student fee                                                             30 EUR

Registrations should be made before November 5, 2007. Cancellations after November 5 will not be refunded.
After registration, you will receive a confirmation and driving directions.

To register or inquire about tables for exhibition, please contact:

Katrien Vanneste, ELIS-TFCG, Gent University                 
Technologiepark 914A, B-9052 Zwijnaarde 
Tel: +32 (0) 9 264 5350
FAX: +32 (0) 9 264 5374                                                             
E-mail : katrien.vanneste@ugent.be

Third European ATW on Micropackaging and Thermal Management, January 29-31, 2008 La Rochelle, France    ^ Top
The Third European ATW on Micropackaging and Thermal Management will be held, January 29-31, 2008 in La Rochelle on the French Atlantic coast.

The aim of the workshop - now a yearly must - is to help the exchange of information between scientists and engineers who are involved in thermal management, in R&D labs or in the industry.

Like it was done for the second issue, the ATW will be open to table top exhibits, strictly limited to organisations involved in the field of thermal management.

As usual, the workshop is organized, at hotel “Mercure Oceanide”, on a global fees basis for registration, hotel and meals.

Abstracts are being accepted until Monday, November 5, 2007. Visit www.imapsfrance.org for more information.

Interested to attend?

Please contact Florence Vireton at the IMAPS France office, imaps.france@imapsfrance.org
Phone: 33-(0)1-39 67 17 73    Fax: 33-(0)1-39 02 71 93

Products and Publications

CD-Rom of Technical Presentations from the 2007 Thermal Management Workshop Now Available   ^ Top
IMAPS ATW on Thermal Management was held September 24-27, 2007, at the Holiday Inn in San Jose, CA. The workshop featured nine sessions addressing market drivers, pumped liquid cooling, system cooling, air cooling, thermal interface materials, and many other cutting-edge topics. If you were not able to attend this workshop you can purchase the CD-Rom of techincal presentations. Visit http://www.imaps.org/registration/pubs1.asp to reserve your copy today. To view the techincal program, visit www.imaps.org/thermal.

 

Oneida Research Services

IMAPS 2007 - 40th International Symposium on Microelectronics
November 11-15, 2007
San Jose, CA

*Exhibitors contact abell@imaps.org

Integrated/Embedded Passives
November 15-16, 2007
San Jose, CA

Global Business Council Spring Conference 2008
March 16-17, 2008

Scottsdale/Fountain Hills, AZ

International Conference and Exhibition on Device Packaging
March 17-20, 2008
Scottsdale/Fountain Hills, AZ
*Exhibitors contact abell@imaps.org

International Conference on Alternative Energy 2008
April 7-10, 2008
Albuquerque, NM

CICMT 2008 -- IMAPS/ACerS 4th International Conference and Exhibition on Ceramic Interconnect and Ceramic Microsystems Technologies
April 21-24, 2008
Munich, Germany

*Exhibitors contact abell@imaps.org

HiTEC 2008 -- International Conference on High Temperature Electronics
May 13-15, 2008
Albuquerque, NM
*Exhibitors contact abell@imaps.org

^ Top

National Training Center For Microelectronics

 
 
 
 
 
 
 
 
 
 
 
 
 
 

 

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