ITRS Assembly & Packaging Roadmap

Debendra Mallik, Principal Engineer
Intel Assembly and Test Technology Development

The International Technology Roadmap for Semiconductors, known throughout the world as the ITRS, is a fifteen-year assessment of the semiconductor industry’s future technology requirements. These future needs drive present-day strategies for world-wide research and development among manufacturers’ research facilities, universities, and national labs. The objective of the ITRS is to ensure cost-effective advancements in the performance of the integrated circuit and the products that employ such devices, thereby continuing the health and success of this industry. The latest edition of ITRS was released in December 2007. This presentation will cover a review of ITRS key challenges related to Assembly and Packaging area.

Presenter Bio:

Debendra Mallik is a principal engineer in the Assembly and Test Technology Development group in Intel Corporation. He manages packaging technology definition for Intel’s 32nm generation products. He received his B.Tech. degree in Mechanical Engineering from the Indian Institute of Technology and M.S. degree in Engineering Science & Mechanics from Iowa State University. He has been with Intel for 25 years and holds over 20 patents in the field of advanced packaging. He pioneered the development of laminated leadframe packaging which was selected as one of the “best product of the year” by the Semiconductor International journal. Debendra is also well recognized for his significant contributions to the development of high performance and low cost organic flip chip packaging technology. He is a member of the ITRS Assembly & Packaging Committee.

Benelux Chapter Autumn Event on MEMS Packaging, Integration and Applications    ^ Top

Thursday, November 20th, 2008

Venue:

Holst Centre
High Tech Campus 31
Eindhoven
The Netherlands

REGISTER ON-LINE

PROGRAM:

9.00        Registration, coffee, exhibition

9.30        Welcome by the chairman

Fred Roozeboom, NXP Research and TU/e, NL

9.35        Introduction to the Holst Centre

Jaap Lombaers, Holst Centre, NL

9.40            iPill: Design considerations of an electronic pill for drug delivery

Frits Dijksman, Philips Research, NL

10.10          “SoC or SiP ?” : Impact on Test and Packaging

Appo van der Wiel, Melexis, BE

10.40      Coffee, exhibition

11.10      Next generation Lab-on-a-Chip systems: cells, proteins and direct sensing

Edwin Carlen and Albert van den Berg, University of Twente and MESA+, NL

11.40      Packaging issues for variable-focus liquid lenses

Stein Kuiper, Philips Research, NL

12.10      Hand-held diagnostics platform with short test time

Joost Maast, Philips Applied Technologies, NL

12.40      Lunch, exhibition – Holst tour

13.45      MEMS packaging using 3D-Si integration approaches

Anne Jourdain and Eric Beyne, IMEC, BE

14.15      Inkjet printing for semiconductor applications

Peter Briër, PixDro BV , NL

14.45      Coffee, exhibition

15.15      Packaging aspects for MEMS based energy harvesters

Rob van Schaijk and Ruud Vullers, IMEC-NL, NL

15.45      MEMS oscillators for timing applications

Joost van Beek, NXP Semiconductors, NL

16.15      Informal meeting – drinks will be served

17.00      Closing

 

More info & registration

Register On-line

Or Contact:

Katrien Vanneste, ELIS-CMST, Gent University                 
Technologiepark 914A, B-9052 Zwijnaarde 
Tel: +32 (0) 9 264 5350
FAX: +32 (0) 9 264 5374                                                             
E-mail : katrien.vanneste@ugent.be

Northern California December 3 Lunch Meeting on Sensual Packaging    ^ Top

With consumer electronics, meeting performance objectives is a requirement for entry but is no guarantee for success in the market place. Market acceptance and commercial success is driven often by intangibles that are easy to spot only after the fact. The make or break success is largely associated with final packaging. For mobile microelectronic products such as MP3 players, PDAs, cell phones and laptops the language of success is fashion; soft, sleek, sexy, ‘living’, glossy, hard, cold, green are the list of attributes. It is all about Sensual Packaging – Packaging Technology that excites our senses.

The press release in September from HP titled “The first-ever HP digital clutch to debut on Fashion Week runway” probably communicates the trend in consumer electronics. This presentation shares examples of product success, reviews technologies and mix to deliver ‘feelings’ expressed by the Industrial Designer to meet the mood of the consumer on ‘fashion’ and ‘green’ appeal. Value creation centered on Sensual packaging with methods that enhance touch, color, light, smell, and are environmentally compelling will be illustrated.

Srinivas Rao is vice president of Corporate Technology at Flextronics leading the initiative on Advanced Materials. He has held executive and senior technology positions as CEO and CTO of Molecular Nanosystems Inc., vice president of technology at Solectron Corporation, and held technology management and research positions at Raychem Corporation, Eastman Kodak Research Laboratories and RCA Laboratories. Dr. Rao’s technical background and expertise is in materials science, microelectronics and fabrication, electronic packaging, second level and system level assembly, and nanotechnology. Dr. Rao is a Distinguished Alumnus of Indian Institute of Technology Madras, and holds master’s and doctorate degrees in metallurgy and materials science from the Stevens Institute of Technology. He has served on the distinguished Blue Ribbon Task Force on Nanotechnology (2005) for the state of California, is recipient of RCAs “Outstanding Achievement Award, “Engineer of the Year” award in 2000 conferred by EP&P and the STAR Award (2004) for his services rendered to the Asian American community in Santa Clara County in California.

UK Chapter's Basic Packaging Workshop on December 4    ^ Top

Device packaging is now the cornerstone of the industry and is a key skill now needed by managers, engineers and technicians in the electronics chip design, development and manufacturing market as well as University academics and Institute professionals.

An Opportunity to gain knowledge and understanding about the basic technology holding Electronic systems together. A day workshop will cover the 4 main topics of:

• Package trends and technologies including a Market briefing and an insight into Package technology trends and developments.
• Mounting Die including work on Die prep and Epoxy / Eutectic materials and processes.  
• Die Interconnection, covering the Ins & outs of wirebonding, Flip chip and die stacking. 
• Test verification & Reliability looking at pull/Shear test equipment and general Package testing.

There will also be the opportunity to see High Tech Packaging in action with a Factory - Window Tour of the UNISEM facility.

Program:

9.00 am – Registration
9.30 – 10.30 Session 1 - Package trends and technologies
            a) Market briefing – Andy Longford, PandA Europe
            b) Package technology trends and developments.  -  UNISEM
11.00 – 12.00 Session 2 - Mounting Die
            a) Die prep – John Sweet,  LOADPOINT
            b) Epoxy / Eutectic materials and processes. – Mark Currie, HENKEL
12.00 – 12.30 Factory Tour
Lunch break
1.30 – 2.30 Session 3 - Die Interconnection
            a) Ins & outs of wirebonding – Hugh de Lacy, TS2 Micro
            b) Flip chip and die stacking. – TWI
3.00 – 4.00 Session 4 - Test verification & Reliability
            a) pull/Shear test equipment -  Dr Stephen Clark, DAGE
            b) Package testing. – Iain Gardiner, WAFERDATA
Close  

IMAPS India's International Conference on Emerging Microelectronics and Interconnection Technology (EMIT-08)    ^ Top