IMAPS 2012 Program and Registration Now On-line (read more...)
19 Professional Development Courses Just Announced - the Best Industry Experts and Training All In One Place! (read more...)
IEEE-CPMT & IMAPS Workshop on Optoelectronic Packaging and Assembly (read more...)
CHAPTER ACTIVITIES (events listed in chronological order)
Northern California Chapter August 1 Lunch Meeting on Advanced Backend Technology (read more...)
Chesapeake Chapter Summer Technical Symposium August 1 at JHU APL (read more...)
Chicago/Milwaukee Chapter August 14 Lunch Meeting and Tour on Material & Process Advancements (read more...)
Announcing IMAPS France Medical Workshop (read more...)
LAST CALL For Society Awards Nominations - Nominate A Deserving Member/Colleague TODAY! (read more...)
||IMAPS Events (view full Web Calendar)
IMAPS 2012 Program and Registration Now On-line ^ Top
The 45th International Symposium on Microelectronics will be held at the Town and Country Convention Center, San Diego, California, USA, and is being organized by the International Microelectronics And Packaging Society (IMAPS). The IMAPS Technical Committee seeks original papers that present progress on technologies throughout the entire microelectronics/packaging supply chain. The 45th Symposium on Microelectronics will cover three tiers of electronics: Systems and Applications; Design and related measurements; and Materials, Process and Reliability. IMAPS 2012 will feature 6 technical tracks that span the three days of sessions on: 3D IC/Packaging; Modeling, Design & Reliability; Next Generation Materials; Advanced Technologies; Assembly and Packaging; and the international track entitled Packaging & System Integration: A Global Perspective. There will also be an Interactive University Poster Session. The 2012 San Diego Symposium is loaded with new/enhanced features, including: a revamped Thursday program that features 2 keynotes on 3D, a new 3D panel discussion, and sessions in the afternoon; exhibitor "power hour" presentations each day in the hall; and much more.
The Hotel and Early Registration Deadlines are August 15. IMAPS cannot guarantee room availability and/or rates after the published hotel deadline. Book your rooms directly with the hotel before the deadline noted above.
To view the program, registration, exhibit details, and all the activities that are part of IMAPS 2012, visit www.imaps2012.org.
19 Professional Development Courses Just Announced - the Best Industry Experts and Training All In One Place! ^ Top
IMAPS 2012 will feature 19 professional development courses (PDCs) on Sunday, September 9 and Monday, September 10. Details and registration are online. This is our best year yet for PDC. Here's a sampling: 2.5D & 3D Interposer...(NEW); Mechanical Design & Reliability Analysis...(NEW); High Temperature Electronics...(NEW); Patents & Intellectual Property...(NEW); Basics of Microelectronics Packaging; Packaging Industry Updates & Trends; Polymers in Electronic Packaging; TSV...3D IC/Si Integrations; Wire Bonding...; Signal/Power Integrity; High-Performance Thermal Management...; Screen Printing; Design & Analysis of Experiments; and many more.
Do you want to broaden and strengthen your skills and knowledge, optimize your manufacturing processes, and integrate the latest advances in materials and technologies to maintain your strength in today's competitive global market? The Technical Committee of IMAPS is pleased to present a comprehensive offering of Professional Development Courses that provide detailed information on topics of immediate interest to the Microelectronics and Packaging community. So please be sure to choose from the 19 in-depth Professional Development Courses taught by recognized industry experts. You will discover the following key ways that will benefit you.
- Better understand the skills and knowledge necessary in today's industry.
- Be exposed to the rapidly expanding developments in new materials and technologies.
- Consult with renowned authorities about your current R&D or manufacturing problems and challenges.
- Learn new ways to identify, think about, and address your problems and opportunities.
- Great opportunities to interact with industry experts and other course attendees.
- Certificate of Attendance and much more…
Don't miss this opportunity to received training from the industry's brightest, all under one roof. Learn more
IEEE-CPMT & IMAPS Workshop on Optoelectronic Packaging and Assembly ^ Top
The Institute of Electrical and Electronics Engineers - Components, Packaging and Manufacturing Technology Society (IEEE-CPMT) and the International Microelectronics And Packaging Society (IMAPS) jointly announce the 2012 Advanced Technology Workshop on Opto-electronic Packaging and Assembly. This workshop will feature an ITRS Assembly and Packaging Roadmap working session as well. Dates: September 6 & 7, 2012 Location: Embassy Suites, 3100 East Frontera Street, Anaheim, CA 92806. To view the technical announcement, exhibit information, to register, or for other details about the Workshop, visit http://www.cpmt.org/opto2012.
Thursday, September 6, 2012
8:00 am – 5:00 pm
Optoelectronic Packaging & Assembly
Invited technical experts will be presenting on the advances and trends in the Optoelectronic Packaging and Assembly Technology areas for applications such as Optical Interconnects & Semiconductor Photonics, Optical Transceivers & Networks, High Brightness LED and CMOS Image Sensors.
Prof. Ricky Lee, President, IEEE CPMT Society
Dr. Mehdi Asghari, Kotura; Dr. Daniel Van Blerkom, Forza Silicon; Ron Bonne, Philips Lumileds; Dr. Jack Cunningham, Oracle Labs; Dr. Peter De Dobbelaere, Luxtera; Dr. Ali Ghiasi, Broadcom; Dr. Radha Nagarajan, Infinera; Dr. Adit Narasimha, Molex; Prof. George Papen, UCSD; Dr. Mark Verdiell, Samtec
Friday, September 7, 2012
8:00 am – 12:00 pm
ITRS Assembly & Packaging Roadmap Working Session
The International Technology Roadmap for Semiconductors (ITRS) Organization will hold an assembly and packaging roadmap working session for the workshop participants, with a presentation on the ITRS working process and an interactive discussion about their optoelectronic packaging activities..
For Details, visit http://www.cpmt.org/opto2012.
||Chapter Activities (events listed in chronological order)
Northern California Chapter August 1 Lunch Meeting on Advanced Backend Technology ^ Top
||August 1, 2012
David's Restaurant, Banquet & Conference Facilities
5151 Stars & Stripes Drive
Santa Clara, CA 95054
11:30 AM - 12 PM Registration & Networking
11:30 AM - 12:15 PM Buffet Luncheon
12:15 PM - 1:00 PM Speaker Presentation
IMAPS Members $25.00;
Students (with ID) $15.00
Price includes lunch and program. Please email Roger Underwood, IMAPS NorCal Treasurer, at email@example.com before COB Monday July 30, 2012 to guarantee your lunch. SPACE IS LIMITED! Registrations will be confirmed via e-mail. We only accept cash and checks at the door.
Advanced Backend Technology
Jesse Wang, Deputy Director
Backend Technology Support & Marketing
TSMC North America, San Jose, CA
As semiconductors continue to scale, challenges of chip-package integration (CPI) at advanced technology nodes continue to mount, due to requirements for smaller bump pitches, larger die sizes, and lead-free packaging, in an expanding number of product applications. The challenges to enable high-end applications that require higher memory bandwidth and lower power, demanding 3-D die stacking and featuring micro bumps and TSV (Through silicon Via), will be even tougher.
TSMC focuses on CPI addressing integration of advanced silicon interconnects and testing technologies. This adds value for shorter time to market, faster yield learning and better cycle time control. These include silicon Chip on Wafer on Substrate (CoWoS) for high performance applications and copper Bump-on-Trace (BOT) for mobile applications.
Over the past 20 years Jesse Wang has worked for ASIC, IDM, fabless, and foundry companies. His focus had been in ASIC implementation and design services. Recently Jesse moved to backend technologies that feature sub-system level integration and scaling. Currently Jesse is leading the backend technology support and marketing department in field technology support of TSMC North America. Through the years in his career, one thing that has not changed is the interest in customer interface. He has a M.S. in Electrical Engineering from Syracuse University.
Chesapeake Chapter Summer Technical Symposium August 1 at JHU APL ^ Top
||August 1, 2012
Applied Physics Laboratory of Johns Hopkins University
Howard County Room #3
11100 Johns Hopkins Road
Laurel, MD 20723
Map and directions at www.jhuapl.edu
Registration fees and member discounts to cover the costs:
students with ID-$5.00.
Only on-line registration by credit card guarantees a dinner seating. On-line registration ends on Friday, July 27 at COB. Checks/cash only on-site. Additional fee at the door of $5.00.
3:00 Registration, Participant Introductions, and Brief Opening Remarks.
3:30 "Packaging for Solar Grid-tie Inverters."
Dr. Dimosthenis Katsis, Chief Technology Officer of Athena Energy, LLC
4:15 “High Temperature Silicon Carbide Switches and Rectifiers.”
Dr. Ranbir Singh, President of GeneSIC Semiconductor.
4:45 Brief break.
5:00 “Optimized Acoustic Microscopy Screening for Multilayer Ceramic Capacitors.”
Dr. Andrew Kostic, Senior Project Leader at the Aerospace Corporation
5:30 Event wrap-up. Ideas for next event. Other business.
6:30 Event Concludes
PRESENTER BIOS AND ABSTRACTS:
Dr. Dimosthenis (Dimos) Katsis
Chief Technology Officer of Athena Energy, LLC
Dimosthenis Katsis is an electrical engineer and researcher in the field of electronics and solar energy. He graduated from Virginia Tech, getting his Bachelors and Masters Degrees in 1995 and 1997. Dimos continued to study power electronics and electric vehicle design at the Virginia Power Electronics Center and again after joining General Electric as an Edison Engineering fellow. He contributed to the development of a new generation of high power AC drives for steel mills and power semiconductor characterization. Dimos then returned to Virginia Tech to pursue a doctorate in Electrical Engineering, finishing in Jan. 2003. He then joined the U.S. Army Research Laboratory the same year to develop power systems for the battlefield. Dimos left the army labs to begin a new company dedicated to solar power products and reliability engineering in power electronics. He presently teaches at the Johns Hopkins University’s Whiting School of Electrical and Computer Engineering.
Microinverter design and packaging for reliability microinverters are becoming ubiquitous in the renewable energy world as an inexpensive and cost-effective way to provide photovoltaic power to the grid. Their small form-factor and high power density creates various challenges for efficient design in the power semiconductor, capacitor, and magnetics components. We will investigate some of the design tradeoffs and decisions made in the development of microinverter systems for high reliability. A sample system will be presented to demonstrate these relationships.
Dr. Ranbir Singh
President of GeneSIC Semiconductor
Dr. Ranbir Singh founded GeneSiC Semiconductor Inc. in 2004. He has developed critical understanding and published on a wide range of SiC power devices including PiN, JBS and Schottky diodes, MOSFETs, IGBTs, thyristors and field controlled thyristors. He has co-authored over 120 publications in various refereed journals and conference proceedings and is an inventor on 26 issued US patents. He conducted research on SiC power devices first at Cree Inc., and then at the National Institute of Standards and Technology (NIST), Gaithersburg MD. He has served on the Technical committee of the International Symposium on Power Semiconductor Devices and ICs (ISPSD) from 2002-04. He earned his MS & PhD degrees from North Carolina State University.
1200 V Class Super-High Current Gain Transistors or SJTs developed by GeneSiC are distinguished by low leakage currents of < 100 µA at 325° C operating temperature, turn-on and turn-off switching transients of < 15 ns at 250 °C, maximum Common Source current gains of 88 and low on-resistance of 5.8 mΩ-cm2. Results from detailed on-state, blocking, switching and reliability characterization of 1200 V-class 4 mm2 and 16 mm2 SiC SJTs are presented. SiC Schottky rectifiers with >250o C junction temperatures with low leakage currents are presented with a detailed analysis of their ideality factors. GeneSiC’s Schottky rectifiers resulted in a distinct positive temperature co-efficient of avalanche breakdown and offers a much smaller increase in leakage current with temperature from 25o C to 250o C.
Dr. Andrew Kostic
Senior Project Leader at the Aerospace Corporation
Dr. Kostic is a Senior Project Leader at The Aerospace Corporation working with electronic, electrical, and electromechanical parts, materials, and processes. He is a recognized authority on environmental stress screening (ESS). Andy has taught classes in screening of electronics for over 20 years for many organizations including Motorola, University of Wisconsin-Milwaukee, Hong Kong Productivity Council, and the Organizational Effectiveness Institute. Dr. Kostic is the author of numerous technical papers and is a Senior Member of IEEE.
A program was having a significant number of early life failures due to infant mortality of Multilayer Ceramic Chip Capacitors (MLCC). Board rework was difficult and expensive due to the locations of the MLCC and the complexity of the board. The proposed solution was to develop an improved acoustic microscopy screen for MLCC with latent defects 30 MHz acoustic microscopy screening is unable to detect a significant number of life limiting defects MLCC. 50 MHz screening is able to detect the defects that were missed at 30 MHz. There was not a 100% link between the detection of an anomaly and a device failure in this study. Four factors were identified that correlate strongly with MLCC failure rates: (1) Dielectric composition (2) Delaminations (3) Size (4) Capacitance value greater than 100,000 pF MLCC program requirements have been changed to require 50 MHz two sided C-Mode Scanning Acoustic Microscope (C-SAM) 100% lot inspection. The enhanced screen had positive cost impact. A different transducer was required in a screen that was already in place. There was increased screen fallout of MLCCs but the reduced board rework/repair costs more than offset the part cost. Parts passing the enhanced screen have not shown the early life failure issue. Additional work is necessary to determine the effects on MLCC reliability of defects other than delaminations.
Chicago/Milwaukee Chapter August 14 Lunch Meeting and Tour on Material & Process Advancements ^ Top
||August 14, 2012
Trace Laboratories, Inc.
1150 West Euclid Avenue
Palatine, IL 60067
For more company information, click here - www.tracelabs.com
IMAPS Members - $20,
Non-members: - $25,
Students with IDs & displaced members: - $5
On-line registration guarantees seating and lunch. Please register by COB on Friday, August 10th. Participants may pay on-site by cash or check only.
For additional chapter information, please contact Ken Burke of GE Healthcare at 847-345-0224 or firstname.lastname@example.org
11:30 Registration and Networking
12:00 Lunch and Chapter Announcements
12:45 “Palladium Copper and Silver Alloy Bonding Wire.”
William Crockett, Business Development Manager at Tanaka Kikinzoku International (America)
1:15 “High Reliability GGI Flip Chip Interconnect for Small Die.”
Philip Couts, Sales and Marketing Manager at TDK Corporation of America
1:45 Break with refreshments
2:00 “Ceramics for Medical Applications.”
Arne Knudsen, General Manager of Business Development at Kyocera America, Inc.
2:30 “How Silver Powder Metallurgy Affects the Physical Properties of Low Temperature Firing Silver Conductors.”
Samson Shahbazi, Senior Research Scientist at Heraeus Materials Technology, LLC
3:00 “Magnetically Aligned Anisotropic Conductive Adhesives for Electronic Assembly Applications.”
Eric Hoppenjans, President of Indiana Microelectronics, LLC
3:30 Facility Tour of Trace Laboratories
Kevin Mehaffey, General Manager of Trace Laboratories
Announcing IMAPS France Medical Workshop ^ Top
The 1st Workshop on Advanced Technology on Microelectronics, Systems and Packaging for Medical Electronics will be held on December 4-5 in Paris, France. Abstracts are due on Sept. 22, 2012. For further information, please consult the call for papers at the link: http://france.imapseurope.org/images/stories/documentPDF/cfp_medical_2012.pdf.
Organized in collaboration with Yole Développement, the first day of the workshop will feature internationally recognized speakers from industry and academia :
• Industry Trends & Forecasts in Medical Electronics
• Implantable and Wearable in New Diagnostics and Therapies
Abstracts are being requested for 22nd of September on following topics (min. 250 words):
- 3D Packaging & Interconnection
- Component Manufacturing at Chip & Package Level
- Implantable and Wearable Applications
- Systems Communication (High Frequency, Data Remote Monitoring)
- Sensors, Actuators, Power Supply
- Embedded Passives and Associated Technologies
Your submission must include the mailing address, business telephone number and email address and the content must be without commercial information. Address your abstract to email@example.com
Authors will be notified of paper acceptance with instructions for publication before October 15th , 2012. Speaker will benefit with special rate of 120 Euros.
LAST CALL For Society Awards Nominations - Nominate A Deserving Member/Colleague TODAY! ^ Top
IMAPS has many deserving members who have given their time and expertise to ensure our industry has a robust future. Please nominate fellow members who have done such current and notable work that they deserve the distinction of the Society's awards to gain wide recognition of their accomplishments. The awards presentation will be on Tuesday, September 11, 2012, preceding the Symposium's keynote speaker.
Please complete nominations of deserving members only on-line at www.imaps.org/awards/index.htm. The deadline to submit nominations is July 30, 2012.
Nominees for each award are evaluated by their respective Nominating Committee. The Chairperson of the Awards Nominating Committees is the First Past President, Dr. Rajen Chanchani.
A brief description for each award follows:
Daniel C. Hughes, Jr. Memorial Award; for the member that has made the greatest combination of technical achievements related to microelectronics, combined with outstanding contributions supporting the microelectronics industry, academic achievement, or support and service to IMAPS. An IMAPS member has had to be a member in good standing for a minimum of five years to qualify. Recipients of this award automatically become Life Members and Fellows of the Society.
William D. Ashman Achievement Award; for providing significant technical contributions to the electronics packaging industry, while participating and demonstrating support of activities to enhance the electronics packaging profession as a member.
John A. Wagnon Technical Achievement Award; for outstanding technical contributions related to microelectronics technology. The award may be given for a specific accomplishment, for a number of accomplishments over a period of years, or for general overall contributions.
Fellow of the Society Award; for those who have made significant and continuing contributions to IMAPS over the years at any level – local or national. Examples of the nomination criteria usually considered for this award are: (1) service as an officer of a local chapter or in a national office; (2) service as a member of a local, regional, or national committee or task force; and/or (3) presentation of papers or conducting of short courses at local, regional, or national symposia. A nominee must have been an IMAPS member for ten (10) consecutive years to qualify. Recipients of this award automatically become Life Members of the Society.
Corporate Recognition Award; honors and recognizes a corporation that has made significant technical contributions to the microelectronics industry, while demonstrating support of IMAPS through its participation.
Sidney J. Stein International Award; for significant international technical and/or leadership contributions to the microelectronics packaging industry, while participating and demonstrating support of IMAPS International activities to enhance the electronics packaging profession. See more award qualifications listed on-line.
Outstanding Educator Award; for significant contributions to education for the electronics packaging industry and/or to the advancement of IMAPS Student Chapters.
Lifetime Achievement Award; for making an exceptional, visible, and sustained impact on the microelectronics packaging industry in technology, business or both.
This is your chance to recognize a deserving member with the prestige of a Society award.
Deadline to Submit Nominations: July 30, 2012
Northern Cal Chapter
CPMT & IMAPS Optoelectronics
IMAPS 2012 (San Diego)
San Diego, CA
*Exhibitors contact firstname.lastname@example.org
*Exhibitors contact email@example.com
*Exhibitors contact firstname.lastname@example.org
*Exhibitors contact email@example.com
HiTEN (High Temp)
*Exhibitors contact firstname.lastname@example.org
IMAPS 2013 (Orlando)
September 29-Oct. 3
*Exhibitors contact email@example.com