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RGL Enterprises
F&K Delvotec
LORD Corporation

Palomar Technologies

TJ Green Associates, LLC

 

  IMAPS Events (view full Web Calendar)
 

Program & Registration Now On-Line for IMAPS 2013 Orlando - Hotel/Registration Deadlines August 30   ^ Top
The 46th International Symposium on Microelectronics will be held at the Rosen Centre Hotel in Orlando, Florida, USA, and is being organized by the International Microelectronics Assebmly and Packaging Society (IMAPS). The IMAPS Technical Committee seeks original papers that present progress on technologies throughout the entire microelectronics/packaging supply chain. The 46th Symposium on Microelectronics will cover three tiers of electronics: Systems and Applications; Design and related measurements; and Materials, Process and Reliability. IMAPS 2013 will feature 6 technical tracks that span the three days of sessions on: INTERPOSERS & 2.5/3D PACKAGING; MODELING, DESIGN, TEST & RELIABILITY; MATERIALS & PROCESSES; ADVANCED PACKAGING & ASSEMBLY; ADVANCED & EMERGING TECHNOLOGIES; and SPECIAL SESSIONS ON PACKAGING & SYSTEM-INTEGRATION, as well as an Interactive Student Poster Session.

IMAPS 2013 will feature...

Complimentary Exhibit Hall Passes
Exhibits Passes are complimentary this year for all attendees. This complimentary registration ("EXHIBITS ONLY") will allow participants to visit the exhibitors, the welcome reception, the keynote presentations, the GBC Market Forecasting talks (GBC lunch tickets for purchase). (PDCs, Sessions, Proceedings and Lunch are not included)
World-Renown Keynote Presentations
Keynote: Klaus-Dieter Lang
Tuesday, October 1 | 12:00 PM - 12:45 PM
Next Generation of Electronic Systems - Challenges and Solutions for System Integration Technologies

Prof. Dr. -Ing. Dr. sc. techn. Klaus-Dieter Lang - Director of the Fraunhofer Institute for Reliability and Microintegration, IZM, Berlin.
Keynote: David McCann
Wednesday, October 2 | 11:20 AM - 12:05 PM
Progress in Developing an Open Supply Chain for 2.5D/3D Market Enablement

David McCann - Vice President of Packaging at GLOBALFOUNDRIES in Malta, New York.
More 2.5D & 3D IC Content Under One Roof...
A Full 3-Day "Track" featuring five 3D Sessions and more than 30 speakers lecturing on the latest and greatest topics. Also an entire morning of the conference on Thursday dedicated to 2.5D & 3D IC with 3D keynotes from Micron, CNSE, and TEL NEXX. Following the keynotes, there will be a panel on What are preventing 3D IC integrations from High Volume Manufacturing? moderated by John Lau and featuring discussions from Fraunhofer, Qualcomm, Micron, ASE and more...

MONDAY PDCs: (9am-5pm)
- Plating Processes for High Rel Microelectronic Devices; (1/2 Day: 8am-12pm)
- Fundamentals of Glass Technology and Applications for Advanced Semiconductor Packaging; (1/2 Day: 1-5pm)
- Polymers in Electronic Packaging;
- Wire Bonding in Microelectronics...;
- Technology of Screen Printing;
- Recent Advances and New Trends in 3D IC Integration; (NEW)
- 2013 Packaging Advances, Updates and Trends; (NEW)
- Introduction to 3D Power Electronics & Post-Silicon Device Packaging; (NEW)
- Hermeticity Testing of Microelectronics for Aerospace and Medical Application;
- Reliability Data Analysis; (NEW) and
- MEMS Reliability and Packaging

THURSDAY PDCs: (8am-12pm)
- Package on Package Technology...;
- Flexible Optical Media for High Data Rate Interconnections; (NEW)
- Understanding the Common Failure Modes from a Physics of Failure Perspective;
- Embedded Chip Packaging Technologies;
- Practical Aspects of MEMS and Microsystem Packaging; (NEW)
- Signal/Power Integrity Design for Electronic Packaging and 3D System Integration;
- Managing the Effects of Mechanical Stress on Performance of Modern SOCS; (NEW) and
- Intro to the Design & Fabrication of RF, High Speed and Microwave Hybrids, MCM's and Modules (NEW)

30 Sessions, 225+ abstracts and a University nteractive Poster Session
6 Concurrent Technical Tracks
addressing:
Interposers & 2.5D/3D Packaging; Modeling/Reliability; Materials & Processes; Advanced Packaging & Assembly; Advanced & Emerging Technologies; Special Sessions on Packaging & System-Integration
Dedicated exhibit hall displaying new products and concepts.
This GBC Fall Luncheon & Market Forecasting Analyst Session is a business session that will provide industry insight to IMAPS 2013 participants. It will feature one keynote lunch presenter followed by two market forecasting presentations. A lively interactive audience question and answer session will follow.
A University Poster Session, a Student Industry Panel/Reception, Corporate Tour at Micross Components, Student Competitions and other programs are designed to provide students with technical information, industry insight, and valuable connections.

...and that's only the technical side of the Symposium! There are also a lot of other exciting activites planned -- the 19th Annual Golf Classic, the Welcome Reception and opening ceremonies, to name only a few.

We hope you enjoy the 46th International Symposium on Microelectronics - IMAPS 2013, Orlando!

Register On-Line

Technical Program | Professional Development Courses (PDCs) | Exhibition Information

Get Trained! 19 Professional Development Courses Now Open    ^ Top

NEW PDC FORMAT THIS YEAR - Monday & Thursday Courses

Monday PDCs: full-day courses, running 9:00 am - 5:00 pm;
two half-day courses (8:00am - 12:00pm & 1:00 pm - 5:00 pm)

All Thursday PDCs are half-day, running 8:00 am - 12:00 pm

MONDAY PDCs: (9am-5pm)
- Plating Processes for High Rel Microelectronic Devices; (1/2 Day: 8am-12pm)
- Fundamentals of Glass Technology and Applications for Advanced Semiconductor Packaging; (1/2 Day: 1-5pm)
- Polymers in Electronic Packaging;
- Wire Bonding in Microelectronics...;
- Technology of Screen Printing;
- Recent Advances and New Trends in 3D IC Integration; (NEW)
- 2013 Packaging Advances, Updates and Trends; (NEW)
- Introduction to 3D Power Electronics & Post-Silicon Device Packaging; (NEW)
- Hermeticity Testing of Microelectronics for Aerospace and Medical Application;
- Reliability Data Analysis; (NEW) and
- MEMS Reliability and Packaging

THURSDAY PDCs: (8am-12pm)
- Package on Package Technology...;
- Flexible Optical Media for High Data Rate Interconnections; (NEW)
- Understanding the Common Failure Modes from a Physics of Failure Perspective;
- Embedded Chip Packaging Technologies;
- Practical Aspects of MEMS and Microsystem Packaging; (NEW)
- Signal/Power Integrity Design for Electronic Packaging and 3D System Integration;
- Managing the Effects of Mechanical Stress on Performance of Modern SOCS; (NEW) and
- Intro to the Design & Fabrication of RF, High Speed and Microwave Hybrids, MCM's and Modules (NEW)

 

Do you want to broaden and strengthen your skills and knowledge, optimize your manufacturing processes, and integrate the latest advances in materials and technologies to maintain your strength in today's competitive global market? The Technical Committee of IMAPS is pleased to present a comprehensive offering of Professional Development Courses that provide detailed information on topics of immediate interest to the Microelectronics and Packaging community. So please be sure to choose from the 18 in-depth Professional Development Courses taught by recognized industry experts. You will discover the following key ways that will benefit you.

  • Better understand the skills and knowledge necessary in today's industry.
  • Be exposed to the rapidly expanding developments in new materials and technologies.
  • Consult with renowned authorities about your current R&D or manufacturing problems and challenges.
  • Learn new ways to identify, think about, and address your problems and opportunities.
  • Great opportunities to interact with industry experts and other course attendees.
  • Courses now offered Monday and Thursday so you can attend a course without missing the conference or extending your travel plans!

Your PDC Registration Fee Includes:

  • Lunch on the day of your course (Monday full-day PDCs only)
  • Refreshment breaks
  • Hard-copy workbook of course materials (no electronic copies provided)
  • Attendee list following your course

Monday PDC Lunch sponsored by:
Heraeus Materials Technology - Premier Sponsor, Gold

PDC Cancellation policy:

IMAPS reserves the right to cancel a course if the number of attendees is not sufficient.  You can transfer to a different course or we will refund you the corresponding amount.

PDCs under SESSIONS
during IMAPS 2013 Registrations

Monday, September 30, 2013
Monday Full-Day PDCs run 9:00 am - 5:00 pm

M1A: Plating Processes for High Rel Microelectronic Devices
PDC Instructor: Fred Mueller, General Magnaplate Corp.

1/2 Day Course (4-hour): 8am-12pm

Course Description: Review the engineering differences and troubleshooting problems in the plating processes used in Plating for Electronics... - Comparison of Electroless Nickel / Immersion Gold (Ni/Au), Electroless Nickel / Immersion Silver (Ni/Ag) and Electroless Nickel / Electroless Palladium / Immersion Gold (Ni/Pd/Au) processes - Presents methods for controlling the properties of plating solutions to maximize the deposits properties, including Laboratory Controls / Equipment - Electroless Nickel/Immersion Gold, Solderability and Solder Joint Reliability as Functions of Process Control - What lack of ENIG process controls can result in black pad? - Flip Chips: review of electroplated solders and golds and newer technology - electroplated copper-bumped wafers.

Who Should Attend? This course is intended as an intermediate level (plus and minus a little) course for process engineers, quality engineers, and managers responsible for Plating for Electronics.

Mr. Fred Mueller is a consultant and serves as a national certified instructor for the American Electroplaters and Surface Finishing Foundation (AESF). He has over twenty-five years experience in the plating industry in printed circuits and plating for electronics. He is currently the Corporate Quality Manager at General Magnaplate, Linden, NJ. As a Chemist, Fred has conducted experiments and presented technical papers at SurFin on various topics in electroplating. He has served as Chairman of the Quality in Surface Finishing Committee and the Electro-forming Committee of the AESF.

M1B: Fundamentals of Glass Technology and Applications for Advanced Semiconductor Packaging
PDC Instructor: Dr. TJ Kiczenski, Corning Incorporated

1/2 Day Course (4-hour): 1pm-5pm

Course Description: The objective of this course is to build a foundation of understanding of engineered glass as a material that technologists can leverage in the development of advanced IC packaging applications. Starting from the fundamental principles of glass structure, composition and properties we will provide a broad overview of glass with a focus on unique attributes that make glass as an enabling material. Subjects to be covered will include strength and reliability, chemical durability, thermal behavior, associated thermal relaxation behavior, and electrical properties. Additionally we will review the platform alternatives as part of the "glass toolkit" available to semiconductor packaging development including various manufacturing (melt & form) approaches, the diversity of compositional options and a survey of glass processing options that can be adapted from adjacent glass technology space to advanced semiconductor packaging. Finally the course will illustrate with case studies how glass is contributing to emerging 3D-IC technologies and explore current and potential applications in advanced semiconductor packaging. We will focus on its role as a carrier for temporary bonding, integrated wafer for CMOS Image Sensor, and 2.5D and 3D glass interposers. Relative costs of glass will be discussed as an alternative to other materials for carriers and interposers.

Who Should Attend? The target audiences include individuals or companies with little or no experience in using glass. Engineers, technical managers, scientists, buyers, and managers involved in materials, research and development, and 3D IC packaging.

Dr. TJ Kiczenski is a Research Associate with Corning Incorporated. His work includes investigations of the physics of glass relaxation, liquidus relationships in multicomponent glass forming systems, metallic glasses, and glass/glass and glass/ceramic composite materials. He is credited as the inventor or co-inventor of several Corning Display Technology products manufactured by the proprietary fusion process, including Corning Lotus Glass for low-temperature polysilicon display applications. He received his PhD in Geology and M.S. in Materials Science from Stanford University where he investigated the structure of fluorine in silicate and aluminosilicate glasses and his B.A. degree in Physics from Coe College where he studied alkali-germanate glasses. Aric Shorey, PhD, is a Sr. Technical Manager at Corning Incorporated working on the Semiconductor Glass Wafer program. He has BS/MS in Mechanical Engineering and a PhD in Materials Science - all from the University of Rochester. He has spent the majority of his career in material's finishing and characterization for the telecommunications, precision optics and semiconductor industries.

M2: Polymers in Electronic Packaging
PDC Instructor: Dr. Jeffrey Gotro, InnoCentrix, LLC

Course Description: The course will provide an overview of polymers and the important structure-property-process-performance relationships for electronic packaging. The main learning objectives will be 1) understand how polymers are used in electronic packaging, 2) learn why specific chemistries are used depending on the application 3) learn the fundamentals of polymer characterization related to electronic packaging 4) develop a foundation in rheology and rheology issues in electronic packaging.

Topics to be covered are thermosetting polymers, curing mechanisms (heat and light cured), network formation, and an overview of key chemistries used (epoxies, acrylates, polyimides, bismaleimides, curing agents, and catalysts). The course will provide a more in-depth discussion of the chemistries, material properties, and process considerations for adhesives (both paste and film), capillary underfills, packaging substrate materials, encapsulants (mold compounds), and coatings. Characterization using thermal analysis will be covered allowing understanding of structure-property relationships. The final portion of the PDC will provide an introduction to rheological characterization methods (various types of rheometers and viscometers) and the properties of adhesives (shear thinning, viscosity, time dependence, and rheology changes during curing), underfills, and mold compounds. Participants are invited to bring problems for discussion.

Who Should Attend? Packaging engineers and R&D professionals involved in the development, production, and reliability testing of semiconductor packages would benefit from the course.

Dr. Jeff Gotro has over thirty years experience in polymers for electronic applications and composites having held scientific and leadership positions at IBM, AlliedSignal, Honeywell, and Ablestik Laboratories. He is an accomplished technology professional with demonstrated success solving complex polymer problems, directing new product development, and enabling clients to improve the financial impact of their polymer technologies. Jeff has consulting experience with companies ranging from early-stage start-ups to Fortune 50 companies. Jeff is a nationally recognized authority in thermosetting polymers and he has received invitations to present lectures and short courses at national technical conferences. He has published 60 technical papers (including 4 book chapters) in the field of polymeric materials for advanced electronic packaging applications, holds 13 issued US patents, and has 8 patents pending. Jeff has a Ph.D. in Materials Science from Northwestern University with a specialty in polymer science and a B.S. in Mechanical Engineering/Materials Science from Marquette University.

M3: Wire Bonding in Microelectronics: Materials, Processes, Reliability and Yield
PDC Instructor: Lee Levine Process, Solutions Consulting, Inc.

Course Description: Wire bonding is the dominant method for chip interconnection. This year the semiconductor industry will produce over 1312(13 trillion) wire bonds. As a result of the increase in the cost of gold a significant portion (approximately 15%) of the entire market has already converted to copper ball bonding. A comparison of the costs, reliability, and difficulty of copper ball bonding will be included. The objective of the short course will be an understanding of the process from the metallurgy to process optimization and capillary selection.

  • The Ball Bond Process: Step by Step Wire Bonding
  • Welding
  • The effect of ultrasonics on weld formation and materials properties
  • Metallurgy and Intermetallics
  • A comparison of the welds associated with Au-Al and Al-Cu bonding
  • Au-Al failure mechanisms in ultra-fine pitch bonding
  • The effect of wire alloying on ultra-fine pitch reliability
  • Wire properties, testing and chemistry
  • Pull and shear testing wire bonds
  • Long term accelerated testing of wire bonds
  • Understanding wire stiffness and the effect on looping
  • Wire bond loop shapes
  • The second bond
  • Diffusion
  • The principal bonding variables
  • Capillary design and selection for optimized processes
  • Simple bond screening designed experiments
  • How to optimize the bonding process

Who Should Attend? Engineers and technical people involved in wire bonding and wafer interconnection at all levels from beginners to advanced.

Lee Levine's previous experience includes 20 years as Principal and Staff Metallurgical Process Engineer at Kulicke & Soffa and Distinguished Member of the Technical Staff at Agere Systems. He was awarded 4 patents, published more than 70 technical papers, and won both the 1999 John A. Wagnon Technical Achievement award and the 2012 Daniel C Hughes award from the International Microelectronics and Packaging Society, IMAPS. Major innovations include copper ball bonding, loop shapes for thin, small outline packages (TSOP and TSSOP, and CSPs) and introduction of DOE and statistical techniques for understanding assembly processes. He is a Fellow, a life member and previously was IMAPS V.P Technology.

M4: Technology of Screen Printing
PDC Instructors: Art Dobie, Sefar Inc.; David Malanga, Heraeus, Inc., Thick Film Division

Course Description: Screen printing continues to offer innovative and cost effective solutions to the increasing demands for higher circuit densities. This course is intended to increase the understanding of the screen printing process, thereby improving production yield and print quality.

Presented are some of the latest advancements in composition, screens, and printing technology that enable screen printing to meet future circuit density requirements as well as the definition required for microwave circuitry. The advantages of screen printing, an additive deposition process, are described and compared to alternative more costly and "less-green" subtractive deposition technologies. This course is applications-oriented in terms of how to optimize the screen printing process; how to use and specify screen correctly; rheology properties that affect print results; minimizing printing defects and trouble-shooting problems related to screens, inks and the printing process itself.

Who Should Attend? This course is targeted for production and process engineers, plant and production managers, supervisors, and all others interested in learning how to optimize and increase the use of the screen printing process.

Art Dobie is Technical Marketing Manager for Sefar, Inc. He has been with Sefar 32 years since receiving his BS in Screen Printing Technology in 1980 from California University of Pennsylvania. Art has co-instructed the IMAPS "Technology of Screen Printing" PDC since its inception in 1991. He has delivered numerous technical presentations to screen-printing professionals at local, national and international level symposia. Mr. Dobie is a Life Member and Fellow of the Society of IMAPS, and received the 2006 IMAPS Technical Achievement Award for outstanding technical contributions to screen printing technology relating to microelectronics. In 1998, Art Dobie was inducted into the SGIA's Academy of Screen Printing Technology and is a co-recipient of the SGIA's 2010 David Swormstedt, Sr. Memorial Award.

David Malanga is currently the Business Unit Manager Americas, Thick Film Materials Division of Heraeus in West Conshohocken, PA. David has over 20 years of experience at Heraeus working in R&D, formulating thick film and LTCC materials, Technical Service solving processing and application problems directly with customers, and as manager of the Sales Department. David has a B.S. and M.S. in Ceramic Science and Engineering from Rutgers University. David has published various articles on thick film resistors, conductors, LTCC materials, and component metallizations worldwide. He is a Life member and Fellow of the Society of IMAPS and has held both local and national positions in the organization.

M5: Recent Advances and New Trends in 3D IC Integration
PDC Instructor: John H. Lau, ITRI

Course Description: 3D integration consists of 3D IC packaging, 3D IC integration, and 3D Si integration, which will be discussed in this lecture. Emphases are placed on the key enabling technologies for 3D IC integrations, such as TSV (through-silicon via) forming and filling, front and back-side metallization, RDL (redistribution layer), temporary wafer bonding, wafer thinning and handling, wafer de-bonding, thin chip/wafer strength measurement and improving, lost-cost lead-free microbumping (<=15µm pitch) and assembly, C2C, C2W, and W2W bonding, and thermal management. Useful characterization and reliability data for 3D IC integration will also be provided. The application of 3D IC integration such as MEMS, LED, logic + logic, memory + microprocessor, wide I/O DRAM, active and passive interposers will be presented. Furthermore, the critical issues of TSV and 3D IC integration will be given and some potential solutions or research topics will be recommended. Finally, the supply chains for high volume manufacturing of 3D IC integration will be discussed and several roadmaps of 3D IC integration will be provided. All the materials are based on the technical papers and books published within the past 3 years by the lecturer and others.

Who Should Attend? If you (students, engineers, and managers) are involved with any aspect of the electronics, LED, MEMS, and optoelectronic industry, you should attend this course. It is equally suited for R&D professionals and scientists. You will receive more than 300 pages of handouts from the Instructor's books, "Advanced MEMS Packaging" (McGraw-Hill, 2010), "Reliability of RoHS Compliant 2D & 3D IC Interconnects" (McGraw-Hill, 2011), and "TSV for 3D Integration" (McGraw-Hill, 2012).

Dr. John Lau has been an ITRI Fellow of Industrial Technology Research Institute (ITRI in Taiwan) since January 2010. Prior to that, he was a visiting professor at HKUST for 1 year, the Director of MMC Laboratory with IME in Singapore for 2 years and a Senior Scientist/MTS at HPL/Agilent in California, US for more than 25 years. With more than 35 years of R&D and manufacturing experience, he has published more than 400 peer-reviewed papers, 30 issued and pending US patents, given 280 lectures/workshops/keynotes worldwide, published 17 textbooks on TSV for 3D integrations, 3D MEMS packaging, flip chip & WLP, high-density PCB, SMT, and lead-free materials, soldering, manufacturing and reliability. John earned his PhD degree from the University of Illinois, 3 MASc degrees in North America. John received many awards and is an elected ASME Fellow and has been an IEEE Fellow since 1994.

M6: 2013 Packaging Advances, Updates and Trends (NEW)
PDC Instructor: Phillip G. Creter, Creter & Associates

Course Description: This NEW overview course focuses on 2013 packaging topics, reviewing leading edge developments in microelectronics advances/updates/trends. Abstracts are expanded from 2013 papers to highlight technical innovations, adding selected tables, photos, figures, conclusions, recent news reports, and organized into the following technical groups:

  • 2.5D-TSV Interposers (wafer-level encapsulation, underfill, through-glass-vias using electric discharging, ultra-thin die stacking, warpage control)
  • 3D-TSV (through-silicon-stack for Wide I-O, heterogeneous CoWoS, self-assembly, low-cost chip-on-chip, low temperature Cu-Cu bonding, temporary wafer bonding)
  • Chip-Package-Interactions (ultra-thin chip stacking/packaging, stress testing, warpage design/control, coreless substrates)
  • Flip Chip (fine-pitch/micro-pitch copper pillars, predicting electromigration reliability, large die on coreless, non-conductive adhesive for micro-pitch, thermally-enhanced FC)
  • LED (very high power density, high-brightness substrate-reflectivity study, nano-composites, quasi-conformal phosphor dispensing, ultra-thin wafer-level-packaging)
  • MEMS (hermetic wafer-to-wafer bonding, carrier wafer with self-assembled monolayer, outgassing, low-cost sensor, high temperature SiC MEMS)
  • Microbumps (minimizing electromigration, effect of plating on microbump reliability, design rules, key elements of sub-50 um microbumps, micro-solder bumps)
  • New Adhesives (Ultra-Fine-Pitch adhesives, micro-pitch interconnects using ACF, NCF wafer lamination, high-thermal conductive ACF, isotropic conductive adhesive using micro-spheres)
  • Embedded Chips (microprocessor/capacitors, WLCSP, wafer/panel mold embedding, reliability, capacitor-embedded interposers)

Technical innovations presented with input from leading industrial/academic institutions: Amkor, Asahi Glass, ASE, Cisco, Fairchild, Fraunhofer IZM, Georgia Institute of Technology, Huazhong University, Hynix, IBM , IMEC, Infineon, Intel, ITRI, Kaist, NAMICS, Qualcomm, Samsung, SEMATECH, SPIL, STMicroelectronics, Sumitomo, Suss MicroTec, Taiwan Semiconductor, Tohoku University, Xilinx, Yole, others.

Who Should Attend? This course's target is the time-constrained participant with little or no extra time to constantly review daily news releases and/or attend major symposia/workshops to stay current with the latest technological developments in new advanced packaging technology. It emphasizes 2013 topics in 2.5D-TSV Interposers, 3D-TSV, Chip-Package-Interactions, Flip Chip, LED, MEMS, Microbumps, New Adhesives, Embedded Chips and is designed for all levels of engineering. It primarily includes advanced packaging concepts for senior engineers/scientists but since the course contains a short review of current single chip and advanced wafer levels of packaging, it is also ideal for entry-level technicians/engineers, QA, sales/marketing, purchasing, safety, administration, program management.

Attendees receive a 300+ page handout with key topics including comprehensive references.

Phillip Creter has over 30 years of microelectronics packaging experience. He is currently a consultant (Creter & Associates) gaining his microelectronics packaging experience at Polymer Flip Chip, Mini-Systems, and GTE. His past positions include GTE Microelectronics Center Manager, Process Engineering/Development Manager, Materials Engineering Manager, Manufacturing Engineer. He is a well-known presenter who has published technical papers in IEEE Transactions, Solid State Technology, High Density Interconnect, Circuits Manufacturing, Insulation Circuits, and others. He has chaired many technical sessions for symposia, has given hundreds of technical presentations, and is a U.S. patent holder. He has been developing/teaching college-level microelectronics courses since 1997 and has continuously taught professional development courses for online webinars and at various national microelectronics symposia. He is an active certified instructor for the Department of Homeland Security. He is a Life member of IMAPS. He was elected Fellow of the Society, National Treasurer and President of the New England Chapter (twice).

M7: Introduction to 3D Power Electronics & Post-Silicon Device Packaging
PDC Instructor: Dr. Douglas C. Hopkins, North Carolina State University

Course Description: Power densities and switching speeds in power electronics applications have increased well over ten fold in the last three years. With the advent of post-silicon power devices, i.e. SiC, GaN and GaAs, voltages and current densities are at unprecedented levels. The greatest change is in switching speeds that approach gigahertz. All this, and operating temperatures are pushing above 250C.

This course is an excerpt from a 45-hour university graduate course that introduces the evolving characteristics of the post-silicon devices; new "energy electronics" packaging materials; and new 3D printed power-packaging technologies. This daylong course presents a comprehensive approach from defining the new challenges facing power packaging to new packaging techniques for working at higher temperatures.

Half the course details more traditional power packaging techniques, such as directed-bonded-metal (Al - DBA and Cu - DBC) and limitations on their applicability to the new higher temperatures and speeds. The other half shows how microelectronics packaging technologies, such as 3D printing, and stack die and stacked boards, can be used in power applications for point of load converters, etc.

Who Should Attend? This course is focused toward packaging design engineers that must integrate power into digital and datacomm systems, or must create next-generation power modules.

Dr. Doug Hopkins is Professor and Director of the Laboratory for "Packaging Research in Electronic Energy Systems" as part of the NSF-funded FREEDM Systems Center at North Carolina State University in Raleigh, NC. He was formerly with SUNY Buffalo as Director of the "Electronic Power and Energy Research Lab". He received his Ph.D. from Virginia Tech, worked for GE's and Carrier's R&D Centers, and held visiting positions at several national labs. He is an IEEE senior member and IMAPS fellow. He is a founding member of IMAPS Subcommittee on Power Packaging, now chairs the technical subcommittee on Electronic Energy Packaging in IEEE-CPMT and member of the IEEE-PELS technical committee on Emerging Technologies. He has authored over 100 journal and conference publications, received three ISHM/IMAPS awards.

M8: Hermeticity Testing of Microelectronics for Aerospace and Medical Applications
PDC Instructor: Thomas J Green, TJ Green Associates LLC

Course Description: Hermeticity testing of microelectronic packages is critical for military, aerospace and medical implants. This course begins with an overview of hermetic sealing processes. Then the accepted leak test methods in Mil specs are described in detail, with an emphasis on the impact of tighter leak spec requirements. Issues with bomb times and pressures, measured leak rate vs air leak rates, helium desorption and other relevant issues will be addressed. The focus will be on practical issues facing the industry. The basic science and applicability of Optical Leak Test (OLT), Cumulative Helium Leak Detection (CHLD) and KR-85 radioisotope testing will be described with plenty of time for questions. The gas ambient inside the package as measured using Residual Gas Analysis (RGA) provides insight into the hermetic seal. The instructor provides numerous excel spreadsheets to help with the calculations (e.g. Howl and Mann equation). A brief review of the techniques and methods to evaluate a "near-hermetic" approach is presented along with a discussion of the pitfalls and issues of TM 1014 (Seal) and TM 1018 (Internal Water Vapor) as applied to a “near” or non-hermetic package. How to incorporate and use a micro moisture sensor inside the package will be reviewed in detail.

Who Should Attend? This PDC is intended for process engineers, designers, quality engineers, and managers responsible for sealing, leak testing and RGA test results for hermetic packages.

Thomas Green is the principle at TJ Green Associates LLC (www.tjgreenllc.com) a veteran owned small business focused on training and consulting for military, space and medical microelectronic devices. He has over thirty years experience in the microelectronics industry at Lockheed Martin and USAF Rome Laboratories. At Lockheed he was a Staff engineer responsible for the materials and manufacturing processes used in building custom high reliability space qualified microcircuits for military and commercial communication satellites. Tom has broad experience in all aspects of microelectronics packaging, specifically sealing and hermeticity testing. He has conducted experiments and presented technical papers at NIST and IMAPS on leak testing techniques and optimization of seam welding processes. Tom regularly attends EIA/JEDEC meetings and is an active member of IMAPS and a Fellow of the Society. He has a B.S. in Materials Engineering from Lehigh University and a Masters from the University of Utah.

M9: Reliability Data Analysis
PDC Instructor: Jianbiao Pan, California Polytechnic State University

Course Description: The objective of this course is to introduce the fundamentals of reliability concepts and enable the student to analyze reliability data and interpret the results. A hands-on training using statistical software Minitab or JMP will be provided as well.

Course outline:

  • Basic reliability concepts
    • The definition of reliability, MTBT, MTTF, failure rate, hazard rate, and bathtub-curve.
    • Different data types: right censored, interval censored, left censored, uncensored.
    • The most commonly used distributions in reliability engineering: exponential, lognormal, and Weibull.
  • Reliability data analysis
    • Reliability distribution identification: probability plotting
    • Parameter estimation
  • System reliability

At the end of this course, participants should be able to:

  • Describe basic reliability concepts and bathtub-curve; distinguish reliability data characteristics; and estimate reliability terms using empirical reliability data.
  • Fit statistical distributions using statistical software JMP or Minitab and interpret the failure mode based on estimated Weibull parameters.

Students are asked to bring along laptop computers with JMP or Minitab (free trial version available) to use during class.

Who Should Attend? Engineers, scientists, and managers in R&D, process/product development, and manufacturing who desire to conduct reliability testing and/or analyze reliability data.

Dr. Jianbiao (John) Pan is a professor in Industrial and Manufacturing Engineering Department at California Polytechnic State University, San Luis Obispo. He is an ASQ-Certified Quality Engineer and an ASQ-Certified Reliability Engineer. He received a PhD in Industrial Engineering from Lehigh University, Bethlehem, PA. His research interests include the materials, processes, and reliability of microelectronics packaging. His teaching interests include statistical data analysis, design and analysis of experiment, quality engineering, reliability engineering, and microelectronics and electronic packaging. He has authored or co-authored over 40 technical papers. He is a Fellow of IMAPS, a senior member of ASQ, IEEE, and SME. Dr. Pan is a recipient of the 2011 Outstanding Educator Award from the IMAPS. He is currently the Editor-in-Chief of Journal of Microelectronics and Electronic Packaging and a guest Associate Editor of IEEE Transactions on Components, Packaging and Manufacturing Technology.

M10: MEMS Reliability and Packaging
PDC Instructor: Slobodan Petrovic, Oregon Institute of Technology

Course Description: This course provides a comprehensive discussion of a broad array of MEMS packaging and reliability issues. An overview of the principles of operation, fabrication methods, and materials used in building MEMS structures will be presented as well. Because each MEMS device requires a distinctive packaging approach, practical examples and illustrations will be used to demonstrate uniqueness of solutions and interactions between micromachined structures and packaging.

A full range of MEMS devices will be discussed while a particular emphasis will be placed on sensors and actuators used in industrial, medical, and automotive applications. Extensive case studies that will be used to most effectively demonstrate diverse packaging principles for devices such as accelerometers, pressure sensors, and digital micromirror devices.

The course will be divided in 2 major sections: general MEMS competence; and packaging and reliability. The following major topics will be covered: fabrication technologies, materials, device physics, design considerations, main MEMS types, integration aspects, selected industrial application, types of packaging, quality control, reliability and failure analysis.

Who Should Attend? While some prior knowledge by the participants of MEMS in general is helpful, the packaging discussion will include a detailed explanation of the principles of operation, fabrication methods, and materials used in building MEMS structures. The course is therefore open to participants with no prior MEMS knowledge and would provide a reasonably broad general introduction into the field. The participants will have the opportunity to gain knowledge about MEMS in general through the eyes of a packaging and reliability specialist.

Dr. Slobodan Petrovic is an associate professor at the Oregon Institute of Technology in Portland, OR. His research interests are in the areas of MEMS fuel cells, sensor media compatibility, hydrogen generation and storage, and dye-sensitized solar cells. Prior to that, he was at the Arizona State University, where he taught courses in MEMS, Sensors, and alternative energy. Dr. Petrovic also held appointments at Clear Edge Power as a Vice President of Engineering; at Neah Power Systems as Director of Systems Integration; and Motorola, Inc. as a Reliability Manager. Dr. Petrovic has over 25 years of experience in MEMS, sensors, energy systems; fuel cells and batteries; and electrochemical solar cells. He has over 50 journal publications and conference proceedings; 2 book contributions and 24 pending or issued patents.

 

Thursday, October 3, 2013
All Thursday PDCs are 1/2 Day Courses (4-hours): 8:00 am - 12:00 pm

T1: Package on Package Technology - What It Is, What Works, What Doesn't Work
PDC Instructor: Dr. Ning-Cheng Lee, Indium Corporation

Course Description: This course covers Package on Package (PoP) Technology, including trends, designs, material selection, processes, and reliability. The approaches of enhancing the reliability will be discussed in details, including effect of fluxes, solder alloy types, processes, profiles, via designs, and ball sizes. Being the solution with the highest potential, epoxy flux will be introduced and will be compared with other solutions. Finally, head in pillow control at reflow soldering, particularly at PoP will be instructed. The control includes considerations on materials, processes, and designs.

Course Content:

  • Trends
  • Designs
  • Processes - General
  • Processes - Rework of PoP
  • Processes - Selection of Dip Transfer Fluxes and Solder Pastes for PoP Assembly
  • Processes - Low Volume PoP Assembly Process Development
  • Processes - Design for Efficient PoP Underfilling
  • Processes - Comparison of Various Polymeric Reinforcement Approaches for PoP/CSP
  • Reliability - One-Pass vs Two-Pass
  • Reliability - Effect of SOP & Material on Yield & Drop Test Performance
  • Reliability - Effect of Materials & Profiles
  • Reliability - Materials Selection & Parameter Optimization
  • Reliability - Mixed Alloy
  • Reliability - Effect of Coplanarity and Design
  • Reliability - Effect of Ball Size, Via Size, Alloy Type on Stack-up Height & Reliability
  • Reliability - Opens/Head-in-Pillow - The Primary Failure Mode of PoP

Who Should Attend? Anyone who cares about successful implementation of package on package technology, and like to know how to achieve it should take this course.

Ning-Cheng Lee is the Vice President of Technology of Indium Corporation of America. He has been with Indium since 1986. Prior to joining Indium, he was with Morton Chemical and SCM. He has more than 20 years of experience in the development of fluxes and solder pastes for SMT industries, plus experience in underfills and adhesives. He received his PhD in polymer science from University of Akron in 1981, and BS in chemistry from National Taiwan University in 1973. Ning-Cheng is the author of "Reflow Soldering Processes and Troubleshooting: SMT, BGA, CSP, and Flip Chip Technologies", and co-author of "Electronics Manufacturing with Lead-Free, Halogen-Free, and Conductive-Adhesive Materials". He was honored as 2002 Member of Distinction from SMTA, 2003 Lead Free Co-Operation Award from Soldertec, 2006 Exceptional Technical Achievement Award from CPMT, 2007 Distinguished Lecturer from CPMT, 2009 Distinguished Author from SMTA, and 2010 Electronics Manufacturing Technology Award from CPMT.

T2: Flexible Optical Media for High Data Rate Interconnections
PDC Instructor: Dr. How T. Lin, Endicott Interconnect Technologies, Inc

Course Topics:

  • Technical reasons for migrating to OI;
  • Light Fundamentals;
  • Optical Components for Light Emission, Detection and Transmission;
  • Optical Interconnect Principle;
  • Flexible Media for Optical Interconnects (Fiber Optics, Optical Waveguides - Fabrication and Assembly); and Summary.

Dr. How Lin is Chief Scientist in Endicott Interconnect. He has Doctoral degree in Electrical Engineering from Rensselaer Polytechnic Institute. He is well known in circle of electrical design, test, optical interconnect, signal integrity and high performance computing. He is also teaching computer science at Binghamton University.

T3: Understanding the Common Failure Modes from a Physics of Failure Perspective
PDC Instructor: Greg Caswell, DfR Solutions

Course Description: There are numerous failure modes and mechanisms that can impact a product. Understanding how they occur and how to obviate them during the design stage can vastly improve a product's ability to withstand the rigors of its intended environment.

This course will address the common failure modes associated with printed circuit boards,passive components, Integrated Circuits, High Brightness LEDs, QFNs, CSPs, PoP, and MEMs along with the effects of long term storage of components.

Physics of Failure (PoF) is a proactive science based philosophy that addresses material science, physics and chemistry and provides the basis for the student to develop an up-front understanding of failure modes/mechanisms. Knowing how things fail is equally important to understanding how and why things work by enabling engineers and designers to be knowledgeable about root causes of failures so that they can be designed out in new products.

PoF provides a scientific basis for evaluating usage life and hazard risks for new materials, structures and technologies when exposed to their actual operating conditions.

Examples of each failure mode/mechanism will be illustrated along with insight into methods for obviating them.

Who Should Attend? Engineers or designers who are developing new products and want to understand how to enhance their designs by developing an in depth knowledge of the various issues that can impact a product design if the wrong materials, packaging technologies, stress loads, or manufacturing processes are implemented.

Greg Caswell is widely recognized as a pioneer in surface mount technology (SMT) and has 40 years of experience in the electronics industry. Currently he is a Sr. Member of the Technical Staff for DfR Solutions. Previously he was the VP-Engineering for Reactive NanoTechnologies and VP Business Development for Newport Enterprises. His experience encompasses all aspects of SMT manufacturing, circuit board fabrication and materials, advanced packaging (BGA, uBGA, CSP, Flip Chip, QFN), IC fabrication processes and materials, solder reflow, RoHS, and bonding utilizing specialized nanotechnology. Greg, a Past President of IMAPS NA, was the National Chairman for the IMAPS Advanced Technology Workshop program from 1989-2000 and was the Editor in Chief for Advancing Microelectronics magazine from 2009-2012. He received his Bachelor of Science in Electrical Engineering from Rutgers University and also has a Bachelors in Management from St. Edwards University in Austin.

T4: Embedded Chip Packaging Technologies
PDC Instructor: Ray Fillion, Fillion Consulting

Course Description: Semiconductor process and device advances have provided ever more functionality in a smaller chip footprint and have driven both the high-end computing market and the portable electronics market. Advances in microelectronics packaging have become just as critical to these markets. These device advances come with an increase in device power requirement, cooling needs, I/O counts and voltage delivery sensitivity. Embedded chip approaches have been developed to address these devices advancements and packaging needs. This course will give an in depth look into embedded chip technologies.

It will start with a background overview of semiconductor advances for the past 40 years and they are effecting device power dissipation, supply current, I/O count and clock rate. It will look at the evolving packaging approaches that have occurred over the past 20 years. It will go into the various approaches used in SoP, SiP, MCP and MCM multichip technologies; 3-D technologies; wafer level package. This course will focus on single chip and multichip embedded chip technologies.

It will look at the basic features of embedded chip approaches, their construction and the processes used to fabricate and assemble them. It will look at the leading approaches to these technologies and their inherent advantages and disadvantages. This course will cover issues including yield losses, component handling and availability. The course will look at the leading companies implementing various versions of these technologies and cover the key differentiators between them.

Who Should Attend? This course covers basic and advanced topics for product and design engineers, manufacturing process and assembly/packaging engineers, engineering managers, senior design technicians, consultants and academic specialists as well as marketing and sales personnel requiring an understanding of the capabilities, implications and options of advanced packaging and assembly technologies.

A BSEE graduate of University of Massachusetts, Ray Fillion focuses in the areas advanced packaging and interconnection for next generation microelectronics systems. Ray has more than 40 years experience at GE in Aerospace Electronics and Global Research in all aspects of microelectronics in technical, management, business development and IP licensing positions. Mr. Fillion also has served on Advisory Boards for a variety of technical societies, industry, academic institutions and governmental funded agencies. He has taught courses on advanced packaging for IMAPS, SMTA, GE and several universities. Ray is now heads a consulting firm, Fillion Consulting, specializing in technical assessment of microelectronic technologies and IP including multichip modules, chip scale, 2.5D/3D, embedded chip and power packaging. He was the lead inventor of the GE embedded chip technology with most of his 32 issued US patents in that area. He has been active in a number of technical societies including IMAPS: Executive Council Director, Technical Committee Member, Session Chair, Presenter; ECTC: Technical Committee Member, Session Chair, Presenter; and Symposium of Polymers in Microelectronics: Board Member, Session Chair, Presenter. He has authored more than 125 technical papers, journal papers, and technical articles with three Outstanding Paper awards from the IMAPS International Conference.

T5: Practical Aspects of MEMS and Microsystem Packaging
PDC Instructor: Chip Spangler, Aspen Microsystems

Course Description: MEMS and Microsystem devices have seen remarkable growth in both high-volume commercial applications as well as lower-volume specialty applications. One of the key reasons for this growth is the advances made in package technologies and the related reductions in cost and improvements in device function that they enable. This class will provide practical guidance for those looking to leverage these advanced packaging technologies to help bring their products to market. The first portion of the class will set the context for microsystem packaging by exploring a diverse range of real-life applications and the packaging challenges they present. Case studies will be used for this exploration into inertial sensors, micro-displays, RF switches and components, print heads and fuel cells as well as medical packages for neural stimulation and DNA analysis. These case studies will focus not only on package design and system interfaces, but also the material and assembly process challenges they create. The second portion of the class will review the fundamentals of microelectronic package design and assembly process as adapted for MEMS and microsystem applications. Topics will include wafer dicing, die attach, wirebond and flip chip technologies as well as hermetic sealing and non-hermetic encapsulation methods.

Who Should Attend? This course is intended for designers, engineers and technical managers who would like to learn about practical aspects of packaging MEMS and microsystem devices. Through real-life case studies attendees will be given the tools needed to analyze the technical tradeoffs so that the products they are responsible for will meet functional, cost, reliability, size and quality requirements. This course will also be suitable for those who are looking for a broad introduction into the challenges of MEMS packaging. Practical information regarding materials, equipment and processes will provide a solid foundation for attendees to address the packaging challenges in their organization.

Dr. Chip Spangler received his Ph.D. in electrical engineering from The University of Michigan in 1988. He is currently President of Advanced Microsystems providing engineering services for advanced microelectronic devices, with specialties in MEMS package and assembly technologies. Previously Chip was the President and CTO of Aspen Technologies, a microelectronic package and assembly service supplier. He was responsible for developing package solutions for high-pixel count displays, DNA analysis products and MEMS telecom switch arrays as well as a variety of other MEMS devices. Before this, Chip worked at Ford Microelectronics where he had responsibility for pressure sensors, and airbag and chassis accelerometers. His work lead directly to the production of the world’s first plastic surface mount airbag accelerometer. Dr. Spangler is the author of over 30 technical publications and has 9 patents. He is currently an editor for IEEE JMEMS and has helped organize a number of MEMS technical conferences.

T6: Signal/Power Integrity Design for Electronic Packaging and 3D System Integration
PDC Instructors: Dr. Ivan Ndip, Fraunhofer IZM; Professor Ege Engin, San Diego State University; Dr. Antonio Ciccomancini Scogna, CST of America

Course Description: Efficient and low-cost design of electronic packages, PCBs and 3D integration technologies requires a good understanding of the root causes of signal integrity (SI), power integrity (PI) and electromagnetic interference (EMI) problems at GHz frequencies, as well as methods to analyze, prevent or solve them. The objective of this course is to illustrate a wide range of methods for electrical modeling, measurement and optimization of electronic packages, PCBs and 3D integration technologies, under consideration of SI, PI and EMI/EMC effects. Measurement techniques for extracting the relative dielectric constant and loss tangent of electronic packaging materials will also be discussed. Finally, design guidelines for system optimization will be provided.

Course Outline:

  • Introduction
    • Technologies for advanced packaging and 3D integration
    • High-speed design challenges
  • Signal Integrity Design and Optimization
    • Lossy transmission lines considering surface roughness and glass weave effect
    • Signal vias in organic and glass interposers
    • Through silicon vias (TSVs) in active and passive silicon for 3D integration
    • Efficient methods for performing signal integrity simulations, considering package/PCB co-simulation
  • Power Integrity Design and Optimization
    • Power-ground plane pairs
    • Decoupling capacitors and simultaneous switching noise (SSN)
    • Electromagnetic band gap (EBG) structures and photonic crystal power/ground layers (PCPLs) for suppressing SSN coupling
    • Efficient methods for performing power integrity simulations
  • Measurement and extraction of relative dielectric constant and loss tangent of packaging materials.

Who Should Attend? Engineers, scientists, researchers, designers, managers and technicians involved in the process of layouts, simulation, design, integration and optimization of electronic packages, PCBs and interconnections.

Dr. Ivan Ndip obtained his M.Sc., and Ph.D. with the highest distinction (Summa Cum Laude) in electrical engineering from the Technical University Berlin, Germany. In 2002, he joined the Fraunhofer-Institute for Reliability and Microintegration (IZM) Berlin as a Research Engineer and worked on signal integrity modeling and design as well as on antenna integration. Since 2006, he has been a Senior Research Engineer and Group Manager of RF & High-Speed System Design, where he's responsible for leading a team of Research Engineers and Graduate Students as well as for developing and leading research projects that focus on electromagnetic modeling, design and optimization of RF/high-speed packages/boards/modules, integrated antennas and passive RF front-end components.

Since 2008 Dr. Ndip has also been a Lecturer in the Department of High-Frequency and Semiconductor System Technologies, School of Electrical Engineering and Computer Sciences, Technical University Berlin. He is currently engaged in teaching courses on Numerical Techniques in Electromagnetics and on Electromagnetics for Design and Integration of Microsystems. He has more than 100 publications and has won 6 best paper awards at leading international conferences. Dr. Ndip is also a recipient of the Tiburtius-Prize, awarded yearly for outstanding Ph.D. dissertations in the state of Berlin, Germany.

Dr. Ege Engin received his B.S. and M.S. degrees in electrical engineering from Middle East Technical University, Ankara, Turkey, and from University of Paderborn, Germany in 1998 and 2001, respectively. He received his Ph.D degree with Summa Cum Laude from the University of Hannover, Germany in 2004. Dr. Engin has worked as a research engineer with the Fraunhofer-Institute for Reliability and Microintegration in Berlin, Germany and at Georgia Tech. He is currently an Assistant Professor in the Electrical and Computer Engineering Department of San Diego State University. He has more than 60 publications in the areas of signal and power integrity modeling and simulation and 4 patent applications. He has co-authored the book "Power Integrity Modeling and Design for Semiconductors and Systems," published by Prentice Hall in 2007.

Dr. Antonio Ciccomancini Scogna received the Laura and Ph.D. degrees in electrical engineering from the University of L'Aquila, L'Aquila, Italy, in 2001 and 2005, respectively. He is currently a Principal Engineer at Computer Simulation Technology (CST) of America, Framingham, MA. His research interests include electromagnetic compatibility numerical modeling, printed and integrated circuits, electromagnetic packaging effects, signal integrity and power integrity analysis in high-speed digital systems. He has authored or coauthored more than 50 publications in IEEE journal transactions, IEEE conference proceedings, and Electronic Design Automation (EDA) magazines. Dr. Ciccomancini is a member of Applied Computational Electromagnetic Society (ACES), Institution of Engineering and Technology (IET), EMC TC-9 and TC-10 Committees. In 2004, he received the CST University Publication Award for the use of the finite-integration technique in signal integrity applications. He is the recipient of DesignCon Finalist Best Paper Award in 2007 and DesignCon Best Paper Award in 2008.

T7: Managing the Effects of Mechanical Stress on Performance of Modern SOCS
PDC Instructor: Riko Radojcic, QTI Qualcomm

Course Description: The proposed course is intended to focus on the potential issues caused by mechanical stress in modern ICs, and specifically on the potential effects of stress on device parametric characteristics. With the current technology trends towards softer insulators and harder conductors, on and off the chip, and with the continued trend towards sub-mm overall component thicknesses, the distribution of strain precipitated by the CPI-driven stress, is expected to be significantly different than in the past. In addition, new features, such as TSVs, and new integration schemes, such as SiP solutions, introduce new sources of stress. This stress results in shifts og device performance and parametric characteristics - phenomena that are harder to detect and hence harder to fix than the traditional CPI issues, such as cracks and delamination. Consequently, this new class of CPI must be addressed proactively during product design. This course will describe the major components of an eco system developed to address this problem. The course is broken into three phases:

1. Product Challenges - a discussion of the various sources of CPI stress and the trends in the technology that make the modern SoC devices susceptible to strain. This portion will also address the challenges of including stress awareness in product design.

2. Modeling Challenges - a discussion of the various modeling methodologies, and a description of techniques used in the simulation tool. This portion will also define the material parameters required.

3. Material Characterization Challenges - discussion of the various characterization techniques for multi-scale materials data, particularly stress, and the selection of the specific solutions used. This portion of the course also describes a specific study conducted to validate the entire methodology.

Who Should Attend? - Chip and Package Design Engineers - Product Managers - Technology Integration Engineers - Failure Analysis Engineers - Reliability Engineers

Riko Radojcic is a Senior Director of Engineering at Qualcomm QTI, and a leader of 3D Technology team. Radojcic has more than thirty year's experience in the semiconductor industry; and held various positions as an independent consultant, and at PDF Solutions, Tality, Cadence, Unisys and Burroughs. Radojcic received his BSc and PhD from University of Salford, UK.

Valeriy Sukharev is a Technical Lead at the Design to Silicon Division of Mentor Graphics Corporation, Fremont, CA. Sukharev leads research and development of new full-chip modeling and simulation capabilities for the semiconductor processing and DFM/DFR applications. Prior to Mentor Graphics, Dr. Sukharev was a Visiting Professor with Brown University, Providence, RI, and a Guest Researcher with NIST, Gaithersburg, MD. He held senior technical positions at LSI Logic Advanced Development Lab, Milpitas, CA. He holds Ph.D. in physical chemistry from the Russian Academy of Sciences. Ehrenfried Zschech is Division Director at Fraunhofer Institute for Nondestructive Testing in Dresden. His responsibilities include micro- and nanoanalysis as well as R&D in the field of test systems. He received his diploma degree in solid-state physics and his Dr. rer. nat. degree from Dresden University of Technology. Zschech gathered experience in industry, during 17 years in several technical and management positions at Airbus and AMD. He holds honorary professorships for nanomaterials at the Brandenburg University of Technology in Cottbus and for nanoanalysis at the Dresden University of Technology. Zschech is acting as President of the Federation of European Materials Societies (FEMS).

T8: Introduction to the Design and Fabrication of RF, High Speed and Microwave Hybrids, MCM's and Modules
PDC Instructor: Tom Terlizzi, GM Systems LLC

Course Description: The course presents electrical and physical design, manufacturing, materials, quality and reliability information in terms understandable to engineering and non-engineering personnel. RF Packaging history, characteristics and drivers will be outlined. Types of packages (IC, chip scale, MEMS, Hybrid, MCM, Flip Chip, BGA, Aluminum and Kovar housings) and substrates (Thick and thin film, HTCC, LTCC ceramic, organic) and critical differences among them and their High Frequency applications (Microstrip, Stripline, Coplanar will be discussed. RF and Microwave layout and the commonly used design tools and software will be outlined. The course will look at the design selection to meet use and application environments. Step-by-step manufacturing flow for different packages and products will be presented as an example to understand the complexity of processes, materials and equipment involved in their manufacture. RF & Microwave packaging concepts will be introduced and the tradeoffs of different interconnect methodology (connectors, wire bonds, ribbon bonds, AuSi & AuSn eutectic, soft solder and epoxy. Materials selection with respect to thermal resistance will be discussed. Finite Element and reliability software will be discussed to insure the design will perform to specification. Quality and reliability issues related to RF packaging and their present and future solutions will be outlined.

Who Should Attend? - It will help the attendees to understand the application and assembly of Rf and Microwave microelectronic package technology on the next level interconnect and the service environment that microelectronic packages must protect its components. Personnel (Design engineers and process engineers) entering the RF microelectronic packaging field will have a critical look at the electrical design, physical design, layout quality, reliability and material issues related to the development and manufacture of microwave modules. Non-packaging personnel will learn the ins and outs of RF packaging. Non-technical personnel will learn the material and manufacturing intricacies of RF and Microwave microelectronic packages and the associated buzzwords used to describe them.

Tom Terlizzi is VP at GM Systems, a Management and Technology consulting firm, providing Microelectronic Business & Technology plans, , Marketing & Sales strategy, Product development for microelectronic projects and business proposal support. He has designed and developed Power management systems, Single board computers, microelectronic circuits, hybrids, COB modules, ICs, RF modules, for over 30 years for military, aerospace, telecom and consumer markets as a VP/GM, Director of marketing, Chief Engineer, Operations/Engineering manager at Aeroflex, Norden/UTC, G.I. Microelectronics and Grumman. He spearheaded acquisitions of several high tech companies,ISO9000/Mil-PRF-38534 quality certifications. He received a BEE from CCNY, a MSEE from NYU-Poly & has published several articles, papers and tutorials at international conferences, edited books on electronic packaging, consulted for the DoD on advanced RF electronic packaging. Tom was the Metro ISHM Chapter President in 1983 and in his free time also writes a Blog for EDN Magazine Online - Looking @ electronics.

 

Register On-Line

PDC registration is listed under SESSIONS
during the on-line registration process

Only 30 Exhibits Remain at IMAPS 2013 Orlando    ^ Top

Reserve Booth(s): Download PDF of Booth Application
For questions or to submit booth applications (via email), contact
Brian Schieman, bschieman@imaps.org, or 412-368-1621.

IMAPS 2013 is the largest symposium related to the microelectronics packaging industry in the world. IMAPS 2013 will feature a powerful technical program, a state-of-the-art exposition, progressive professional development courses, another informative Global Business Council Marketing Forum and many other events and activities to share the latest developments in microelectronics. We will hold this year's exhibition at the Rosen Centre HOTEL. Being in a smaller venue will allow us to negotiate more with the venue and our decorator to help keep costs down for you, the exhibitor!

The Annual IMAPS Symposium attracts approximately 1,200 attendees who represent all facets of the microelectronics and electronic packaging industries. These include: engineers, technicians, R&D, purchasing, manufacturing, management, and many more. They represent the automotive, communications, medical, aerospace, computer, defense, homeland security and consumer industries.

Exhibiting at IMAPS enables you to:

  • Reach over 1,200 buyers and specifiers in one place
  • Generate exposure in this highly competitive marketplace
  • Launch new products and concepts to the market
  • Enhance relationships with existing customers

Thank you to the current 2013 Exhibitors!

Exhibitor Contact name
Booth
Booth Type
Booth Category
3D Plus USA
Emond Mich
201
10 x 10
Corner
ACM Research, Inc.
Lee Michael
421
10 x 10
In-Line
AdTech Ceramics
Wade Jim
614
10 x 10
In-Line
Advance Reproductions Corp.
Robinson Don
522
10 x 10
Corner
Advanced Dicing Technologies
Eichhorn Mark
517
10 x 10
In-Line
AI Technology, Inc.
Boersig Charlie
400
10 x 10
Corner
Alabama Microelectronics Science & Technology Center
Hamilton Michael
627

10 x 10
Research Corridor

In-Line
ancosys Inc.
Pye Graham
805
10 x 10
In-Line
Besi North America, Inc.
Kok Alice
704
10 x 20
Corner
Binghamton University IEEC
Santos Daryl
726

10 x 10
Research Corridor

Corner
Ceradyne VIOX, Inc.
Brown Harlan
717
10 x 10
Corner
CeramTec North America
Christensen Robert
307
10 x 10
In-Line
Colorado Microcircuits, Inc.
Thalman Gary
315
10 x 10
In-Line
Conductive Containers Inc. (CCI)
Loggins Tom
313
10 x 10
In-Line
CVInc.
Collier Terence
317
10 x 10
In-Line
Deweyl Tool Inc..
Palmer Johanna
316
10 x 10
In-Line
DuPont Microcircuit Materials
Vernon Joan M
520
10 x 10
In-Line
East China Research Institute of Microelectronics
Wang Tony
311
10 x 10
In-Line
Element Six Technologies US Corp.
Obeloer Thomas
308
10 x 10
In-Line
Endicott Interconnect Technologies, Inc.
Orband James
200
10 x 10
Corner
ENrG, Inc.
Olenick John
215
10 x 10
In-Line
Epoxy Technology, Inc.
McCabe Joseph D
622
10 x 10
Corner
ESL ElectroScience
Chambers Drew
808
10 x 10
Corner
F & K Delvotec, Inc.
Bailey Rick
405
10 x 20
Corner
Ferro Corporation
Stadnicar Edward
615
10 x 20
In-Line
Finetech, Inc.
Gerard Adrienne
508
10 x 10
Corner
Fraunhofer Institute for Ceramic Technologies and Systems IKTS
Pohontsch Fanny
526

10 x 20
Research Corridor

Corner
Fraunhofer Institute for Reliability and Microintegration IZM
Weigelt Georg
426

10 x 20
Research Corridor

Corner
Gannon & Scott
Conway Raymond
207
10 x 10
In-Line
Geib Refining Corporation
Gervais Michael T
609
10 x 10
In-Line
Gel-Pak/Quik-Pak
Nunes Jennifer
518
10 x 10
In-Line
General Metal Finishing Co., a unit of Precision Engineered Products
Chatfield Stephen
310
10 x 10
In-Line
Haiku Tech, Inc.
De Moya Martin I
417
10 x 10
Corner
Harrop Industries, Inc.
Timmel Paul
714
10 x 10
In-Line
Hary Manufacturing Incorporated
Hary Paul
500
10 x 10
Corner
Heraeus Thick Film Division
Yin Yin
504
10 x 20
Corner
Hesse Mechatronics, Inc.
Bubel Joseph S
605
10 x 20
Corner
Hi-Rel Laboratories, Inc
Devaney Roger M
612
10 x 10
In-Line
IBM Microelectronics Division
Hochlowski Barry
418
10 x 10
In-Line
Indium Corporation
Cruz-Griffith Victoria
409
10 x 10
Corner
Infinite Graphics
Maitland Pete
206
10 x 10
Corner
Interconnect Systems, Inc.
Andrews Abby
406
10 x 10
In-Line
Kulicke & Soffa Industries, Inc.
Frese Sheila
705
10 x 10
Corner
Kyocera America, Inc.
Labadie Iris
616
10 x 10
In-Line
LINTEC of America
Campbell Stuart
521
10 x 10
In-Line
LORD Corporation
Greig Jim
600
10 x 20
Corner
Metallix Refining, Inc.
Woolley Micki
618
10 x 10
In-Line
Metalor Technologies
Imhof Howard
807
10 x 20
Corner
Micro Hybrid Dimensions, Inc.
Spradlin Greg
414
10 x 10
In-Line
MicroScreen LLC
Wise Wallace Holly
523
10 x 10
Corner
Micross Components
Smith Scott
721
10 x 20
Corner
Midas Technology, Inc.
Towl Kenneth
803
10 x 10
Corner
Minco Technology Labs, LLC
Cooper Kristi
309
10 x 10
In-Line
Mini-Systems, Inc.
Tourgee Craig
412
10 x 10
In-Line
NAMICS Corporation
Jensen Richard C
611
10 x 10
In-Line
Natel Electronic Manufacturing Services, Inc.
Angeloni James A
505
20 x 20
ISLAND
Neu Dynamics Corp.
Johnson Don
712
10 x 10
In-Line
Newport Corporation
Medernach Jon
416
10 x 10
In-Line
NorCom Systems, Inc.
Aubertin Chris
613
10 x 10
In-Line
Nordson DAGE
Kardjian Aram
701
10 x 10
Corner
nScrypt, Inc.
Brownell Beth
716
10 x 10
Corner
NTK Technologies, Inc.
Stoops Mariel
719
10 x 10
In-Line
Oneida Research Services, Inc.
McEwen James
422
10 x 10
Corner
Pacific Trinetics Corporation
Meshkin Neda
621
20 x 20
ISLAND
Palomar Technologies, Inc.
Sylvester Jessica
511
10 x 20
Corner
Perfection Products, Inc.
Vickery John
515
10 x 10
In-Line
Photofabrication Engineering, Inc.
Grande Judy
318
10 x 10
In-Line
Plasma-Therm, LLC
Messineo Nancy
111
10 x 20
ISLAND
Polysciences, Inc.
Gidzinski Ashley
620
10 x 10
In-Line
Prince & Izant Co.
Faulhaber Nancy
105
10 x 10
Corner
Reldan Metals Co.
Whitaker Kathleen
305
10 x 10
Corner
Riv, Inc.
Keefe Tania M
700
10 x 10
Corner
Royce Instruments, Inc.
Cox Diane
516
10 x 10
Corner
Rudolph Technologies
Pauling Amy
519
10 x 10
In-Line
Sales and Service, Inc.
Winn Chris
314
10 x 10
In-Line
SANTIER Thermal Management Solutions
Loomis Tom
420
10 x 10
In-Line
Sefar, Inc.
Potratz Christine
204
10 x 10
Corner
Semi Dice, Inc.
Minter Darin
707
10 x 10
In-Line
Semiconductor Equipment Corporation
Moore Donald I
410
10 x 10
In-Line
Sikama International, Inc.
Skeen Phil
816
10 x 10
Corner
SMART Commercialization Center for Microsystems
Apanius Matt
626

10 x 10
Research Corridor

Corner
Sonoscan, Inc.
Lykowski Janet
709
10 x 10
Corner
Souriau PA&E
Kalkowski Rick
610
10 x 10
Corner
SST International
Wilson Bruce A
304
10 x 20
Corner
Stellar Industries Corp.
Snook John B
401
10 x 10
Corner
TDK Corporation
Lambeth Sara
804
10 x 10
Corner
Technic, Inc.
Roza Drew
205
10 x 10
Corner
Teledyne Microelectronic Technologies, Inc.
Fletcher Sharon
501
10 x 10
Corner
Torrey Hills Technologies, LLC
Zhang Joyce
408
10 x 10
In-Line
Towa Corporation
Tripp Lloyd
312
10 x 10
In-Line
Trebor Instrument Corp.
Grzesiak Margaret
404
10 x 10
Corner
Tresky Corporation
Weil Allen
708
10 x 20
In-Line
West Bond, Inc.
Straight Randy
300
10 x 10
Corner
XYZTEC
Haley Tom
423
10 x 10
Corner
Zeon Corporation
Shoulders Kimberly
419
10 x 10
In-Line
Booth Count: 115

 

Calling all Golfers!    ^ Top

19th Annual IMAPS Golf Classic
to benefit The Microelectronics Foundation

Monday, September 30, 2013
8:00am Shotgun Start - "Best Ball" Scramble

Shingle Creek Golf Club
9939 Universal Blvd | Orlando, Florida 32819
407-996-9933 |
www.shinglecreekgolf.com

Shingle Creek - Hole 8

The IMAPS Microelectronics Foundation Fall Golf invitational will be held at the Shingle Creek Golf Club. Experience this remarkable new orlando golf course, which takes its name from the pristine creek, which traverses the property. Early Central Florida settlers, circa 1800, were drawn to the area by the abundance of game, fishing, ancient cypress trees, and of course, the beautiful creek.

Cost is $125 per person.

$450 for a team of four; $750 for a team of four including a hole sponsorship.
$500 for one individual golfer and 1 hole sponsorship.

The cost includes: Transportation to and from the course, greens/cart fees, shotgun start, and a breakfast/lunch -- TBD.

All proceeds from this event will benefit the IMAPS Microelectronics Foundation.

Special Awards and Activities tentatively planned:

  • Closest to the Pin;
  • Longest Drive
  • Mulligans for sale!

Golfers will tee off shortly after arriving at the course. Times are tentative and will be confirmed before the outing. Callaway rental clubs are available for $50 plus tax.

 

Golf fees and hole sponsorships under SESSIONS during on-line registration...
Register On-Line


Sponsorship Opportunities:

Eagle Sponsor - $3,000

  • Entrance of two four-somes.
  • Includes three hole sponsorships with signage.
  • Company logo/name on all event promotional signs, materials and website.
  • Company may provide take-away products to be handed to all golfers. Golf-related items usually most appropriate (e.g., golf towels, balls, tees, etc.). At expense of sponsor.

Birdie Sponsor - $1,500 -- 1 SOLD

  • Entrance of one four-some.
  • Includes one hole sponsorship with signage.
  • Company logo/name on all event promotional signs, materials and website.
  • Company may provide take-away products to be handed to all golfers. Golf-related items usually most appropriate (e.g., golf towels, balls, tees, etc.). At expense of sponsor.

Hole Sponsor - $500 ($750 w/ four-some) -- 17 Holes Remain

  • Sponsorship of one hole with signage.
  • Entrance of one golfer ($500) or one four-some ($750).
  • Company logo/name on promotional materials and website.

 

Sponsors receive signange, on-line recognition, and other benefits as defined on the sponsorship page. Contact David Virissimo, IMAPS 2013 Foundation Chair, with questions - David.Virissimo@ametek.com. Or contact Brian Schieman, IMAPS, at bschieman@imaps.org.

Golf Sponsors
"Birdie" Sponsor &
Hole Sponsor:

LORD - Golf "Birdie" Sponsor
Hole Sponsor: Golf Hole Sponsor: Coining Inc/Ametek
Hole Sponsor:
Golf Hole Sponsor: Infinite Graphics

 

Thermal Management 2013 Workshop - Abstracts Due September 1   ^ Top
IMAPS will hold its Advanced Technology Workshop and Tabletop Exhibit on Thermal Management at the Toll House in Los Gatos, California from November 5-7, 2013. Abstracts are due September 1, 2013. Visit the workshop website at www.imaps.org/thermal for more details.

Exhibit information available soon. Contact bschieman@imaps.org if you wish to reserve one of the limited number of tabletops available at the Toll House.

The purpose of this Workshop organized each year by IMAPS is to promote presentation and discussion of leading-edge developments in thermal management components, materials, and systems solutions for removing, spreading, and dissipating heat from microelectronic devices and systems. The Workshop emphasis is for practical, high-performance solutions intended to meet current and evolving requirements in power electronics, military/aerospace, computing, and telecom systems. Single-company product development concepts are acceptable subjects; however, all abstracts will be judged on novel and innovative contributions to the industry knowledge.

This Advanced Technology Workshop and Tabletop Exhibition on Thermal Management has been held since 1992, and is considered to be one of the most successful of the IMAPS ATWs that are held each year. Information will be available on transportation methods by train and/or bus from area airports.

Speakers are expected to attend the entire Workshop to maximize opportunities for interaction with registered attendees. Every year, authors and attendees find this IMAPS Workshop format to be a proven forum for highly effective networking between attendees and speakers. Speakers pay a reduced registration fee, making participation even more beneficial.

ABSTRACTS ARE SOLICITED IN THE FOLLOWING AREAS:

  • Market Drivers:  Thermal challenges and business and economic drivers which influence change in electronic systems design and manufacturing. Developing market trends, market segmentation, cost drivers, and reliability factors are examples of topics that are included in this session. Such market and business data sets the framework for new technical solutions.
  • Thermal Interface Materials and Testing:  Developments in thermal materials for high-performance processors, memory, telcom, IGBT, RF, and microwave components and systems. Standards for testing and reliability. Organic, metallic, metal, graphitic, and other forms of TIMs are included, as well as developments with nanomaterials.
  • CTE-Matching and High Thermal Conductivity Materials:  Metallic, ceramic, and other composite materials with excellent thermal conductivity and coefficient of thermal expansion targeted to that of GaN, SiC, silicon, or ceramic materials. 
  • Stacked-Die and Device Packaging:  Chip-level packaging, including System-In-Package, Multi-Chip Module and Multi-Package Module, stacked-die and related thermal and interconnect challenges.
  • Liquid, Phase-Change, and Refrigeration Cooling:  Performance, flexibility, reliability, and serviceability improvements.
  • System Cooling:  Component- and system-level thermal management solutions for high-performance computing systems.
  • Data Center Cooling:  Cooling provisioning, airflow, temperature distribution, and migration paths to system liquid cooling.
  • Power Semiconductor Thermal Components, Systems, and Solutions:  Discrete and multichip IGBT packaging.
  • Mil/Aerospace:  Thermal management solutions for emerging and future military and aerospace components and platforms.
  • Telecommunications Systems:  Component- and system-level thermal management solutions for high-performance telecommunications systems.
  • Consumer Electronics:  Component- and system-level thermal management solutions for stationary and mobile systems, including displays, desktop and notebook computers, and handheld devices.

PREPARATION OF ABSTRACT:
Speakers should submit one copy of a two-paragraph abstract describing their proposed 25-minute presentation no later than September 1, 2013. No formal technical paper is required.

Abstracts must be submitted on-line at http://www.imaps.org/abstracts.htm.

A post-conference CD containing the full presentation material as supplied by authors will be mailed approximately 15 business days after the event to all attendees.  Presentation material must be submitted onsite no later than November 7, 2013, and will be included on the post-conference CD.

Questions:  Brian Schieman with questions bschieman@imaps.org or 412-368-1621. You may also contact the workshop chairs.

 

  Chapter Activities (events listed in chronological order)
 

IMAPS France - EMPC 2013 Begins September 9...Get Registered    ^ Top

Reminder: Registration for EMPC 2013 conferences are in progress!

Please use the following address: www.empc2013.com to view conference programme and for registration.

EMPC is one of the largest European conferences relating to semiconductor packaging and assembly.

When coming, you will enjoy a world-class 3-day conference with:
-more than 120 conferences in parallel technical sessions
-poster sessions
-a large exhibition hall with 57 booths.
-tutorials, social and additional technical events : INEMI Workshop

Don't miss  the opportunity to be part of this event!

Looking forward to welcoming in Grenoble!
...........................................................
Sincères Salutations/Best regards

Florence VIRETON
Tél: 33 (0) 1 39 67 17 73
email:imaps.france@imapsfrance.org

Carolinas Chapter Revival Meeting September 13    ^ Top
Save the date!

The planning committee composed of Dr. John Lannon and Alan Huffman of RTI International, Dr. Phil Garrou of NCMC and Michael O’Donoghue of IMAPS staff announces the Carolinas Chapter revival meeting on Friday, September 13, 2013. Please mark your calendars!

Carolinas Chapter Revival Meeting
Friday, September 13, 2013
11:30am - 5:00pm

Conferences Rooms A & B
RTI International
The Center for Materials and Electronics Technologies
3040 East Cornwallis Road
Research Triangle Park, NC 27709

Lunch will be provided complimentary to members and $10 for non-members.

An exciting program is currently in development. If you are interested in submitting ideas or recommendations for presentations or chapter development, please contact us.

Furthermore, Dr. Rex Anderson of RTI International has stepped forward to volunteer his time as chapter President. Members interested in serving as part of the chapter officer team should plan to attend this revival meeting.

More details will follow soon. Please contact the planning committee with any questions, comments, or suggestions. We look forward to seeing you in September.

Dr. John Lannon
lannon@rti.org

Alan Huffman
Huffman@rti.org

Phil Garrou
philgarrou@att.net

Michael O’Donoghue
modonoghue@imaps.org

IMPACT-IAAC 2013 - Agenda, Registration Now On-Line    ^ Top
Submit Your Abstract Before June 15!

In order to avoid dangerous climate change, provide sustainable green energy and better life for global population, the ICT products and services need to gain further effective improvements in system performance and integration, and innovate to reduce environmental impact. Over the past years, IMPACT conference, a remarkable platform, continually pay attention to the latest trends of global micro-system, packaging and circuit technology, and encourage the development and research of new materials, processes and designs in realizing the versatile system demands for advanced consumer, communication, cloud & mobile computing, medical and automobile applications.  

IMPACT sincerely welcomes you to IMPACT-IAAC 2013 Joint Conference which will be held in conjunction with TPCA Show 2013 on 22nd -25th at Taipei Nangang Exhibition Hall. This year, the 2nd IAAC (IMAPS All Asia Conference) is rotated in Taiwan, and a joint international conference of IMPACT and IAAC is organized by IEEE CPMT-Taipei, iMAPS-Taiwan, ITRI and TPCA. To cater for the technology trends, the theme of IMPACT-IAAC 2013 highlights “Green & Cloud: Creating Value and Toward Eco-Life” and will arrange Panel Sessions, invited talks, industrial sessions and outstanding paper presentations. Furthermore, IMPACT keeps collaborating with International organizations such as ICEP from Japan and iNEMI from U.S.A. We hope this Conference to be successful and to become an important and valuable resource under your contribution and participation.

Conference: IMPACT-IAAC 2013
Exhibition: TPCA Show 2013
Theme: Green & Cloud: Creating Value and Toward Eco-life
Date: Oct 22 (Tue.)-25(Fri.), 2013
Venue: Taipei Nangang Exhibition Hall
Website:http://www.impact.org.tw

Save The Date for the Next Cleveland/Pittsburgh Chapter Meeting: October 29    ^ Top
Save the date!

The planning committee for the Cleveland/Pittsburgh Chapter has confirmed that the next Chapter Meeting will be held Tuesday October 29 at Valtronic Technologies (USA), Inc. at 29200 Fountain Pkwy, Solon, OH 44139. The meeting will focus on medical device packaging topics - details soon.

 

  Membership Corner
 

Journal of Microelectronics and Electronic Packaging 2nd Quarter 2013 On-Line - Q3 Available Soon   ^ Top

Journal of Microelectronics
and Electronic Packaging

(ISSN # 1551-4897)

Volume 10, Number 2
Second Quarter 2013

download pdf of full Journal - 45mb



Development of Silver Nanoparticle Ink for Printed Electronics
Yiliang Wu, Ping Liu, and Tony Wigglesworth, Xerox Research Centre of Canada

49

Reliability Assessment of a New Power Electronics Packaging Material: Silver Diamond Composite
M. Faqir, J. W. Pomeroy, T. Batten, and M. Kuball, University of Bristol; M. Faqir, Université Internationale deRabat (UIR); T. Mrotzek and S. Knippscheer, Plansee SE; O. Vendier and S. Rochette, Thales Alenia Space; M. Massiot and L. Letteron, Egide, Site Industriel du Sactar; J. M. Desmarres and F. Courtade, CNES

54
Eutectic Zn-Al Die Attachment for Higher Tj SiC Power Applications: Fabrication Method and Die Shear Strength Reliability
Satoshi Tanimoto, Kohei Matsui, Yusuke Zushi, Shinji Sato and Yoshinori Murakami, R&D Partnership for Future Power Electronics Technology (FUPET) c/o AIST; Satoshi Tanimoto, Kohei Matsui, Yusuke Zushi and Yoshinori Murakami, Nissan Motor Co., Ltd.; Shinji Sato, Sanken Electric Co., Ltd.; Masato Takamori and Takashi Iseki, Sumitomo Metal Mining Co., Ltd.
59

High Temperature Characterization up to 450°C of MOSFETs and Basic Circuits Realized in a Silicon-on-Insulator (SOI) CMOS Technology
K. Grella, S. Dreiner, A. Schmidt, W. Heiermann, H. Kappert, H. Vogt, and U. Paschen, Fraunhofer Institute for Microelectronic Circuits and Systems, IMS

67

The Distribution and Transport of Alpha Activity in Tin
Brett M. Clark, Honeywell Electronic Materials

73
Combined Temperature and Vibration Testing for Wire Bond Interconnections in Harsh Environment Electronics
M. Mirgkizoudi, C. Liu, and P. P. Conway, Loughborough University; S. Riches, GE Aviation Systems-Newmarket
80
   

Torrey Hills Technologies

Oneida Research Services

Metallix

2013 Events:

IMAPS 2013 (Orlando)
September 29-Oct. 3
*Exhibitors contact bschieman@imaps.org

Thermal Management 2013
Nov. 5-7
*Exhibitors contact bschieman@imaps.org

2014 Events:

Wire Bonding 2014
Jan. 21-22
*Exhibitors contact bschieman@imaps.org

Device Packaging 2014
Mar. 10-13
*Exhibitors contact bschieman@imaps.org

High Temperature (HiTEC 2014)
May 13-15
*Exhibitors contact bschieman@imaps.org

^ Top

 
 
 
 
 
 
 
 
 
 
 
 
 
 

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