Device Packaging 2013 - Program Available Tomorrow! 1 Booth Remains... (read more...)
February 8 Early Registration & Hotel Deadlines for Device Packaging 2013 - Book On-Line ASAP (read more...)
10 Professional Development Courses (PDCs) Available in March on 3D, Flip Chip, MEMS, High Temperature Electronics and more... (read more...)
Join Us for the 2013 IMAPS Microelectronics Foundation Spring Golf Invitational This March (read more...)
Upcoming Webinar - Intro to Micro... (read more...)
High Temperature (HiTEN 2013) - Abstracts Still Being Accepted - Exhibits, Registration and Sponsorships Now Open (read more...)
CHAPTER ACTIVITIES (events listed in chronological order)
New England Chapter Dinner Presentation on February 5 (read more...)
Register by THIS FRIDAY for the Viking Chapter February 5 Technical Presentations and Facility Tour at Benchmark Electronics in Rochester (read more...)
Central Texas Chapter's Electronics Design & Manufacturing Symposium Tuesday, February 5 (read more...)
Northern California Chapter February 6 Lunch Presentation on 2.5D Interposer Fabrication for the Rest of Us (read more...)
IMAPS France 8th European Advanced Technology Workshop on Micropackaging and Thermal management (read more...)
2nd Southeastern Microelectronics Packaging Conference - Registration and Exhibits Filling Fast! (read more...)
New England Chapter's 40 Symposium & Expo - Call For Papers (read more...)
Advancing Microelectronics January/February 2013 Magazine Now On-Line - Bumping & Wafer Level Packaging... (read more...)
Journal of Microelectronics and Electronic Packaging 3rd Quarter 2012 On-Line - Q4 and Q1 2013 Available Soon (read more...)
||IMAPS Events (view full Web Calendar)
Device Packaging 2013 - Program Available Tomorrow! 1 Booth Remains... ^ Top
IMAPS 9th International Conference and Exhibition on Device Packaging will be held at the Radisson Fort McDowell Resort in Fountain Hills, Arizona from March 11-14, 2013. Visit www.imaps.org/devicepackaging this week to register, view the program and more. The PROGRAM will be online tomorrow.
Device Packaging 2012 was another great conference. The exhibit hall sold again for the 7th consecutive year. We saw an increase in attendance with more than 560 participating in 2012. 8x10 exhibit booths are also available - only 1 remains! We are again limited to 65 booths and expect to sell-out EARLY for the 8th consecutive year. Contact Brian Schieman at email@example.com with any questions or if you wish to speak, attend, sponsor and/or exhibit.
February 8 Early Registration & Hotel Deadlines for Device Packaging 2013 - Book On-Line ASAP ^ Top
IMAPS 9th International Conference and Exhibition on Device Packaging will be held at the Radisson Fort McDowell Resort in Fountain Hills, Arizona from March 11-14, 2013. Visit www.imaps.org/devicepackaging this week to register, view the program and more. The early registration and hotel deadlines are February 8. Registration fees increase after this date and IMAPS cannot guarantee the hotel room availability or pricing after this time.
10 Professional Development Courses (PDCs) Available in March on 3D, Flip Chip, MEMS, High Temperature Electronics and more ^ Top
IMAPS 9th International Conference and Exhibition on Device Packaging will be held at the Radisson Fort McDowell Resort in Fountain Hills, Arizona from March 11-14, 2013. Visit www.imaps.org/devicepackaging this week to register, view the program and more.
For those wishing to broaden their knowledge of device packaging, a selection of half-day courses will be offered on Monday, March 11th, preceding the technical conference (and for an additional registration fee). Morning PDCs will run from 8:00am until 12:00 noon. Afternoon PDCs will be held from 1:00pm until 5:00pm. The Welcome Reception will immediately follow the PDCs from 5:00pm until 6:30pm in the foyer. A Microelectronics Foundation Texas Hold-em Tournament will be held this year from 7:00pm until 10:00pm (TBD).
When you register on-line for these courses, you should first select your Device Packaging Conference registration category on page 1, and then under SESSIONS (page 2 of registration) you will select your PDCs. If you DO NOT plan on attending the conference (Tuesday-Thursday), then simply select EXHIBITS ONLY on page 1 ($0 charge) and then select your PDCs on page 2. Contact firstname.lastname@example.org with questions..
Morning Professional Development Courses
8:00 am - Noon
Monday, March 11
PDC1: 2.5D/3D, Flip Chip WLP, MEMS & LED Packaging Trends, Updates & Advances
Course Leader: Phillip G. Creter, Creter & Associates
This NEW overview focuses on the four technical topics of this 2013 Device Packaging Conference, independently reviewing leading edge technical developments featuring the latest in microelectronics updates/trends.
Specific topics from 2012-1Q2013 conferences, technical papers, news reports:
- 2.5D/3D (Status/market, wide I/O memory stacking, polymer isolated TSVs, silicon bridge TSVs, fusion glass substrates, wafer adhesives, thin stacking, test vehicle demos, self-assembly).
- Flip Chip Wafer Level Packaging (Status/market, fine pitch copper pillars, electromigration, intermetallic compound studies, non-conductive film used in wafer level underfill, low cost FC-PoP, electromigration of lead free solder bumps).
MEMS (Status/market, challenges, novel approaches, hermetic wafer level packaging, drop reliability, flex adhesive).
LED Packaging (Status/market, high power heat sinks/die attach material, novel encapsulants, silicon/glass/GaN substrates).
Technical innovations related to the above topics presented with input from leading industrial/academic institutions: Advanced Semiconductor Engineering/ASE, Altera, Amkor, CEA-Leti, Corning, DELO, Georgia Institute of Technology, Global Foundries, Hitachi, Hong Kong University, IBM, IFTLE, Intel, ITRS, Karlsruhe Institute, Microsystems, NAMICS, National Tsing Hua University, Oracle, Philips Lumileds, Qualcomm, Samsung, Sandia National Labs, Sematech, Solid State Technology, Siliconware Precision Industries/SPIL, TechSearch, Tohoku University, Toray, Toshiba, University of California, Wuhan National Laboratory for Optoelectronics, Xilinx, Yole and others.
Emphasis on visual aids (photos, figures, videos) with pass-around microcircuit samples. An invaluable handout includes over 100 references.
Who Should Attend?
Designed primarily for all engineers, scientists and others interested in an up-to-date overview of new developments in 3D, Flip Chip, MEMS and LED. The course uses simple terms and many graphics and figures to describe these elements of advanced packaging for those who are new to the field and needing a running start in these four focused areas of packaging technology. Ideal for entry-level technicians and engineers but also for people in quality assurance, sales, marketing, purchasing, safety, administration and program management since it also includes a short review of current single chip and advanced wafer levels of 3D packaging.
Phillip Creter is a consultant (Creter & Associates) with 30 years of microelectronics experience at Polymer Flip Chip, Mini-Systems, GTE, Itek Corporation. Past positions at GTE included Microelectronics Center Manager (received GTE Corporate Lesley Warner Technical Achievement Award), and Principal Investigator of GTE IR&D Projects. Other positions elsewhere included management in Projects/Process Engineering, Process Development, Materials Engineering/Manufacturing Engineer, receiving many awards of distinction. Creter has been teaching college-level microelectronics courses since 1997. He has continuously taught PDCs since 2004 for online webinars and national microelectronics symposia/workshops. He is a well-known presenter having published technical papers in IEEE Transactions, Solid State Technology, High Density Interconnect, Circuits Manufacturing, Insulation Circuits, others. He has chaired many technical symposia sessions, given numerous technical presentations, is a US patent-holder. He is an active certified Department of Homeland Security instructor, a Life member of IMAPS, elected Fellow of the Society, and has held several executive committee offices both locally/nationally.
PDC2: Recent Advances in Glass and Silicon Interposers for 2.5D and 3D Integration
Course Leader: Venky Sundaram, Georgia Institute of Technology (PRC)
This course will present a comprehensive review of the latest 2.5D and 3D interposer approaches being developed worldwide. High density interposers are emerging as a mainstream technology for packaging of heterogeneous ICs and 3D ICs, but also as a simpler and better alternative to 3D ICs with TSV, eventually providing a path for integration of sub-systems or entire systems. Silicon and glass interposers are emerging as the front-runners to address the I/O, CTE, warpage and thermal limitations of current organic packages. The topics covered include Electrical & Mechanical Design, Silicon Interposers, Glass Interposers, Chip Level & Board Level Interconnections, Applications and Markets, and Manufacturing Infrastructure for interposers. Wafer based BEOL Si interposers as well as emerging panel based glass and other interposer technologies will be described in detail. A variety of materials and process options for interposer fabrication will be presented. The technical and business challenges that must be addressed for successful implementation of interposers in 3D packages will be discussed. Specific examples of key interposer developments such as Xilinx stacked silicon interconnect, MEMS packaging using glass interposers, silicon interposer for high performance CPU packaging, and logic-memory high bandwidth 3D integration will be highlighted. For 2013, the course materials will be updated to include technology highlights in the past twelve months.
Who Should Attend?
This popular course is a must-attend event for those highly interested in interposer technology advances for the future. The course is intended for a broad audience including semiconductor and packaging managers, technologists, engineers, industry and academic researchers, and students.
Dr. Venky Sundaram is the Director of Research at the 3D Systems Packaging Research Center (PRC), Georgia Tech. He is the Program Manager for the Silicon and Glass Interposer (SiGI) industry consortium with more than 25 active global industry members. His research expertise is in the areas of System on a Package (SOP) technology, 3D packaging and integration, ultra-high density interposers, embedded components and systems integration. He is a globally recognized expert in packaging technology and a co-founder of Jacket Micro Devices, an RF/wireless start-up acquired by AVX. Dr. Sundaram is the co-chairman of the IEEE CPMT Technical Committee on Interconnections and Substrates and is on the Executive Council of IMAPS as Director of Education Programs. Dr. Sundaram has won several best paper awards and has 15+ patents and 100+ publications. He received his BS from IIT Mumbai, and MS and PhD in Materials Science and Engineering from Georgia Tech.
PDC3: High-Temperature Electronics - with an Emphasis on Assembly & Packaging
Course Leader: Randall Kirschman, Consultant
High-Temperature Electronics (HTE) is a valuable option for substantially improving overall system performance. Operating temperature can be an additional design parameter when justified by system performance requirements. Applications of HTE include many areas of science and technology, including petroleum and geothermal wells, vehicles, aircraft, Solar System exploration, and electric power. Relocating electronic subsystems to high-temperature can improve overall system efficiency, decrease size and weight, simplify maintenance and improve reliability. At the same time there are many technical challenges, related to materials interactions, component behavior, circuit design and interfacing. The focus of this course is semiconductor electronics assemblies at high temperatures: applications, advantages and drawbacks, technical issues and present situation. Topics include semiconductor device behavior and capabilities, packaging and assembly materials characteristics as a function of temperature, passive electronic component behavior, practical aspects of choosing packaging and assembly material and techniques. The temperature range covered in this course extends from 125°C upward, as high as 1000°C, although emphasis is on the more practical range of approximately 125°C to 300°C. The course notes include approximately 160 PowerPoint slides, more than 100 pages of detailed notes, and more than 300 references.
Who Should Attend?
Engineers and technical persons developing, designing or working with electronics for operation at high temperatures. A basic background in electronic materials and devices will be helpful.
Dr. Randall Kirschman is an internationally recognized authority on extreme-temperature electronics. He has been consulting to industry, government and academe since 1980 in the areas of micro-electronic materials and fabrication technology, and electronics for extreme temperatures. Before going into business for himself, he managed an R&D processing laboratory a division of Eaton Corporation, where he was responsible for the fabrication of microwave thin-film circuits. Prior to that he was on the staff of the Jet Propulsion Laboratory, performing research on a variety of semiconductor materials and devices. During 1990-91 he was a Visiting Senior Research Fellow at the University of Southampton, England. and between 1998-2005 was a member of the Physics Department at Oxford University. He edited the 1999 IEEE Press/Wiley book High-Temperature Electronics. He completed his undergraduate studies at the University of California, and earned his Ph.D. in Physics and Electrical Engineering at the California Institute of Technology.
PDC4: Hermetic Sealing and Testing of Small Volume MEMS Packages
Course Leader: Thomas J. Green, TJ Green Associates LLC
Reliable packaging of MEMS requires the ability to create and maintain a suitable inert atmosphere or vacuum inside the package cavity for the expected lifetime of the device. Traditional hermetic ceramic/metal packages are being replaced by wafer level packaging techniques, which present unique challenges from a hermeticity testing perspective. This course begins with an overview of traditional hermetic sealing processes along with wafer level MEMS packaging processes and methods. In some cases near-hermetic packages, such as LCP are suitable for some applications. Testing of small cavity MEMS packages according to the traditional Mil Spec TM 1014 requirements may not be sufficient to guarantee reliable operation. Difficulties and limitations in fine leak testing of small volume packages will be addressed. Recent advances in Optical Leak Testing (OLT), Cumulative Helium Leak Detection (CHLD) along with other hermeticity techniques, such as pirani vacuum sensors, are reviewed in light of the new tighter hermeticity specifications. Gaseous ingress is of primary concern for a small volume MEMS cavity packages. Moisture level vs. surface area to volume ratio is an important concept, along with material outgassing and the potential to mitigate these problems with getters. These along with other critical MEMS packaging issues are addressed.
Who Should Attend?
This PDC is intended as an intermediate level course for process engineers, designers, quality engineers, and managers responsible for packaging and hermetic testing of small volume cavity style packages.
Thomas J. Green is the principal at TJ Green Associates LLC (www.tjgreenllc.com), a veteran owned small business specializing in teaching and consulting for the microelectronics industry. Tom has demonstrated expertise in sealing and hermeticity testing of products intended for high rel military and medical applications. He is currently on the JEDEC committee helping to revise TM 1014 and has served as an expert witness in medical cases related to hermeticity failures. Tom is an active member of IMAPS and a Fellow of the Society. He has a B.S. in Materials Engineering from Lehigh University and a Masters in Engineering.
PDC5: Failure Mode Analysis of Flip Chip and Advanced Package and Board Assemblies
Course Leader: Daniel Baldwin, Engent, Inc.
Over the past few years, numerous advanced packaging and process technologies have emerged such as flip chip in package, PoP, SiP, WLCSP, 3D-WLCSP, QFN, etc.. While a large number of technical publications are available to help with process requirements, understanding failure modes and reliability standards is essential for these technologies to be successfully sustained in production. This course will present reliability test procedures, assembly process defects, and common failure modes that occur in advanced package and board level assemblies. It will focus on process defect identification and resolution, failure mechanisms and the associated analysis tools needed to identify them such as FTIR, XRF, transmission X-ray analysis, acoustic microscopy and scanning electron microscopy. Numerous process defects and failure modes will be presented along with extensive visual aids to provide a more intuitive understanding of the defects and failure modes associated with these advanced assemblies. It will also discuss artifacts leading to process defects and how they can contribute to premature failure.
Who Should Attend?
Individuals associated with electronics packaging, package reliability, package failure analysis, and assembly process control/defects are encouraged to attend. The following are encouraged to attend. Managers. Knowledge gained through this course will allow managers to make informed decisions about the technical feasibility, implementation factors, performance benefits, reliability, and risks of implementing flip chip technology. Engineers. Manufacturing, quality, design, and packaging engineers in integrated circuit, equipment, materials, and system design who are challenged to solve process defects and packaging problems. Knowledge gained through this course will allow engineers and technologists to make informed decisions about the technical feasibility, implementation factors, performance benefits, reliability, and risks of implementing flip chip technology.
Dr. Daniel F. Baldwin is the President and CEO of Engent, Inc.-Enabling Next Generation Technologies providing enabling manufacturing services and process technologies in the areas of microelectronics, flip chip, optoelectronics, and MEMS. He is one of the 2003 founding partners of Engent. He recently completed an Adjunct Associate Professor of Mechanical Engineering position at the Georgia Institute of Technology. He was a tenured Associate and Assistant Professor of Mechanical Engineering at Georgia Tech from 1995 through 2005. At Georgia Tech, he headed the Low Cost Flip Chip Processing program for the Packaging Research Center, the Advanced Interconnect Technologies research program for the Manufacturing Research Center, and the Low Cost Assembly Processing Program for the CBAR. Prior to joining the faculty, he was a Member of the Technical Staff at Bell Laboratories, Princeton NJ working on electronic product miniaturization. He was formerly the Vice President of Siemens' Advanced Assembly Technology Division. He also served as a research manager and research assistant at MIT's Laboratory for Manufacturing and Productivity from 1990 to 1994, a Draper Fellow at the Charles Stark Draper Laboratory in Cambridge MA from 1988 to 1990, and an Engineering Intern for Mitsubishi Electric, Kamakura, Japan in 1987. Dr. Baldwin received his S.M. and Ph.D. degrees in Mechanical Engineering from MIT in 1990 and 1994, respectively. Dr. Baldwin served as the Technical Program Chair of the IMAPS 2nd International Advanced Technology Workshop on Flip Chip Technology and the General Chair of the IMAPS 3rd International Advanced Technology Workshop on Flip Chip Technology. Dr. Baldwin was the recipient of the ASME Electrical and Electronics Packaging Division's Outstanding Young Engineer Award, 1998 and the Milton C. Shaw Outstanding Young Manufacturing Engineer Award, Society of Manufacturing Engineers, 1999. He has sixteen years of experience in the electronics manufacturing and packaging industries, eight U.S. Patents, over 230 scholarly publications, and expertise in electronics packaging, MEMS packaging, advanced materials processing and manufacturing systems design. Dr. Baldwin is a past President of the Surface Mount Technology Association (SMTA), and formerly on the Board of Advisors for the Society of Manufacturing Engineers/Electronics Manufacturing Division (SME/EM). He was on the editorial advisor board of Advanced Packaging magazine and HDI magazine. He is on the Board of Directors of Engent, Inc. and Akrometrix, LLC, and the Board of Advisors for IC Interconnect. Dr. Baldwin was also on the technical Board of Advisors of RFIDentics Corp. which was acquired by Avery Dennison Corp.
Break: 10:00 am - 10:20 am
Afternoon Professional Development Courses
1:00 pm - 5:00 pm
PDC6: Fundamentals of Glass Technology and Applications for Advanced Semiconductor Packaging
Course Leader: TJ Kiczenski, Corning, Inc.
The objective of this course is to build a foundation of understanding of engineered glass as a material that technologists can leverage in the development of advanced IC packaging applications. Starting from the fundamental principles of glass structure, composition and properties we will provide a broad overview of glass with a focus on unique attributes that make glass as an enabling material. Subjects to be covered will include strength and reliability, chemical durability, thermal behavior, associated thermal relaxation behavior, and electrical properties. Additionally we will review the platform alternatives as part of the "glass toolkit" available to semiconductor packaging development including various manufacturing (melt & form) approaches, the diversity of compositional options and a survey of glass processing options that can be adapted from adjacent glass technology space to advanced semiconductor packaging. Finally the course will illustrate with case studies how glass is contributing to emerging 3D-IC technologies and explore current and potential applications in advanced semiconductor packaging. We will focus on its role as a carrier for temporary bonding, integrated wafer for CMOS Image Sensor, and 2.5D and 3D glass interposers. Relative costs of glass will be discussed as an alternative to other materials for carriers and interposers.
Who Should Attend?
The target audiences include individuals or companies with little or no experience in using glass. Engineers, technical managers, scientists, buyers, and managers involved in materials, research and development, and 3D IC packaging.
Dr. TJ Kiczenski is a Research Associate with Corning Incorporated. His work includes investigations of the physics of glass relaxation, liquidus relationships in multicomponent glass forming systems, metallic glasses, and glass/glass and glass/ceramic composite materials. He is credited as the inventor or co-inventor of several Corning Display Technology products manufactured by the proprietary fusion process, including Corning Lotus Glass for low-temperature polysilicon display applications. He received his PhD in Geology and M.S. in Materials Science from Stanford University where he investigated the structure of fluorine in silicate and aluminosilicate glasses and his B.A. degree in Physics from Coe College where he studied alkali-germanate glasses. Aric Shorey, PhD, is a Sr. Technical Manager at Corning Incorporated working on the Semiconductor Glass Wafer program. He has BS/MS in Mechanical Engineering and a PhD in Materials Science - all from the University of Rochester. He has spent the majority of his career in material's finishing and characterization for the telecommunications, precision optics and semiconductor industries.
PDC7: Polymers for Electronic Packaging
Course Leader: Jeffrey Gotro, InnoCentrix, LLC
This course will provide a broad overview of polymers and the important structure-property-process-performance relationships for electronic packaging. Topics to be covered are thermosetting polymers versus thermoplastics, thermosetting polymer curing, curing mechanisms (heat and light cured), network formation, and an overview of key chemistries used (epoxies, acrylates, polyimides, bismaleimides, curing agents, and catalysts). The course will provide a more in-depth discussion of the chemistries, material properties, and process considerations for adhesives (both paste and film), capillary underfills, packaging substrate materials, encapsulants (mold compounds), and coatings. In most cases, adhesives, underfills, mold compounds and coatings are applied as a viscous liquid and then cured. The flow properties are critical to performance in high volume manufacturing. The final portion of the PDC will provide an introduction to rheological characterization methods (various types of rheometers and viscometers) and the properties of adhesives (shear thinning, viscosity, time dependence, rheology changes during curing), underfills, and mold compounds.
Who Should Attend?
Packaging engineers and R&D professionals involved in the development, production, and reliability testing of semiconductor packages would benefit from the course.
Dr. Jeffrey Gotro has over twenty-six years experience in polymers for electronic applications and composites having held scientific and leadership positions at IBM, AlliedSignal, Honeywell, and Ablestik Laboratories. He is an accomplished technology professional with demonstrated success solving complex polymer problems, directing new product development, and enabling clients to improve the financial impact of their polymer technologies. Jeff has consulting experience with companies ranging from early-stage start-ups to Fortune 50 companies. Jeff is a nationally recognized authority in thermosetting polymers and he has received invitations to present lectures and short courses at national technical conferences. He has published 60 technical papers (including 4 book chapters) in the field of polymeric materials for advanced electronic packaging applications, holds 13 issued US patents, and has 8 patents pending. Jeff has a Ph.D. in Materials Science from Northwestern University with a specialty in polymer science and a B.S. in Mechanical Engineering/Materials Science from Marquette University.
PDC8: Thermal and Mechanical Simulation Techniques - An Introductory Course for 3D Enablement Professionals
Course Leader: Kamal Karimanal, Cielution LLC
The industry is becoming increasingly aware of the fact that thermal and mechanical factors are crucial hurdles to the realization of TSV based 3 Dimensionally stacked IC products. These challenges are pervasively felt at all stages of the product development cycle starting from Layout, IC design, power management, assembly processing strategy, package design, and testing. Due to the need to narrow down from a myriad of costly choices even prior to test chip or prototype development, engineering simulation is an important tool at the disposal of the engineer. As a result, engineers from all IC design and packaging background who are tasked with the responsibility of enabling 3D ICs are interested in utilizing thermal and mechanical simulation. This is an introductory course on thermal and mechanical simulation techniques pertaining to 3D Through Silicon Stacking meant for engineering professionals involved in the enablement of TSV based 3D stacked SOCs. Thermal Modeling Techniques: Steady-State, Transient, Detailed and Compact. Modeling Tools and Techniques for 3D IC Thermal Management. Overview of mechanical challenges to 3D stacking: warpage, assembly Yield, CPI effects on Yield & reliability Mechanical Modeling Tools and Techniques for Technology development and Reliability. Mobility/stress distribution: Contributions from package, TSV and devices.
Who Should Attend?
Any Engineering professional involved in 3D enablement with interest in the Thermal and mechanical challenges. Also suited for technologists and managers interested in deploying engineering simulation as a strategic tool for understanding thermo-mechanical feasibility, risks and benefits of costly technological investments related to 3D TSV based products.
Kamal Karimanal is the Founder of Cielution LLC, which is an engineering simulation software and services company serving the electronics supply chain. Prior to starting Cielution, Dr. Karimanal has served in several engineering simulation focused roles at Fluent Inc, ANSYS Inc and Globalfoundries. Dr. Karimanal has contributed to several detailed and compact modeling methodologies which are being widely used by the electronics industry today. He has written several conference and journal papers and online application notes. Dr. Karimanal received his Ph. D in Mechanical Engineering from The University of Texas at Austin.
PDC9: MEMS Reliability and Packaging
Course Leader: Slobodan Petrovic, Oregon Institute of Technology
This course provides a comprehensive discussion of a broad array of MEMS packaging and reliability issues. An overview of the principles of operation, fabrication methods, and materials used in building MEMS structures will be presented as well. Because each MEMS device requires a distinctive packaging approach, practical examples and illustrations will be used to demonstrate uniqueness of solutions and interactions between micromachined structures and packaging. A full range of MEMS devices will be discussed while a particular emphasis will be placed on sensors and actuators used in industrial, medical, and automotive applications. Extensive case studies that will be used to most effectively demonstrate diverse packaging principles for devices such as accelerometers, pressure sensors, and digital micromirror devices. The course will be divided in 2 major sections: general MEMS competence; and packaging and reliability. The following major topics will be covered: fabrication technologies, materials, design and device physics, main MEMS types, integration aspects, selected industrial application, design considerations, types of packaging, quality control, reliability and failure analysis.
Who Should Attend?
While some prior knowledge by the participants of MEMS in general is helpful, the packaging discussion will include a detailed explanation of the principles of operation, fabrication methods, and materials used in building MEMS structures. The course is therefore open to participants with no prior MEMS knowledge and would provide a reasonably broad general introduction into the field. The participants will have the opportunity to gain knowledge about MEMS in general through the eyes of a packaging and reliability specialist.
Dr. Slobodan Petrovic is an associate professor at the Oregon Institute of Technology in Portland, OR. His research interests are in the areas of MEMS fuel cells, sensor media compatibility, hydrogen generation and storage, and dye-sensitized solar cells. Prior to that, he was at the Arizona State University, where he taught courses in MEMS, Sensors, and alternative energy. Dr. Petrovic also held appointments at Clear Edge Power as a Vice President of Engineering; at Neah Power Systems as Director of Systems Integration; and Motorola, Inc. as a Reliability Manager. Dr. Petrovic has over 25 years of experience in MEMS, sensors, energy systems; fuel cells and batteries; and electrochemical solar cells. He has over 50 journal publications and conference proceedings; 2 book contributions and 24 pending or issued patents.
PDC10: Basics of Conventional and Advanced Packaging
Course Leader: Syed Sajid Ahmad, Center for Nanoscale Science and Engineering, NDSU
The course presents manufacturing, materials, quality and reliability info in terms understandable to engineering and non-engineering personnel. Packaging characteristics and drivers will be outlined. Types of packages and critical differences among them and their applications will be discussed. The course will look at the design selection to meet use and application environments. Step-by step manufacturing flow for plastic packages will be presented as an example to understand the complexity of processes, materials and equipment involved in their manufacture. Advanced packaging will be introduced. Materials selection with respect to application environments will be discussed. Quality and reliability issues related to chip packaging and SMT and their solution will be outlined. Topics: Packaging characteristics and drivers. Types of packages and critical differences among them. Design selection to meet use and application environment. Step-by step manufacturing flow for plastic packages. Advanced packaging. Materials selection. Quality and reliability issues.
Who Should Attend?
It will help the attendees understand the effects of package configurations on their work and the effect of their work on chip packages. Personnel entering the packaging field will have a critical look at the quality, reliability and materials issues related to the development and manufacture of chip pacakages. Non-packaging personnel will learn ins and outs of chip packaging. Non-technical personnel will learn the material and manufacturing intricacies of simple looking chip packages.
Syed Sajid Ahmad contributed to quality and reliability enhancement of assembly processes at Intel (1979-89), especially wire bond. Ahmad also contributed to packaging development at National Semiconductor (1990) and managed quality at GigaBit/TriQuint (1990-91). His major work at Micron Technology (1991-2003) involved the development and implementation of advanced packaging. At the Center for Nanoscale Science and Engineering, Ahmad's focus is on enhancing research and manufacturing capabilities at the center in the areas of thin film, thick film, chip scale packaging (CSP) and surface mount technology (SMT). Ahmad has 34 international publications and presentations and holds 54 patents.
Break: 3:00 pm - 3:20 pm
Welcome Reception (All Attendees Are Invited To Attend)
5:00 pm - 6:30 pm
Microelectronics Foundation Texas Hold'Em Tournament (Separate Register Fees - limited seating)
7:00 pm - 10:00 pm
Register On-Line | Device Packaging Home
Join Us for the 2013 IMAPS Microelectronics Foundation Spring Golf Invitational This March
Join Us for the 2013 IMAPS Microelectronics Foundation Spring Golf Invitational This March ^ Top
Thursday, March 14, 2013
1:00pm Shotgun Start – “Best Ball” Scramble
Desert Canyon Golf Club
10440 Indian Wells Drive |
Fountain Hills, AZ
The IMAPS Microelectronics Foundation Spring Golf invitational will be held at the Desert Canyon Golf Club. Desert Canyon was named 2009 “Best Places to Play” by Golf Digest and has been voted “Best Public Golf Course” in Fountain Hills for six consecutive years. Desert Canyon Golf Club’s eighteen hole championship course features elevated tees coupled with a variety of elevation changes. Fairways, though open, play tight and prove challenging with strategically placed doglegs.
Cost: $125/golfer -- $450/four-some
The cost includes: Transportation to and from the course, greens/cart fees, shotgun start, lunch in cart, and awards reception following your round.
A shuttle will pick up golfers at the Radisson Fort McDowell at 12:00pm. Golfers will tee off shortly after arriving at the course – 1:15pm shotgun start. Golfers are welcome to drive themselves to arrive earlier. An awards presentation and reception will be held immediately following golf.
All proceeds from this event will benefit the IMAPS Microelectronics Foundation.
Special Awards and Activities tentatively planned:
- Closest to the Pin;
- Longest Drive
Eagle Sponsor - $3,000 -- 2 SOLD
- Company logo/name displayed as Awards Reception Sponsor.
- Entrance of two four-somes.
- Includes three hole sponsorships with signage.
- Company logo/name on all event promotional signs, materials and website.
- Company may provide take-away products to be handed to all golfers. Golf-related items usually most appropriate (e.g., golf towels, balls, tees, etc.). At expense of sponsor.
Birdie Sponsor - $1,500 -- 1 SOLD
- Company logo/name displayed as Lunch Sponsor - in/on boxed lunches.
- Entrance of one four-some.
- Includes one hole sponsorship with signage.
- Company logo/name on all event promotional signs, materials and website.
Hole Sponsor - $400 ($750 w/ four-some) -- 13 SOLD
- Sponsorship of one hole with signage.
- Entrance of one golfer ($400 or $750 includes 4-some).
- Company logo/name on promotional materials and website.
Upcoming Webinar - Intro to Micro... ^ Top
Upon registering for one of our webinars, IMAPS provides the log-in details for the web software as well as the audio dial-in through your phone. You are able to view the presentation materials over your computer and listen to the live lecture through your phone. You will receive a copy of the slides for each session, and have direct interaction with the instructor.
PDC Webinar Series on Introduction to Microelectronics Packaging Technology
Phillip Creter, Creter and Associates
Tuesday, February 5 and Thursday, February 7, 2013 - 12:00pm-1:00pm EASTERN
High Temperature (HiTEN 2013) - Abstracts Still Being Accepted - Exhibits, Registration and Sponsorships Now Open ^ Top
IMAPS International Conference and Exhibition on High Temperature Electronics Network (HiTEN) will be held July 8-10, 2013, at St. Catherine’s College Oxford in Oxford, United Kingdom. Visit www.imaps.org/hiten to register to attend and to view the program on-line.
The objective of the HiTEN Conference is to have a unique forum that brings together researchers and practitioners in academia and industry from all over the world. All styles of practical high temperature electronics design and implementation approaches are encouraged, along with a variety of high temperature application areas. Today the main semiconductor focus of HITEN is silicon and silicon on insulator (SOI). Although, HITEN is not simply a semiconductor focused network. HITEN provides a conduit for the exchange and dissemination of information on all aspects of high temperature electronics. It is a global network with users, suppliers, developers and fundamental researchers dealing in all aspects of High Temperature Electronics.
Abstracts are being requested in the following areas:
- Applications in the Aerospace, Automotive, Oil & Gas, and Geothermal Industries
- Devices and applications
- Novel devices
- ASICs for high temperature applications
- Passive components
- Power devices
- Semiconductor materials
- Contacts and metallizations
- Packaging and inter connects
- Sealants, adhesives, solders
- Reliability and failure mechanisms
- Lifetime predictions
- Accelerated life testing
- Testing at high temperatures
Those wishing to present a paper at the HiTEN Conference must submit a 200-300 word abstract electronically ASAP, using the on-line submittal form at: www.imaps.org/abstracts.htm. A Final Manuscript of 6-12 pages, two-column format is due May 31, 2013, for all accepted abstract.
Please contact Brian Schieman by email at email@example.com or by phone at 202-548-8715 if you have questions.
Accepted papers may be considered for publication in the IMAPS Journal of Microelectronics and Electronic Packaging. All Speakers are required to pay a reduced registration fee and are required to attend the entire Conference to maximize opportunities for interaction with registered attendees.
||Chapter Activities (events listed in chronological order)
New England Chapter Dinner Presentation on February 5 ^ Top
Holiday Inn Tewksbury-Andover
4 Highwood Drive
Pre-Registration deadline is Thursday, January 31.
After January 31, or for Walk-Ins At-Door, the fee is an additional $5.00 [Limited Availability]
Pay At-Door with Credit Card or Check payable to “iMAPS New England”
5:30 PM Registration, Socializing, Networking & Cash Bar
6:30 PM Dinner – All American Buffet
7:15 PM “Advancements in Acoustic Micro-Imaging Technology”
Speaker: Jack H. Richtsmeier, Business Development Manager for Sonoscan, Inc.
Presentation Summary: Acoustic Micro Imaging is an established non-destructive inspection technique that applies ultrasound in the inspection of microelectronic packaging and semiconductor devices for commercial, military and medical devices.. Recent advancements and new developments have expanded the role of AMI for semiconductor and MEM’s devices. You will learn about these latest advancements through examples and case studies depicting a variety of advanced packaging, wafer and MEM’s components
Speaker: Mr. Richtsmeier holds a Bachelors Degree in Physical Science from St. Thomas University (St. Paul, MN). His professional background includes over 20 years of expertise in acoustics and ultrasonics within the semiconductor and microelectronics industry.
Register by THIS FRIDAY for the Viking Chapter February 5 Technical Presentations and Facility Tour at Benchmark Electronics in Rochester ^ Top
Participants will need to provide photo ID given on-site ITAR regulations.
3535 Technology Drive NW
Rochester, MN 55901
Pre-registration is required by THIS FRIDAY, February 1. To register, please contact Dan Johns of Benchmark Electronics at 507-535-4315 or firstname.lastname@example.org.
2:00 Registration, chapter welcome, and overview of Benchmark Electronics.
2:30 Guided Facility Tour.
Tour includes: 1) a walking tour of the printed circuit board assembly area (Note: US Citizenship is required in this area due to ITAR restrictions), 2) systems integration area, 3) design engineering labs, and 4) observation window view of the microelectronics assembly clean room. Tour guide will be Chuck Gilbertson, Product Engineering Manager.
3:30 Brief Break
3:45 “Counterfeit Parts; Their Detection, Mitigation, and Supply Chain Impacts.” Dan Gibbs, Failure Analysis Manager at Benchmark Electronics
4:15 “Case Study: Accuvein Vein Viewer.” David Edmonson PhD., Staff Research and Development Engineer at Benchmark Electronics
4:45 Appetizers and beverages. Event wrap-up. Next chapter events. Other business.
5:30 Event concludes
Presenter Abstracts and Bios:
“Counterfeit parts; Their Detection, Mitigation, and Supply Chain Impacts.”
Abstract: Counterfeiters are improving their capabilities, such that altered components are nearly indistinguishable from the original package. This presentation discusses counterfeit definitions, supply chain complexities associated with suspect sources, and laboratory tools / methods used to detect counterfeit components from an electronic contract manufacturers perspective. This includes optical inspection (packaging and component), X-ray, XRF, chemical decapsulation, ion chromatography, SEM/EDAX, cross sectioning, solvent, electrical, and solderability testing. In addition, the factors of analysis time, cost, and skill set relative to each tool and method will be covered.
Bio: Dan Gibbs is the Failure Analysis Manager for the Benchmark Electronics - Minnesota Division. His department is a resource for all Benchmark Electronics worldwide divisions. Dan has 20 years of experience in the electronics assembly industry. This includes a variety of positions in analytical / conformance testing, Six Sigma, and quality assurance management. Dan received a Bachelor of Science degree from Winona State University in 1991.
Dr. Dave Edmonson.
“Accuvein Vein Viewer.”
Abstract: Dermal layers and subcutaneous fat are rather transparent in the infrared region of the spectrum. In contrast (literally) blood, both oxygenated and non-oxygenated, exhibits strong absorption. Since blood is concentrated in the veins and arteries this differential absorption phenomenon can be used to highlight the location of the veins in particular, since they are closer to the skin surface. The presentation will discuss how Benchmark Electronics developed and produced a commercial handheld device from a crude prototype. The presentation will provide both an overview of how the device functions and then note the subsystems that were created and packaged to achieve the final design.
Bio: Over the past 10 years at Benchmark Electronics Inc., Dr. Edmonson has been developing equipment and processes for many hybrid assembly products ranging from data storage to medical implants. More recently, Dr. Edmonson has worked on optical hybrid devices and medical instruments; most of these required some sort of hybrid assembly process using mixed technologies. Specific processes include alignment of single mode fibers to lasers, lenses, gratings and attachment processes. Most required customized test systems and the creation of performance criteria for data analysis.
Central Texas Chapter's Electronics Design & Manufacturing Symposium Tuesday, February 5 ^ Top
2:00 Registration Begins
2:30 CTEA Welcome. Specialty Coating Systems Factory Overview
2:35 Specialty Coating Systems Factory Tours
3:35 "Parylene Coating Technology Update.” Dr. Rakesh Kumar, Vice President of Technology of Specialty Coating Systems
4:05 "Before & After Reflow Characterization of FCBGA Voiding Utilizing High Resolution CT Scan, X-ray (2D & 3D) Imaging, and Cross Section with Digital Imaging." Gordon O’Hara, Process Engineering Manager at Flextronics
4:35 Brief Break
4:50 "Overview of Copper Wire Bonding Technology.” Andrew Mawer, Packaging Analysis Lab Manager at Freescale Semiconductor
5:20 "Protecting Intellectual Property (IP)." Robert Villhard, Intellectual Property Attorney at The Villhard Patent Group
5:50 Closing Remarks
6:00 Bar-B-Q Dinner sponsored by Specialty Coating Systems
Please contact Bob Baker at email@example.com to register. Advance registration is helpful. There is no charge for this event - through the generous sponsorship by Specialty Coating Systems.
Specialty Coating Systems
1130 Rutherford Lane, #260
Austin, Texas (between I-35 & Cameron Rd)
IMAPS Northern California Chapter February 6 Lunch Presentation on 2.5D Interposer Fabrication for the Rest of Us ^ Top
11:30 AM – 12 PM Registration & Networking
11:30 AM – 12:15 PM Buffet Luncheon
12:15 PM – 1:00 PM Speaker Presentation
David's Restaurant, Banquet & Conference Facilities
5151 Stars & Stripes Drive
Santa Clara, CA 95054
IMAPS Members $25.00; Non-members $30.00;
Students (with ID) $15.00
Price includes lunch and program. Please email Roger Underwood, IMAPS NorCal Treasurer, at firstname.lastname@example.org before COB Monday February 4, 2013 to guarantee your lunch. SPACE IS LIMITED! Registrations will be confirmed via e-mail. We only accept cash and checks at the door.
Real 3DIC Solutionss
Charles G. Woychik, Ph.D. Director of 3D Technology & Marketing
Abstract: 3DIC packaging continues to migrate from R&D to commercial adoption at an accelerating rate. The arrival of the first commercial 2.5D (silicon interposer) solution challenges us to question "which parts of the process and supply chain are maturing, and which parts are ripe for reinvention?" Invensas has been developing HVM fine-node 2.5D interposer technology in partnership with AllVia, in conjunction with advanced micro-bumped die that accommodate interconnect schemes exceeding 10,000 I/O. An overview will be given of this development as well as a brief discussion of the remaining "choke-points", those areas in need of reengineering and reinvention.
Charles Woychik is Director of 3D Technology and Marketing for Invensas Corporation™, a San Jose based leader in semiconductor packaging and 3DIC technology [Invensas.com]. He draws from 25 years of experience in the area of microelectronics packaging, and his extensive knowledge of the design, materials selection and processes used for microelectronics packaging applications ranges from high-performance computer processors to low-power mobile applications. Prior to Invensas, Chuck worked for General Electric Global Research and Advanced Semiconductor Engineering, after spending the first 18 years of his career with IBM. He holds a doctorate and Master’s of Science degree in Materials Science and Engineering from Carnegie-Mellon University. He has a Bachelor’s of Science degree in Materials Science from the University of Wisconsin, Madison. Chuck has numerous publications and 42 patents to his credit.
IMAPS France 8th European Advanced Technology Workshop on Micropackaging and Thermal management ^ Top
||February 6-7, 2013
MERCURE OCEANIDE VIEUX PORT SUD Hotel
Quai Louis Prunier 17000 La Rochelle France
Tel : 33 (0) 5 46 50 61 50/Fax : 33 (0) 5 46 41 24 31
Email : H0569@accor.com
Early Registration ends on January 11, 2013
Final Registration ends on January 31, 2013
« Formulaire de Convention de formation sur demande »
International Microelectronics And Packaging Society France
49 rue Lamartine 78035 Versailles
Tel : + 33 (0) 1 39 67 17 73/ Fax : + 33 (0) 1 39 02 71 93
E-mail : email@example.com
The Workshop will present improvements in thermal management materials, components and systems, to provide
innovative packaging and cooling solutions for highly integrated power, RF, microwave and other devices and subsystems.
Increases in functionality, complexity, miniaturisation, operating temperature and power output will require advances
in thermal solutions at many levels, for military, aerospace, consumer and industrial systems.
Industry transition to SiC and GaN devices allows higher operating temperatures with higher heat flux but also
greater reliability; these trends also require improvements and changes in packaging and thermal materials.
Thermal management has been clearly identified, in industry technology roadmaps worldwide, as a crucial constraint
in packaging at all levels.
CONFERENCES SCHEDULE (Provisional as of November 27, 2012)
FEBRUARY 6, 2013 (Wednesday)
09.00 am Opening address: J.M.Yannou, President of IMAPS-France
09.15 am Thermal Storage Nanocapsules
R. Rodriguez Alonso, Inasmet Tecnalia (Spain)
10.00 am SESSION 1 NEW CONCEPTS
Chairs: J.M. Yannou ASE / W. Eckhard, ECPE
10.00 am Miniaturized Frictionless Fan Concept for Thermal Management of Electronics
R. Schacht, Lausitz University of Applied Sciences, Fraunhofer Enas,
Joint lab Berlin (Germany)
10.25 am Enhanced Boiling Heat Transfer on Micromachined Surfaces Using Acoustic Actuation
A. Glezer, Georgia Institute of Technology (United States)
10.50 am Coffee Break/ Table Top Exhibition
SESSION 2 MATERIALS
Chairs: P. Lewandowski, Continental Automotive / M. Mermet Guyennet Alstom
11.15 am Industrial Application of Cold Spray and Use of this Technology for
S. Hartmann, Obz Innovation GmbH (Germany)
11.40 am Thermal Management Materials and Cooling Solutions Made by Rapid Hot Pressing
and Rapid Sinter Pressing
E. Neubauer, Rhp Technology GmbH (Austria)
12.05 pm Approach for Finding a Proper Golden-Reference Sample for TIM Tester Calibration
A. Vass-Varnai, Mentor Graphics (Hungary)
12.30 pm-02.00 pm Lunch
SESSION 3 MODELING AND EXPERIMENTAL
Chairs: J. Lallier, Thales / S. Feneyrou, Zodiac Aerospace
02.00 pm Application of Complex Thermal Impedance for Multilayer Thermal Structure
B. Wiecek, Technical University of Lodz (Poland)
02.25 pm Thermal Resistance Simulation and Measurement of a Double Sided Cooled
S. Kraft, Fraunhofer IISB (Germany)
02.50 pm Experimental Investigation of High Density Folded Fin Structures for
Electronics Cooling Applications
A. Engelhardt, Thermacore Europe (United Kingdom)
03.15 pm Practical Evaluation of CFD Models for Heat Sink Design in Photonic System
O. Wittler, Fraunhofer Berlin (Germany)
03.40 pm Coffee Break/ Table Top Exhibition
SESSION 4 SOLUTIONS INTEGRATED AT SUBSTRATE LEVEL
Chairs: N. Chandler, BAE Systems / B. Braux, Astrium
04.15 pm Theoretical Study of the Thermal Impact of a Passive Heat Spreading Layer Integrated
in 3D Mobile Device
S. Salman, CEA, LETI, (France)
04.40 pm An Integrated Passive Cooling Solution for PCB Substrates
D. Kearney, J. Griffin, ABB Corporate Centre, (Switzerland)
05.05 pm Developments and Applications for Thermal Core PCBs
D.L. Saums, DS&A LLC (United States)
05.30 pm End of Session
08.00 pm Dinner « Salle de l’Oratoire » 6 rue Albert 1er La Rochelle
FEBRUARY 7, 2013 (Thursday)
SESSION 5 APPLICATIONS
Chairs: C. Sarno, Thales Avionics / M. Massiot, EGIDE
09.00 am Analysis of Thermal Management Techniques in Tablets
E. Rahim, Electronic Cooling Solutions (United States)
09.25 am Autonomous Cooling for Embedded Computer –New Concept
B. Bellin, Thales Avionics (France)
09.50 am Thermal Management of a 49W Computer Processing Unit with a 23W Hotspot
J. Carcone, Airbus Opérations SAS (France)
10.15 am Loop Heat Pipe for the Thermal Management of Hot Spots in Future
R. Hodot, Thales Avionics (France)
10.40 am – 11.15 am POSTER SESSION / TABLE TOP EXHIBITION
SESSION 6 MATERIALS
Chairs: D. Saums DS&A LLC / B.Wiecek Technical University of Lodz
11.15 am Thermal Properties of Carbon Material Reinforced Aluminium Composite Fabricated
by Hot Pressing with Semi-Liquid Existent Phase
H. Kurita, ICMCB-CNRS (France)
11.40 am Copper/Diamond Composite Materials for Thermal Management Applications
T. Guillemet, ICMCB-CNRS,(France)
12.05 pm Thermally Conductive Encapsulants –Balancing Critical Properties
P. Hough, Lord Corporation (Germany)
12.30 pm – 2.00 pm Lunch
SESSION 7 MATERIALS FOR HARSH ENVIRONMENT
Chairs: R. Seddon, Inasmet Tecnalia / J.L Diot, Novapack SAS
02.00 pm Silicon Nitride Substrates for Power Electronics
U. Voeller, Curamik Electronics GmbH (Germany)
02.25 pm MEMPHIS: Miniaturized Electronic Module for Power and Hermetic Innovative
Applications In harSh Environment
D. Baudet, B. Braux Astrium (France)
SESSION 8 MODELING
Chairs: R. Seddon, Inasmet Tecnalia / J.L Diot, Novapack SAS
02.50 pm Parametric Transient Thermo-Electrical PSPICE-Model for a Power Cable
R. Schacht, C. Gerner Fraunhofer ENAS (Germany),The Lausitz University of Applied Sciences
03.15 pm Cooling Device Libraries Development for Surrogate Models in Modelica and
D. Lossouarn, EPSILON (France)
03.40 pm End of session / Final Coffee / Departure
2nd Southeastern Microelectronics Packaging Conference - Registrations and Exhibits Filling Fast! ^ Top
||February 28, 2013
Rosen Centre Hotel
9840 International Drive
Orlando, FL 32819
Please email Doug Bokil - firstname.lastname@example.org with questions
The objective of the Florida Chapter Microelectronics Symposium is to provide a forum that brings together experts from science, academia, design, manufacturing and business to discuss the latest advances and emerging applications in microelectronics and high density packaging.
||Patrick Simpkins, Director of Engineering
NASA's John F. Kennedy Space Center in Florida
Dr. Patrick Simpkins is the director of Engineering at NASA's John F. Kennedy Space Center in Florida. In this position, Simpkins leads a group of engineers from multiple disciplines in the design, development and operations of spaceflight hardware and ground systems assigned to the Kennedy Space Center.
Professional Development Course (PDC) on WIRE BONDING:
9AM - 12 NOON
Conducted by Lee Levine who is an expert on this topic & has conducted a similar PDC for IMAPS
1PM - 5PM
DNA Marking to Assure Product Authenticity
Janice Meraglia, Applied DNA Sciences
Additive Manufacturing of Fine Lines and Embedded Electronics for use in Chip Packaging and Microelectronic Systems
Scott Lauer, AdvantechUS, Inc.
Predicting the Reliability of Zero-Level TSVs
Greg Caswell, Dfr Solutions, LLC
Low Temperature Sintering Silver Paste Using MO Technology
Ken Araujo, NAMICS Technologies, Inc.
Rediscovering Multilayer Rigid-Flex with Z-interconnect Technology
Rabindra Das, Endicott Interconnect Technologies, Inc.
Cyberfacturing and the 3rd Industrial Revolution
Mike Newton, Newton Cyberfacturing, LLC
Design Optimization of Micro-channel Heat Exchanger embedded in LTCC
Aparna Aravelli, University of Miami
A Novel Approach to Interconnect Redistribution on Singulated Die
David Herndon, Harris Corporation
3 - 8:30PM
Please contact Doug Bokil - email@example.com if you have questions.
New England Chapter's 40 Symposium & Expo - Call For Papers ^ Top
||Tuesday May 7th, 2013
Holiday Inn Boxborough Woods Conference Center
Please send 250 word abstract to: Jim McLenaghan, AJM@Creyr.NET for more details visit us at: www.imapsne.org
Abstract Deadline has passed -- contact Jim asap with questions
For details about Sponsoring, Exhibiting or Attending Contact Harvey Smith: firstname.lastname@example.org or Call 508-699-4767
CALL FOR PAPERS
Symposium Technical Chair
A. James (Jim) McLenaghan, Creyr Innovation, LLC
The Largest Regional Symposium Dedicated to Microelectronics and Packaging
Tuesday May 7th, 2013
----- Featuring -----
Six to Eight Lecture Sessions, Full Poster Session,
Employment Center & 80 Booth Exhibit Hall
The New England Chapter Symposium Technical Program Committee seeks papers that demonstrate how new technologies and applications are expanding and redefining microelectronics. Areas of interests include:
- Medical Electronics
- Telecom – RF & Microwave
- Military Electronics
- Consumer Electronics
- Renewable Energy: Fuel Cells, Solar, Wind
- Thermal & Power Management
- Manufacturing, Outsourcing & Quality
- Software and Firmware Applications
- High Performance Interconnects and Boards
- Sensors (Manufacturing & Applications)
- Emerging Technologies
- Solar, Photovoltaic
- Electronics for Environmental Impact Measurement & Assessment
Advanced Processes & Materials
- 3D, SiP, and High Density Packaging
- Nano Materials - Mfg., Applications, & Safety
- Photonics, Optoelectronics, LED Packaging
- MEMS and Nano Packaging
- Underfill - Materials, Applications, Effectiveness
- Green packaging - Regulation Compliance, Materials, Processes, Recycling
- Flip-Chip and Bumping Processes & Reliability
- Wire-bonding and Stud-Bumping
- Embedded Components – Passives, Magnetics
- Ceramic, Polymer and Conductive Materials
- Cu, Low-K
- Product DFR & DFM Tools, Programs, Implementation
- Materials Deposition & Delivery - Print, Vapor, Dispensing, Placement, etc
Advancing Microelectronics January/February 2013 Magazine Now On-Line - Bumping & Wafer Level Packaging... ^ Top
Volume 40, No. 1
Bumping & Wafer Level Packaging
The January/February 2013 issue featured four technical articles on: A Short History of Flip Chip and Wafer Level Packaging; A Brief History of Electroplating for Bumping and Wafer Level Packaging; Wafer Level Chip-Scale Packaging: Evolving to Meet a Growing Application Space; and Embedded Wafer-Level Packaging is Expected to Increase by 2015, Once Platforms Mature and Fabless Customers Commit
magazine PDF (10mb)
Journal of Microelectronics and Electronic Packaging 3rd Quarter 2012 On-Line - Q4 and Q1 2013 Available Soon ^ Top
and Electronic Packaging
(ISSN # 1551-4897)
Die-Attach Technologies for Ultraviolet LED Multichip Module Based on Ceramic Substrate
T. Burkhardt, M. Hornaff, A. Acker, T. Peschel, E. Beckert, R. Eberhardt, and A. Tünnermann, Fraunhofer Institute for Applied Optics and Precision Engineering IOF; T. Burkhardt and A. Tünnermann, Friedrich-Schiller-University Jena; K.-H. Suphan, Micro-Hybrid Electronic GmbH; K. Mensel and S. Jirak, Lastronics GmbH
Design and Fabrication of an LTCC Structure for a Microceramic Combustor
Darko Belavic, Marko Hrovat, Kostja Makarovic, and Marina Santo Zarnik, Centre of Excellence NAMASTE; Darko Belavic, HIPOT-RR; Darko Belavic, Marko Hrovat, Gregor Dolanc, Kostja Makarovic, and Marina Santo Zarnik, Jozef Stefan Institute; Marina Santo Zarnik, IN.Medica
|Inkjet Printing of Multilayer Capacitors
D. Jeschke, E. Ahlfs, and K. Krüger, Institute of Automation Technology Helmut-Schmidt-University and University of the Federal Armed Forces Hamburg
Southeastern Microelectronics Conference
*Exhibitors contact email@example.com
*Exhibitors contact firstname.lastname@example.org
New England Chapter 40th Symposium & Expo
HiTEN (High Temp)
*Exhibitors contact email@example.com
IMAPS 2013 (Orlando)
September 29-Oct. 3
*Exhibitors contact firstname.lastname@example.org