NEWS | JOBS | FAST LINKS

Heraeus TFD

THANK YOU TO THE IMAPS 2016 PASADENA
SPONSORS & EXHIBITORS!

 

    Premier Program Sponsor:
Premier Program Sponsor - Heraeus Materials Technology

    Premier Technology Sponsor:

    Premier Technology Sponsor:
    Premier Technology Sponsor:
Premier Tech Sponsor - Metalor
Premier Tech Sponsor - Indium Corp.
Premier Tech Sponsor - NGK NTK

 

:: Corporate Member News ::

:: Thank you to all the IMAPS 2016 Exhibiting Companies - View the List & Plan Your Visit! (full story)

:: View the Full Exhibit Directory to Learn more about the IMAPS 2016 before you arrive next Week! (full story)

:: View the Pasadena Floorplan and Register for your Complimentary Exhibit Pass to visit the Vendors, listen to the Keynotes, have some fun at the Welcome Reception, and Network! (full story)

:: Palomar Technologies, the world-leading provider of precision microelectronics and optoelectronic packaging systems, will be presenting a technical paper and exhibiting at IMAPS 2016 (full story)

:: Micro Systems Technologies, Inc. receives ITAR registration – Come visit our booth (#123) at IMAPS Pasadena (full story)

:: Indium Corporation Experts to Present at IMAPS 2016 (full story)

:: Royce Instruments and V-TEK International introduce new AP+ - Come Learn more at Booth #403 in Pasadena Next Week! (full story)

:: Corporate Fast Links ::

Click below to learn more about this issue's featured corporate members.

PREMIER Sponsors:

 

    Premier Program Sponsor:
Premier Program Sponsor - Heraeus Materials Technology

    Premier Technology Sponsor:

    Premier Technology Sponsor:
    Premier Technology Sponsor:
Premier Tech Sponsor - Metalor
Premier Tech Sponsor - Indium Corp.
Premier Tech Sponsor - NGK NTK
Event Sponsors:
Dessert "Happy Hour" Sponsor:

Palomar Technologies: Dessert "Happy Hour" Sponsor
Posters & Pizza Sponsor:

Northrop Grumman EC - Poster Session Sponsor
Keynote Sponsor:

Applied Materials - Keynote Sponsor

Lunch Sponsor:
EMD Performance Materials - Corporate Sponsor

Student Programs Sponsor:
Honeywell - Student Programs Sponsor

Coffee Break Sponsor:

Fujifilm Dimatix - Coffee Break Sponsor

Coffee Break Sponsor:
MRSI - Break Sponsor

Coffee Break Sponsor:
Shenmao - Event Sponsor

Golf Sponsors
EMD Performance Materials - Corporate Sponsor
Technic - Golf Hole Sponsor
MicroScreen - Golf Sponsor
 
Media Sponsors
Media Sponsor: MEMS Journal
Media Sponsor: US Tech
Solid State Technology - Media Sponsor
Media Sponsor: MEPTEC
3D Incites - Media Sponsor
Media Sponsor: Webcom - Antenna Systems & Technology
Media Sponsor: Webcom - Electronics Protection
Media Sponsor: Webcom - Thermal News
Media Sponsor: Chip Scale Review
     

 

All IMAPS Corporate Members will have the opportunity to place their logo/link in the "Fast Links" section. To have your company logo included in an upcoming "Fast Links," email your logo as a JPEG or GIF to Brian Schieman at bschieman@imaps.org. You should also identify which URL to link your logo to. If you have questions, contact Brian. There is no charge for this service, it is offered as part of the corporate membership benefits.

:: More Information ::

:: Only news about IMAPS Corporate Members will be published in this Corporate Bulletin. Please send your electronic press releases to Brianne Lamm, blamm@imaps.org, at least 3 days before the first or fifteenth of every month to be considered for publishing in this bulletin. All corporate bulletin questions - news releases, advertising, logo inclusion, IMAPS membership, and more - should be addressed to Brianne.


:: Palomar Technologies, the world-leading provider of precision microelectronics and optoelectronic packaging systems, will be presenting a technical paper and exhibiting at IMAPS 2016

Palomar Technologies, the world-leading provider of precision microelectronics and optoelectronic packaging systems, today announced they will be presenting a technical paper and exhibiting at the IMAPS 49th International Symposium on Microelectronics in Pasadena, CA being held on October 10-13, 2016 in booth #702.

Palomar Technologies’ Chief Technical Officer, Dan Evans, will present the paper “Wedge Bonding Wire and Ribbon to Support RF and Optoelectronic Packaging” on Thursday, October 13th at 10:30am. This paper will provide a survey of RF andoptoelectronic packages, and the common wire and ribbon bond requirements. It will also survey the packaging challenges and solutions available to process engineers. Collaborations between manufacturer and equipment supplier with helpful tips leveraging each other’s strengths to transition from concept to production will also be discussed.

In addition, SST Vacuum Reflow Systems, as part of Palomar Technologies total solutions for eutectic die bonding and advanced packaging systems, will present their technical paper “Achieving Low Voiding with Lead Free Solder Paste for Power Devices”, and will be performing live demos of their 5100 Vacuum Pressure Furnace. SST’s Process Development Engineer, Pierino Zappella, will present this paper on Thursday, October 13th at 1:00pm. The processes discussed in this session will show how low void levels can be achieved while using solder paste on different materials in a vacuum reflow oven.

Don’t forget to also stop by booth 702 during the Palomar Technologies sponsored Dessert Happy Hour and during the exhibition to learn more about Palomar Technologies and SST Vacuum Reflow Systems.

Palomar


###
Contact
Katie Finney
Marketing Communications Manager
Palomar Technologies, Inc.
kfinney@bonders.com | +1 760-931-3680

 

SST International - Downey, CA -  As part of Palomar Technologies total solutions for eutectic die bonding and advanced packaging systems, SST Vacuum Reflow Systems will be on display and presenting a technical paper at IMAPS 49th International Symposium on Microelectronics in Pasadena, California on October 10-13, 2016 in booth #702. SST will be demonstrating vacuum reflow systems used to create void-free, flux-free solder joints in advanced microelectronic packages.  In addition to participating in the exhibition, SST's Process Development Engineer, Pierino Zappella, will present “Achieving Low Voiding with Lead Free Solder Paste for Power Devices” on Thursday, October 13 at 1 p.m. The processes discussed in this session will show how low void levels can be achieved while using solder paste on different materials in a vacuum reflow oven. This allows SST systems to be used in building power module devices due to lower material cost, higher production speed, and the void free solder performance achieved in a vacuum reflow system.

Palomar Technologies will also be sponsoring a “Dessert Happy Hour” in the exhibition hall on Tuesday, October 11th from 3:30 -4:30 p.m.

SST is excited to be part of the largest conference for microelectronics and to show our new products, applications, and processes to maximize the performance of your microelectronic devices products.

---
A.J. Wilson
President
SST International

 

SST
The QuikCool rate profile achieves lower void concentration versus normal rate profile in AuSn solder alloys. AuSn is the “best” alloy to use due to its strong mechanical properties, fluxless and chemical-free etchant treatment compared to other indium, lead, and tin-based alloys. The QuikCool process was applied to AuSn eutectic-based alloys. The critical point in AuSn alloy is 280°C, the point at which both the solid and liquidus phases exist. Here, preform pieces of 1 mil AuSn (80wt% Au and 20wt% Sn) were used to join direct bonded substrates (DBCs) metallized with Si die attach. Thus, in order to achieve low void concentration <1% and reduction in cycle times in solder alloys, the QuikCool system feature is an excellent alternative.

We developed a process approach to a QuikCool system time above liquidus (TAL-critical point). See the graphs below; we compared two different profiles: normal rate profile vs. QuikCool with both profiles using ramp of 4.5 minutes to achieve void concentration <1%. The TAL of the normal rate profile was seen to have ~4.75 minutes at 280°C, whereas at 300°C was ~3.00 minutes.

SST

                                          a)

SST
                                             b)

The TAL with QuikCool rate profile at 280°C was ~2.50 minutes whereas at 300°C was ~1.50 minutes. The void concentration of the normal rate profile was ~0.91% increase in void concentration as compared to the QuikCool rate profile. Void concentrations are shown below in figures C and D, respectively. A decrease in void concentration was achieved with the QuikCool rate profile as compared to the normal rate profile.

SST
                                            c)

SST
                                          d)


Adrienne D. Williams, Ph.D.
Process Engineer
SST International

 

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:: Micro Systems Technologies, Inc. receives ITAR registration – Come visit our booth (#123) at IMAPS Pasadena

Micro Systems Technologies, Inc. (MSTI), located in Mesa, Arizona, is now qualified to work on projects which are subject to ITAR or EAR regulations.  Our offering includes ultra-HDI/microvia flex, rigid-flex or rigid PCBs and LCP based substrates for aerospace & defense applications requiring the highest reliability and performance. The sophisticated solutions are manufactured according to the EN 9100:2009 standard, guaranteeing highly effective processes and 100% traceability.

For further information please contact:  Micro Systems Technologies, Inc., 1839 S. Alma School Road,
Suite 270, Mesa, AZ 85210-3024, phone: (480) 398 1496, or via unrestricted email* to sales.msti@mst.com, or visit booth# 123 at IMAPS Pasadena. 

*Please note: No ITAR or EAR data should be sent to us via email.

www.mst.com

MST


LCP substrate for HF & microwave applications

 

 

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:: Indium Corporation Experts to Present at IMAPS 2016

Premier Tech Sponsor - Indium Corp.

Several Indium Corporation experts will share their knowledge and expertise at IMAPS 49th International Symposium on Microelectronics (IMAPS 2016 - Packaging the Connected World), Oct. 10-13, in Pasadena, Calif.
The following technical papers authored by Indium Corporation experts will be featured: 

  • Voiding Control in Preform Soldering by Dr. Ning-Cheng Lee, Vice President of Technology
  • Avoid the Void by Edward Briggs, Senior Technical Support Engineer
  • Evaluating the Effect of SMT Material & Process Variables on Voiding Under QFNs by Maria Durham, Technical Support Engineer, Semiconductor and Advanced Assembly Materials; and Brandon Judd, Technical Support Engineer, Southwest/Rocky Mountains U.S.
  • Metallic TIM Testing and Selection for IC, Power, and RF Semiconductors by Tim Jensen, Product Manager for Engineered Solders Materials; and David Saums of DS&A LLC
  • Challenges in Fine-Feature Solder Paste Printing for SiP Application by Sze Pei Lim, Semiconductor Product Manager – Southeast Asia; and Kenneth Thum, Senior Technical Support Engineer

Additionally, Dr. Ning-Cheng Lee is teaching two professional development courses:

  • Achieving High Reliability Lead-Free Solder Joints – Materials Consideration
  • It is Time for Low Temperature – Low Temperature Solders, New Developments, and Their Applications

To register for the IMAPS conference, visit: www.imaps.org/imaps2016/.
Indium Corporation is a premier materials manufacturer and supplier to the global electronics, semiconductor, thin-film, thermal management, and solar markets. Products include solders and fluxes; brazes; thermal interface materials; sputtering targets; indium, gallium, germanium, and tin metals and inorganic compounds; and NanoFoil®. Founded in 1934, Indium has global technical support and factories located in China, Malaysia, Singapore, South Korea, the United Kingdom, and the USA.
For more information about Indium Corporation, visit www.indium.com or email abrown@indium.com. You can also follow our experts, From One Engineer To Another® (#FOETA), at www.facebook.com/indium or @IndiumCorp.

 

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:: Royce Instruments and V-TEK International introduce new AP+ - Come Learn more at Booth #403 in Pasadena Next Week!

Highly customizable die sort solution offers multiple wafer and tray input options, adds output to tape and reel or tray.

Royce Instruments and V-TEK International today announced the release of their new automated die sorter, the AP+. The AP+ will be showcased at the upcoming IMAPS 2016 Symposium on Microelectronics in Pasadena, California from October 10-13, 2016.

With over 30 years in the electronic component processing and packaging industry, Royce and V-TEK each bring a wealth of experience to the design table. The result is the AP+, a flexible solution that merges Royce’s capability of processing highly sensitive die with V-TEK’s most advanced taping technology.


The highly customizable AP+ offers a variety of automated input and output options while maintaining fast change-over between processes. Die input is from wafer, waffle pack, Gel-Pak, JEDEC tray or custom tray using an input map. Output options are the same with the addition of a new tape and reel system.  The AP+ taper features an adjustable width track with heat and pressure seal options.


Die Sort Manager Software provides input to output traceability at the die level. Die Sort modes include pizza map or reticle mask wafer mapping, ink dot recognition and pick all die. AP+ options include non-surface die pick-up, 180 degree die flip and taper post-place vision inspection.

With its multi-project wafer mapping capability and quick-change fixtures and tooling, the AP+ is ideal for supporting medium volume, high mix environments.

For more information on the AP+,
please contact:

Bill Coney
Business Development Manager
Royce Instruments, LLC
831 Latour CT, Suite C
Napa, CA 94558
707.975.2846
bconey@royceinstruments.com

Royce

 

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:: Issue 195 ::
October 4, 2016

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