PDC 1 -- 3D Integration: Technology, Applications & Markets for 3D Integrated Circuits
Philip Garrou
Microelectronic Consultants of NC
This course is based on the authors activity over the past 7 years with numerous companies in the industry, his weekly 3D blog “Insights From the Leading Edge “ in Solid State Technology and the 2nd volume Wiley-VCH book “Handbook of 3D IC Integration: Technology and Applications of 3D IC Circuits” which he authored. The course will begin by defining and contrasting 3D Integration (thinning, bonding and TSV) to 3D packaging (thinning, stacking and wire bonding to the BGA base). The various drivers for 3D integration including the electrical performance and economic issues will be examined. We will examine the various process sequences being proposed for 3D integration and the process unit operations necessary to fabricate a 3D stack. The process sequences proposed by IDMs, Universities, and Institutes will be compared and contrasted. We will then examine applications and the evolving infrastructure that will be necessary to accomplish this. The course will end by looking at the remaining technical and market barriers (design, thermal and test) and looking at the current best sources of 3D information.
Who Should Attend?
The course will be aimed at technical personnel wanting a status review of the subject and marketing/management personnel looking for a status report to help determine their position in the business food chain.
Biography
Philip Garrou
Microelectronic Consultants of NC
Dr. Garrou consults in the areas of 3D IC integration, thin film technology, IC packaging and microelectronic materials. Dr. Garrou is a fellow of IEEE & IMAPS and was President of the IEEE CPMT (2003-2005) and IMAPS (1998). He is currently a contributing editor and weekly 3D IC blogger for Solid state Technology magazine “Insights From the Leading Edge”. Dr Garrou is a Sr. Analyst and contributor for the Yole Developpment “i-Micronews” and Yole newsletters. He has authored / co-authored > 100 technical publications and book chapters. He edited and authored the 2008 “Handbook of 3D Integration: Technology and Applications of 3D Integrated Circuits” for Wiley-VCH.
PDC 2 -- Advanced Packaging Technologies: Chip Scale & Embedded Chip
This course has been cancelled
Ray Fillion
GE Global Research, Retired
Consultant
Advances in microelectronics packaging have become as critical to the leading edge portable and computer industries as have the advances in semiconductor technologies. Semiconductor advances have provided ever more functionality in a smaller chip footprint. But with that comes an increase in device power requirement, cooling needs and I/O count. There are a small but important number of microelectronics packaging advances that have enabled fabricators and OEMs to efficiently put these latest chips into viable products. These include chip scale packaging and the newest advance, embedded chip packaging.
This course covers wafer level and package level chip scale approaches, and single chip and multichip embedded ICs. It will look at the basic features of these packaging approaches, their construction and their processes. It will look at the leading approaches to these technologies and their inherent advantages and disadvantages. This course will cover issues yield losses, component handling and electronic test. The course will look at the leading companies implementing various versions of these technologies, cover the key differentiators between them and show how these devices have contributed to the advancements made in a wide range of both portable and high-end electronics.
Course Outline:
- General Packaging and Interconnection Requirements
- Semiconductor Advances
- Advanced Packaging Needs
- Package Level Chip Scale Packaging
- Structures & Processes:
- Practitioners:
- Advantages & Features
- Wafer Level Chip Scale Packaging
- Structures & Processes:
- Practitioners:
- Advantages & Features
- Embedded Chip
- Structures & Processes:
- Practitioners:
- Advantages & Features
- Issues and Concerns
- Costs
- Reliability
- Availability
- Future Advancements
- Summary
Who Should Attend?
This course covers basic and advanced topics for product and design engineers, manufacturing process and assembly/packaging engineers, engineering managers, senior design technicians, consultants and academic specialists as well as marketing and sales personnel requiring an understanding of the capabilities, implications and options of advanced packaging and assembly technologies.
Biography
Ray Fillion
GE Global Research, Retired
A BSEE graduate of University of Massachusetts, Ray Fillion focuses in the areas advanced packaging and interconnection for next generation microelectronics systems. Ray has more than 40 years experience at GE in Aerospace Electronics and Global Research in all aspects of microelectronics in technical, management and business development positions. Mr. Fillion also serves or has served on Advisory Boards for a variety of technical societies, industry, academic institutions and governmental funded institutions. He has taught courses on advanced packaging for SMTA, GE and several universities. He was the lead inventor of the embedded chip technology at GE with most of his 27 issued US patents covering embedded chip technologies. His other technical areas of expertese include advanced microprocessor carriers, chip scale packages, multichip modules, 3-D packaging, power packaging, packaging for cryogenic electronics, and microwave packaging.
- Program Director of the GE Embedded Chip Development
- Inventor: 27 Issued US Patents
- Director GE Licensing: Microelectronics (2005-2008)
- IEEE MCM and JC-92 Standards Committees (1982-1984, 1990-1991)
- Georgia Tech PRC Technical Advisory Board (2004-2006)
- Technical Advisory Board: SUNY Binghamton IEEC (2000-2004)
- IMAPS Outstanding Paper Award (2001, 2002, 2003)
- IMAPS Best Paper of Session Awards: (1994(2), 1997, 2001, 2002, 2003)
- IMAPS Advanced Microelectronics and Journal of Microelectronics: Technical Papers (8)
- IMAPS Chapter Presentations: Metro, Keystone, New England, Garden State, Empire
- GE Research Whitney Technical Achievement Award (2004)
- Technical Advisory Board, Optical Electronics Industry Association
- Co-author OEIA Solid State Lighting Initiative Report
- Technical Advisory Board: Endicott Interconnect (5 years)
- Board Member Symposium of Polymers in Microelectronics (10 years)
- Technical Chair: IMAPS Mid-Atlantic Microelectronics Packaging Conference 2010
- Electronics Components & Technology Conference (Technical Committee: 1995–2001)
- Technical Conference Session Chair: 15 times (various technical societies)
- Authored more than 125 technical presentations, journal papers, technical articles.
- Short Course Instructor: SMTA, Georga Tech, Cornell, University of Binghamton, GE
