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IMAPS Traveling Professional Development Courses (PDCs)

June 24, 2009
Research Triangle Park, North Carolina - USA

Sigma Xi - The Scientific Research Society, 3106 East NC Highway 54, RTP, NC 27709

Wire Bonding in Microelectronics
Presented by: Lee Levine, Process Solutions Consulting
June 24, 2009 | 8:00am - 5:00pm EDT (Full-Day Course)

3D IC Integration: Status and Overview
Presented by: Dr. Phil Garrou, Microelectronic Consultants of NC
June 24, 2009 | 1:00pm - 5:00pm EDT (1/2 Day Course)

Register On-line

Early Registration Deadline: Friday, June 5, 2009
All Registration Closes: Friday, June 12, 2009


Wire Bonding in Microelectronics
Presented by: Lee Levine, Process Solutions Consulting
June 24, 2009 | 8:00am - 5:00pm EDT

Key Words

Wire bond, intermetallic, ultrasonic welding, semiconductor packaging, BGA. 3D packaging, SOP

Course Description

Wire bond manufacturing defects range typically from about 50 to 1000 ppm, with exceptions to >10,000 and <50 ppm. In order to achieve the low defect rates in production, one must understand all of the conditions that affect both bond yield and reliability. This course will discuss many small- and large-wire bonding problems, as well as subjects of specific interest to hybrid/MCM device bonding. In addition, a number of advanced topics, such as high yield, fine pitch (towards 25 µm ball bond pitch), and bonding to flex will be covered. Newer developments are included along with a major discussion of wire bonding to multichip substrates, soft substrates, Cu-Lok and the special intermetallic problems occurring when fine pitch chips are used. Wire bond testing and metallurgy (covering both aluminum and gold bonds); intermetallic compounds in general; cratering; cleaning for high yield and reliability; failures resulting from electroplating; mechanical problems in wire bonding; new bond technologies and developments; how ultrasonic bonds are formed, and the metallurgy of gold and aluminum wire. It concludes with methods of making very low loops and the implementing of Flip Chip by using wire bonding/stud bumping techniques.

Recommended Text Book

Wire Bonding in Microelectronics, George Harman, McGraw Hill, NY, 1997 (List price $80). NOT required for class and NOT provided with your registration. May be available for an additional fee.

Presenter

Lee is an internationally recognized semiconductor assembly process expert with over 25 years of targeted experience in technical process development and optimization. He is known for keen analytical and troubleshooting skills in the creative and effective resolution of problems in production processes. He consistently produces business results that create enhanced revenue opportunities, higher yields and trouble free operations.

Experience:
Previous experience includes 20 years as Principal and Staff Metallurgical Process Engineer at Kulicke & Soffa and Distinguished Member of the Technical Staff at Agere Systems. He was awarded 4 patents, published more than 50 technical papers, and won the 1999 John A. Wagnon Technical Achievement award from the International Microelectronics and Packaging Society, IMAPS. Major innovations include copper ball bonding, loop shapes for thin, small outline packages (TSOP and TSSOP, and CSPs) and introduction of DOE and statistical techniques for understanding assembly processes. He is a Fellow and V.P Technology for IMAPS.

Lee is a graduate of Lehigh University, Bethlehem, Pa where he earned a degree in Metallurgy and Materials Engineering.

Register On-line

Early Registration Deadline: Friday, June 5, 2009
All Registration Closes: Friday, June 12, 2009

Thomas Green

3D IC Integration: Status and Overview
Presented by: Dr. Philip Garrou, Microelectronic Consultants of NC (MCNC)
June 24, 2009 | 1:00pm - 5:00pm EDT

Course Description

3D IC Integration is without question the hottest topic in Microelectronics today. This course has been put together based on the authors activity in this field for the past 5 years which has included direct programs with numerous companies in the industry,his weekly 3D blog “Perspectives From the Leading Edge" in Semiconductor International and editing the 2008 (2) volume Wiley-VCH text “Handbook of 3D IC Integration: Technology and Applications of 3D IC Circuits”. The course will define and contraste 3D Integration (thinning, bonding and TSV) to 3D packaging (thinning stacking and wire bonding to a BGA base). We will look at drivers for 3D integration including the electrical performance and economic issues that are about to end CMOS device shrinkage, and the miniaturization issues faced in todays portable devices. We will then look at various proposed process sequences and the process unit operations necessary to fabricate 3D stacks. The processes sequences proposed by Universities, Institutes and commercial entities will be compared and contrasted and we will examine early adopter applications such as CIS [CMOS image sensors]; memory [DRAM and NAND]; memory on logic and heterogeneous integration. The course will end by looking the remaining technical and market barriers (design, thermal and test) and looking at the current best sources of 3D information.

Who Should Attend?

The course will be aimed at technical personnel wanting a status review of the subject and marketing/management personnel looking for a status report to help determine their position in the business food chain. In the next few years 3D integration will have a rippling effect throughthe microelectronics industry and those who are caught unaware will be sorry.

Recommended Text Book

Handbook of 3D IC Integration: Technology and Applications of 3D IC Circuits; Wiley-VCH, 2008. NOT required for class and NOT provided with your registration. May be available for an additional fee.

Presenter

Dr. Garrou is a fellow of both IEEE (2001) and IMAPS (2000)and has served as President and Technical VP of IEEE CPMT and IMAPS. He is currently Editorial Advisor and 3D integration blogger ("Perspectives From the Leading Edge")for Semiconductor International. He has authored 3 microelectronic texts including: “Handbook of 3D IC Integration: Technology and Applications of 3D IC Circuits”; Wiley-VCH, 2008 and "Enabling Technologies for 3D Integration" MRS Vol. 970, 2006. Dr. Garrou has been awarded the 2007 IEEE CPMT Sustained Technical Contributions Award for “ …25 years of leadership and technical contributions in thin film dielectric materials and microelectronic applications such as multichip modules, bumping and wafer level packaging, integrated passives, o-LEDs and most recently 3D integration" and the 2001 IMAPS WD Ashman Achievement Award for “... technical contributions to the Microelectronics Packaging Industry”.


Register On-line

Early Registration Deadline: Friday, June 5, 2009
All Registration Closes: Friday, June 12, 2009

Thomas Green



 


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