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Preliminary Program Agenda

IMAPS Advanced Technology Workshop on

Advanced 3D Packaging
Innovations and Applications for MCM
and System-in-Package Technology

March 11-13, 2003
Renaissance Harbor Place Hotel
202 East Pratt Street, Baltimore, MD

General Chair:

Phillip Zulueta
Jet Propulsion Laboratory NASA
P: 818-354-1566; F: 818-393-5245
Phillip.j.zulueta@jpl.nasa.gov
  

Technical Chair:

Vern Solberg
Tessera
P: 408-383-3614; F: 408-894-0768
vsolberg@tessera.com
 

 

Don't miss the Military, Aerospace, Space and Homeland Security ATW being held in conjunction with this workshop. Receive a special discount for attending both workshops!


View Program By Day: Tuesday (Day 1) | Wednesday (Day 2) | Thursday (Day 3)
View Program By Session: 1a | 1b | 2 | 3 | 4 | 5 | 6
Register On-Line and $ave

Tuesday, March 11

Registration: Noon - 4:30 pm

Welcome Introduction: 2:00 pm
General Chair: Phillip Zulueta, JPL

Session 1A
Market Drivers for 3D Package Technology
Chair: Vern Solberg, Tessera Technologies
2:30 pm - 3:30 pm

Market Outlook for CSP and 3D Packaging
Jim Walker, Gartner Dataquest

SiP - Technology Challenges and Market Opportunities
Charles G. Woychik, William Chen, Jennifer Yuen, ASE (U.S.) Inc.; Jordan Tsai, Advanced Semiconductor Engineering, Inc. Kaohsiung (ASEK)

Break: 3:30 pm - 4:00 pm

Session 1B
OEMs Requirement for High Density Packaging
Chair: Vern Solberg, Tessera Technologies
4:00 pm - 5:00 pm

High Density Circuits Technologies for Microelectronics Manufacturing
Jeffrey Flammer, HEI, Inc.

Supply Chain and Business Challenges Associated with 3D Packaging
Joseph Adam, Skyworks Solutions, Inc.

Reception/Dinner: 5:00 pm - 7:00 pm


Wednesday, March 12

Registration: 7:15 am - 5:30 pm

Breakfast: 7:30 am - 8:30 am

Session 2
3D IC Packaging Technologies and Innovation
Chair: Phillip Zulueta, Jet Propulsion Laboratory NASA
8:30 am - 10:00 am

Emerging Technologies; Business and Logistics Issues
Brandon Prior, Prismark Partners

Folded and Stacked 3D Packaging
Steve Greathouse, Intel

Applications and Advances in Chip Scale Package Stacking
Lee Smith, Tessera Technologies

Break: 10:00 am - 10:30 am

Session 3
Package Strategy for Wireless Electronics
Session Chair: Jim Walker, Gartner Dataquest
10:30 am - Noon

System-In-Package: An Alternative to System-on-Chip Solutions
Frank Jurskey, Advanced Interconnect Technologies, Inc.

System in Module using Passive and Active Components Embedding Technology
Toshiyuki Asahi, Matsushita Electric Industrial Co., Ltd.

Integrating Active and Passive Functions for RF Applications
Catherine de Villeneuve, Tessera Technologies, Inc.

Lunch: Noon - 1:00 pm

Session 4
Vertical Stacked Die and Stacked Package Solutions
Session Chair: Lee Smith, Tessera Technologies
1:00 pm - 3:00 pm

Vertical Stacked 3D Packaging for Ultrafast Imaging
Kris Kwiatkowski, Los Alamos National Laboratory; J.C. Lyke, Air Force Research Laboratory; R.J. Wojnarowski, C. Kapusta, General Electric

Bumpless 3D Stacked Packages for Density/Functionality Driven Devices
Charles W. C. Lin, Sam C.L Chiang, T. K. Andrew Yang, Bridge Semiconductor Corp.

Low Profile Ball Stacked CSP for DDR II and RDRAM
Roger Mangrum, DPAC Technologies

Vertically Integrated Thin Chip Stack Utilizing a Seamless High Connectivity Process
David Scheid, Union Semiconductor Technology Corp.

Break: 3:00 pm - 3:30 pm

Session 5
Package Assembly; Methodology and Materials
Session Chair: David Gerke, Jet Propulsion Laboratory NASA
3:30 pm - 5:30 pm

Package Level System Integration Enabling Solutions
Marcos Karnezos, ChipPAC

Through Silicon via (TSV) 3D Layer Stack for Advanced VLSI
S. Spiesshoefer, L. Schaper, University of Arkansas

Study on Laminate Substrate Design and Packaging Technology for Package Stackable CSP
Akito Yoshida, Amkor Technology Inc.

Evaluation of 3D Plus Packaging Test Structures for NASA Goddard Space Flight Center
Jeannette Plante, Dynamic Range Corporation; Harry Shaw, NASA Goddard Space Flight Center

Reception/Dinner: 6:00 pm - 8:00 pm


Thursday, March 13

Registration: 7:15 am - noon

Breakfast: 7:30 am - 8:30 am

Session 6
3D Package Design for Performance and Reliability
Session Chair: Steve Greathouse, Intel Corp.

10:30 am - Noon

Edge Flower Chip Carrier efficiently provides more Connectivity
Arthur R. Zingher

Failure Analysis of Electrostatic Discharge and Electrical Overstress Failures of GaAs MMIC
Yu-chul Hwang, Mikyoung Lee, Michael Pecht, University of Maryland

EDA Software for Advanced 3D Technologies
Andres Carrasco, CAD Design Software

Break: 10:00 am - 10:30 am

Thermo-Mechanical Analysis of Thru-Silicon-Via in Ultra Thin Wafers for Z-Axis Interconnect Technologies
Parthiban Arunasalam, Matthew H. Gordon, Leonard W. Schaper, University of Arkansas

System-in-Package; Managing Multiple Die Sourcing
TBD, Chip Supply

Concluding Remarks: Noon

Register On-Line and $ave

Don't miss the Military, Aerospace, Space and Homeland Security ATW being held in conjunction with this workshop. Receive a special discount for attending both workshops!

 



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IMAPS-International Microelectronics And Packaging Society and The Microelectronics Foundation
611 2nd Street, N.E., Washington, D.C. 20002
Phone: 202-548-4001

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