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IMAPS and SEMI proudly announce a
Topical Workshop on

Advanced Interconnect Technologies
Wednesday, July 14, 2010
San Francisco Marriott Hotel
San Francisco, CA

This event will be co-located with IMAPS Workshop on Wire Bonding
and with SEMICON West 2010

Early Registration Deadline: June 25, 2010

Chair:

Co-Chair:

Anwar Mohammed
Huawei Technologies amohammed@huawei.com

Zhihao Yang
NanoMas Technologies zhihao.yang@nanomastech.com



Workshop Focus:
The Advanced Interconnect Technologies Workshop has been organized to allow for the presentation and debate of some of the latest interconnect and processing technologies in Electronic Packaging.

Wednesday, July 14, 2010

Registration: 7:00 am - 5:00 pm

Continental Breakfast: 7:00 am - 8:00 am

Opening Remarks: 8:20 am - 8:30 am

Keynote Presentation: 8:30 am - 9:30 am
Future Interconnect Demands for Super Computing
How T. Lin, Ph. D., Endicott Interconnect Technologies, Inc.

Dr. Lin is a Chief Scientist in the R&D group of Endicott Interconnect Technologies, Inc. and holds a Ph. D. in electrical Engineering from Rensselaer Polytechnic Institute. He earned both MSEE and BEE in EE both from Georgia Institute of Technologies. He was with IBM MD from 1977 to 2001 where he developed large scale precisions artwork generators and high-speed PWB testers. Currently, he is the TA of company CTO at Endicott Interconnect Technologies working on developing advanced computing architectures, advanced electronic packaging technologies and optical interconnects. Dr. Lin has received three IBM Outstanding Innovation/Achievement Awards and 40 US issued Patents. He has published over 30 journal articles in the area of optical interconnects, electronic and electro optical packaging.

Session 1: 3D Interconnect
Session Chair: Anwar Mohammed, Huawei Technologies
9:30 am - 12:00 pm
The next significant frontier in Semiconductor Packaging is 3D integration. It offers many promises and expectations and yet there are substantial challenges that need to be surmounted. The touted benefits include enhanced performance, lower power consumption, optimized real estate utilization, improved reliability and yields and reduced packaging and overall cost. It is also envisaged that this technology will play a leading role in board size reduction and integration which will be a salient challenge in the very near future. However, promising 3 D approaches like Through Silicon Vias (TSVs) and others will need to solve critical processing, manufacturing and supply chain issues before the technology can claim an acceptable level of maturity that can lead to mass conversions.  This session will cover some of those challenges and alternative approaches to overcome them.

Sub-70 mm Dispensable Interconnects for 3D System-In-Package Assemblies
Suzette K. Pangrle, Jeff S. Leal, Marc Robinson, Bruce King, Mark Kowalski, Sunil Kaul, Vertical Circuits, Inc.

Break: 10:15 am - 10:30 am

Advances in Wafer Bonding Techniques Enabling Vertical Integration
Bioh Kim, Thorsten Matthias, Markus Wimplinger, Paul Lindner, EV Group

Aerosol Jet® Printer as an Alternative to Wire Bond and TSV Technology for 3D Interconnect Applications
Michael O'Reilly, Michael J. Renn, Bruce H. King, Optomec, Inc.

Lunch On Your Own: 12:00 pm - 1:30 pm
Take some time to visit SEMICON West 2010 - www.semiconwest.org

Session 2: Advanced Interconnect Materials/Processes
Session Chair: Zhihao Yang, NanoMas Technologies
1:45 pm - 5:00 pm
Innovative materials and processes are the key enablers for continuous development of advanced interconnect technologies for electronic packaging, such as 3D and high density packaging, photonic/optoelectronic packaging, underfill/encapsulants and adhesive, flip-chips, wirebonding and stud bumping, ceramic, polymer, nanomaterials,  conductive materials, Cu/low-K, etc. Presentations in this session will cover the most recent developments in materials and processes for advanced interconnect technologies.

Electromigration Performance of Fine-pitch µPILR Interconnects in Flip Chip
Rajesh Katkar, Laura Mirkarimi, Ilyas Mohammed, Tessera Inc.

Printing Conductive Traces using Nano Silver-Based Inks
David Van Heerden, Hichang Yoon, Yu Do, Zhihao Yang, NanoMas Technologies 

Break: 3:15 pm - 3:30 pm

A First Individual Solder Joint Encapsulant Adhesive
Wusheng Yin, Mary Liu, YINCAE Advanced Materials, LLC

Optical Interconnect Using Optopolymer Material
How Lin, Benson Chan, David Bajkowski, Jay Huang, Endicott Interconnect Technologies, Inc.

Closing Remarks: 5:00 pm


Register On-line



Housing: Hotel Cut-off is July 1, 2010

The IMAPS Topical Workshop is being run at the San Francisco Marriott Hotel, in conjunction with SEMICON West.

San Francisco Marriott Hotel
55 Fourth Street
San Francisco, CA 94103

To book online, Please visit the official housing site: Several hotels to choose from. Room Rates Vary. https://www.cmrhousing.com/SEMI_S6/HotelList.aspx

Or call the SEMICON West Housing Office
Monday - Friday, 6:00am - 6:00pm Pacific Standard Time
1.800.421.2499 (US & Canada)
1.415.979.2287 (International)
Please reference SEMICON West when making reservations by phone.

Speaker Dates/Information:

  • Abstract(s) due to IMAPS: April 30, 2010
  • Speaker Notification/Confirmation emailed: May 10, 2010
  • Extended Abstract or Presentation Material due: June 18, 2010
  • Powerpoint/Presentation file for CD-Rom due not later than: July 15, 2010
  • Powerpoint/Presentation file used during session: Speaker's responsibility to bring to session on USB and/or CD (recommended to have back-up on personal laptop or email to jmorris@imaps.org prior to event)
  • Technical Presentation Time: 45 minutes (40 to present; 5 for Q&A)

 


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IMAPS-International Microelectronics And Packaging Society and The Microelectronics Foundation
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Phone: 202-548-4001