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IMAPS Advanced Technology Workshop on
Packaging Copper/Low-K Semiconductors

December 15 - 17, 2003

Red Lion Hanalei Hotel
2270 Hotel Circle North
San Diego, CA 92108
P: 619-293-7302; F: 619-297-0555
http://www.hanaleihotel.com
Hotel Cutoff: October 31, 2003

General Chair
Dr. Andrew J.G. Strandjord, IC Interconnect
P: 719-533-1030 ext:13
astrandjord@icinterconnect.com

Sponsored by:
International Microelectronics And Packaging Society (IMAPS)

$ave on the Technical Program Registration when you Register On-Line

Early Registration and Hotel Deadline: October 31, 2003




Monday, December 15

Registration: 11 am - 5 pm

Opening Remarks: 1:45 pm - 2 pm
General Chair

Session I: Copper/Low-K
Session Chairs: Eric Beyne, IMEC; Scott Cummings, Dow Chemical
2 pm - 5 pm

Packaging Integration Issues with Low-K Dielectrics
Scott Cummings, Mike Mills, Joost Waeterloos, Dan Scheck, Dow Chemical

EMC Characterization for Improved T/C Reliability of Copper/Low K Chip Packaging
Min Yoo, Jiyoung Chung, Heeyoul Yoo, Kyeongsool Seong, Joonyeob Lee, Keunsoo Kim, Yoonjoo Khim, Seokho Na, Jinyoung Khim, Amkor Technology

Break: 3:30 pm - 4 pm

Rapid Reliability Assessment of ULSI Electronics with Copper-Low K Interconnects
Pat McCluskey, Shirish Gupta, University of Maryland

A Tale of Two Packages: Packaging Comparison for the Motorola MPC7410 PowerPC® Copper Processor
Linda Bal, Andrew Mawer, Motorola

Reception: 5 pm - 5:30 pm
Dinner: 5:30 pm - 7 pm


Tuesday, December 16

Registration: 8 am - 9:30 pm

Continental Breakfast: 8 am - 9 am

Session II: Materials
Session Chairs: Frank G. Shi, University of California - Irvine; Harry Fuerhaupter, Atotech Deutschland
9 am - Noon

Development of Low Stress Materials for Low-K Copper Integrated Circuit Packaging
Michael G. Todd, Larry Crane, George Carson, Jack Zhang, Vincent Villeda, Kathy Costello, Henkel Loctite Electronic Materials

Epoxy Molding Compound for Low-K Die
Shinichi Zenbutsu, Sumitomo Bakelite Co., Ltd.

Ultra Low-K Dielectric Insulators for On-Chip Interconnects: Materials Challenges and Potential Solutions
Willi Volksen, R. D. Miller, V. Lee, T. Magbitang, H. C. Kim, IBM Corporation

Break: 10:30 am - 11 am

Impact of Copper Low-K Materials on Advanced Interconnect Packaging
Surasit Chungpaiboonpatana, Frank G. Shi, University of California - Irvine

Electroless Ni/Au for Low-K Copper Devices - A Technology Roadmap
Thorsten Teutsch, Ronald G. Blankenhorn, Elke Zakel, PacTech USA - Packaging Technologies, Inc.

Lunch: Noon - 1 pm

Session III: Handling/Assembly
Session Chairs: Thorsten Teutsch, PacTech USA; D. Tonnies, SUSS MicroTec - Germany
1:30 pm - 4:30 pm

A Scribe and Saw Technique for Dicing Wafers with Low-K Dielectric/Metal Stacks
Pradeep Subrahmanyan, Electro Scientific Industries Inc.

Copper Electroplating Process with Improved Stability, Conductivity and Total Cost of Ownership
Harry Fuerhaupter, Robert Preisser, Thomas Dretschkow, Atotech Deutschland

Technology Enhancements in Full-Field Lithography to Meet 300mm Wafer-Level Packaging Requirements for Cu/Low-K Wafers
Klaus Ruhmer, SUSS MicroTec, Inc.; Dietrich Tonnies, Joe Kramer, SUSS MicroTec - Germany

Break: 3 pm - 3:30 pm

Composite Cost of Ownership of a 300mm Electroplating Bumping Line from UBM thru Singulation
Paul Siblerud, Semitool & Secap; Deitrich Tonnies, SUSS MicroTec - Germany

Electro-Chemically Deposited Copper for Packaging Applications
Bioh Kim, Tom Ritzdorf, David Erickson, Charles Sharbono, Semitool, Inc.

Reception: 5 pm - 5:30 pm
Dinner: 5:30 pm - 7 pm

Session IV: Wirebonding
Session Chairs: George Harman, NIST; Bob Chylak, K&S
7 pm - 9:30 pm

Packaging of Cu/Low-K IC Devices: A Novel Direct Fine Pitch Gold Wirebond Ball Interconnects onto Copper/Low-k Terminal Pads
Surasit Chungpaiboonpatana, Frank G. Shi, University of California - Irvine

Emerging Heavy and Fine Copper Bonding Wire for Chip Packaging
Z. Guo, L. Monterulo, C. V. Pham, K. Huth, Semiconductor Packaging Materials, Inc.

Automatic Copper Wire Bump and Ball Bonding
Bryan V. Drew, Palomar Technologies

Simulation of Wirebond Stresses under Bondpads in Copper/Low-K Technology
Kevin J. Hess, Susan H. Downey, Tom Lee, Lei L. Mercado, James W. Miller, Motorola

Successful Demonstration of Wire Bonding and Flip Chip Assembly on Cu-CVD Low K Interconnect
Tony Pan, Applied Materials; Jamin Ling, ST Assembly Test Services; Tom Strothmann, Jon Brunner, Frank Keller, K&S; George Carson, Renzhe Zhao, Henkel Loctite Corporation


Wednesday, December 17

Registration: 8 am - Noon

Continental Breakfast: 8 am - 9 am

Session V: Flip Chip
Session Chairs: R. Wayne Johnson, Auburn University; John U. Knickerbocker, IBM
9 am - Noon

Impact of Flip Chip Packaging on Interfacial Delamination in Cu/Low K Structures
Guotao Wang, Steven Groothuis, Paul S. Ho, University of Texas at Austin

Impact of Intermetallic Formation and Electro-Migration on the Integrity of Bumped Cu/LowK Dies
Riet Labie, Eric Beyne, Dominiek Degryse, IMEC

Finite Element Modeling of Shear Test on Bumped Cu-lowK Wafers
Dominiek Degryse, Riet Labie, Bart Vandevelde, Eric Beyne, IMEC

Break: 10:30 am - 11 am

Flip Chip Underfill Technology Development for Next Generation Silicon Technologies
Kumar Nagarajan, Kishor Desai, LSI Logic Corporation; Michael Todd, George Carson, Henkel Loctite

Bumpless Flip Chip Package for Copper/Low-K Semiconductor Devices
Charles W. C. Lin, Sam C. L. Chiang, T. K. Andrew Yang, Bridge Semiconductor Corporation

Concluding Remarks


Register On-line and $ave





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