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International Conference and Exhibition on
Device Packaging

Doubletree Hotel
Scottsdale, Arizona USA

Device Packaging General Chairs:
Ted Tessier, FlipChip International
Andrew Strandjord, FlipChip International
Device Packaging Technical Chairs:
Beth Keser, Freescale Semiconductor
Jon Aday, Amkor Technology Inc.
Conference and Technical Workshops
March 20-23, 2006
Exhibition and Technology Showcase
March 21-22, 2006
Professional Development Courses
March 20, 2006
GBC Spring Conference
March 19-20, 2006

Early-Bird Registration Ends: February 15, 2006
Hotel Cut-off: February 10, 2006

In conjunction with the Global Business Council (GBC) Spring Conference, March 19th & 20th
$100 discount if attending both Device Packaging and GBC

Exhibit Information | Exhibiting Companies | Floorplan | Reserve Booth(s)
GBC Spring Conference 2006

The Second Annual Device Packaging Conference (DPC 2006) is being held in Scottsdale, Arizona on March 20 - 23, 2006. It is an international event being organized and sponsored by the International Microelectronics And Packaging Society (IMAPS).

The Device Packaging Conference will feature keynote speakers, technical sessions, professional development courses, and a vendor exhibition and technology showcase. The conference aims to provide a focused forum to hear and discuss the latest technological developments in 5 topics areas related to microelectronics packaging: Optoelectronics; MEMS; Flip Chip Technologies; Copper/Low-K; and 3D Packaging. Technical presentations in these 5 topical areas will range from early stage design work and R&D, to systems manufacturing and production operations. The professional development courses which are offered, as well as the vendor exhibition and technology showcase, are also focused on the microelectronics and packaging aspects of these 5 topical areas and should provide a very valuable added resource to people attending the conference. The Global Business Council (GBC) will be offering a stellar Spring Conference, March 19th & 20th which will focus on the business side of these technologies (see the next page). There will also be several networking receptions and gatherings throughout the week, including the opening receptions, meals and other social events.

This conference is a major forum for the exchange of knowledge and provides numerous opportunities to network and meet leading experts in these 5 fields. The conference was organized to attract a fairly diverse group of people, across many different functional groups and experience levels within both industry and academics. People who would benefit from this conference include: scientists, process engineers, product engineers, manufacturing engineers, professors, students, business managers, sales, and marketing.

Professional Development Courses (PDCs)

7:00 am - 5:00 pm


7:00 am - 8:00 am


8:00 am - Noon

Morning Professional Development Courses (PDCs)
* Click on PDC title to see full description *

PDC1 - Area Array Microelectronics Package Reliability

Instructor: Amaneh Tasooji, Arizona State University

PDC2 - Hermeticity Testing and Issues with RGA

Instructor: Thomas Green, Microelectronics Packaging Consultant

PDC3 - Advanced Thermal Management Materials

Instructor: Carl Zweben, Advanced Thermal Materials Consultant

10:00 am - 10:20 am


1:00 pm - 5:00 pm

Afternoon Professional Development Courses (PDCs)
* Click on PDC title to see full description *

PDC4 - Reliability Methodologies for Fiber Optic Components

Instructor: David Maack, JDS Uniphase

PDC5 - Fundamentals of Packaging of MEMS and Related Microsystems and Nanomanufacturing

Instructor: Ajay Malshe, University of Arkansas

PDC6 - Microwave & Millimeter Wave Packaging; Basics, Materials and Processes

Instructors: Fred Barlow & Aicha Elshabini, University of Arkansas

3:00 pm - 3:20 pm


5:30 pm - 7:30 pm

Welcome Reception

Welcome Reception
(Device Packaging Conference)

Monday, March 20th
5:30 pm – 7:30 pm

GBC Attendees are Invited!

$100 Discount

when you register for the
Device Packaging Conference &
the Global Business Council Conference (GBC)

Keynote Presentation & Technical Sessions







7:00 am - 7:00 pm


7:00 am - 8:00 am


8:00 am - 8:45 am

Keynote Presentation
Electronics Packaging

Jim Fusaro, Amkor Technology

9:00 am - Noon

Optoelectronics - Interconnects and Data Transmission
Chair: Ephraim Suhir, University of California at Santa Cruz and Nanoconduction, Inc

MEMS - Sensors and Devices

Chair: Bruce Romenesko, John Hopkins University

Flip Chip - Wafer Bumping Technologies

Chair: Guy Burgess, FlipChip International LLC

Copper and 3D Sessions
begin on
Wednesday, March 22nd.

9:00 am

Dual Coated Optical Glass Fiber Subjected to Pull-Out Force

Ephraim Suhir, University of California at Santa Cruz and Nanoconduction, Inc.

Porous Ceramic Packaging for MEMS Chemical Sensors Requiring Environmental Access

Robert Dean, Nicole Sanders, Jeremiah Pack,Phil Reiner, Auburn University

C4NP - First Manufacturing & Reliability Data for High-End FlipChip Solder Bumping Based on IBM's C4NP Process

Klaus Ruhmer, Emmett Hughlett, SUSS MicroTec, Inc.; Dietrich Toennies, SUSS MicroTec - Germany; Peter Gruber, IBM Microelectronics, TJ Watson Research Center

9:30 am

Liquid Crystal Polymer Molded QFN Package for Microwave and Millimeter Wave Applications

Kunia Aihara, Anh-Vu Pham, University of California at Davis; John W. Roman, RJR Polymers Inc.

A Planar MEMS-Based Solid State Propellant Micro-Rocket with Micro-Igniter Micromachined on a Thin SiO2/SiNx Membrane

Amar Chaalane, C. Rossi, X. Dollat, L. Jalabert, D. Estve, LAAS-CNRS

High Speed Electrodeposition of Lead-Free Solder Bumps for Wafer Level Packaging

Zhenqiu Liu, Jim (Zhongqin) Zhang, Bill Wu, Arthur Keigler, NEXX Systems

10:00 am

Building a Packaging Hierarchy for Optical Interconnects using Polymer Waveguides: Exploring the Options

Stephen L. Buchwalter, Russell Budd, Frank R. Libsch, Bert Offrein, Yoichi Taira, IBM Corporation

MEMS Inertial Sensors and Wafer-Level Packaging

Changhan Hobie Yun, T. Lor, J. Villarreal, Analog Devices Inc.

Production Feasiblity of Electrodeposition of Tin-Silver-Copper for Wafer Bump Applications

Rozalia Beica, Eric Chiu, Angelo Chirafisi, Rohm and Haas Electronic Materials, L.L.C.

10:00 am - 7:30 pm

Exhibition & Technology Showcase

10:30 am

Break in Exhibit Hall

11:00 am

Embedded Thermoelectric Devices for Optoelectronic and Other High-Flux Cooling Applications

David A. Koester, Bob Conner, Randy Alley, Marco Soto, Nextreme Thermal Solutions, Inc.

A New Test Device for Characterization of Mechanical Stress caused Packaging Processes

Soeren Hirsch, Bertram Schmidt, University of Magdeburg

Process Integrity of Lead-Free Solder Bumping for Reliable Flip Chip Interconnects

Hirokazu Ezawa, Kazuhito Higuchi, Masaharu Seto, Masayuki Uchida, Toshiba Corporation Semiconductor Company

Copper and 3D Sessions
begin on
Wednesday, March 22nd.

11:30 am

Model LCP-Based Packages for Optoelectronic Devices

Raymond Pearson, Rajesh R. Gomatam, Jessica Goodell, John P. Coulter, Lehigh University

Leadless Chip Carrier for Microwave MEMS Packaging

Rick Sturdivant, MPT, Inc.

Lead Free Wafer Bumping Techniques with Solder Paste

Richard R. Lathrop, Heraeus Incorporated-Circuit Materials Division

Noon - 1:00 pm

Lunch in the Exhibit Hall







1:00 pm - 3:00 pm

Optoelectronics - Reliability
Chair: Stephen L. Buchwalter, IBM Corporation

MEMS - Assembly and Packaging

Chair: Robert Dean, Auburn University

Flip Chip - Future Directions in Wafer Bumping

Chair: Robert Darveaux, Amkor Technology

Copper and 3D Sessions
begin on
Wednesday, March 22nd.

1:00 pm

Liquid Crystal Polymer (LCP) based Opto and Electronic Packaging with Functionally Hermetic Performance

Linas Jauniskis, Foster-Miller, Inc.

Characterization of Strain Gauges Fabricated by Serigraphic Method

Bruno Luis Soares de Lima, Ana Neilde da Silva Rodrigues, Nilton Itiro Morimoto, Laboratrio de Sistemas Integrveis, USP

Stencil Printing Technology for Fine Pitch Deposition of Pb-Free Flip Chip Interconnects

Robert Kay, E. deGourcuff, I. Roney, N. J. Gorman, MicroStencil Limited

1:30 pm

Integrated Wafer Level Technology with Chip on Board Process Enables Higher Yields and Reduced Costs for Optical Devices

Yehudit Dagan, Vage Oganesian, Gil Perlberg, Osher Avsian, Shellcase Ltd.

Achieving and Maintaining High Vacuum Levels In MEMS Packages

David Muhs, Paul Barnes, SST International

SAC Low Voiding Pb-Free Solder Paste Optimization

Guy F. Burgess, FlipChip International, LLC

2:00 pm

Optimizing Interactions in Optoelectronic Packaging

John S. Mazurowski, Pennsylvania State University

A Cost-Effective Chip Scale Packaging

Guohong He, Discera Inc.

Experimental Study of Void Formation in Solder Joints of Flip-Chip Assemblies

Daijiao Wang, GrafTech International Ltd.; Ronald L. Panton, The University of Texas at Austin

2:30 pm


Low Temperature Wafer-Scale Thin Film Encapsulation for RF MEMS

Gilles Poupon, Charlotte Gillot, Emanuelle Lagoutte, Jean Louis Pornin, Nicolas Sillon, CEA-LETI

Current Challenges in Flip Chip Packaging Technology

Robert Darveaux, Miguel Jimarez, Amkor Technology

3:00 pm

Break in Exhibit Hall

4:00 pm - 6:00 pm

Optoelectronics - Packaging Adhesives and Analysis
Chair: Raymond Pearson, Lehigh University

MEMS - Wafer Bonding

Chair: Changhan Hobie Yun, Analog Devices Inc.

Flip Chip - Lead Free Bumping

Chair: Ted Tessier, FlipChip International LLC


4:00 pm

Evaluating the Dimensional Stability of Optoelectronic Adhesives

Raymond Pearson, Thomas Daugherty, Lehigh University

Investigations of Anodic Bonding for MEMS Wafer Level Package Applications

Hsueh-Kuo Liao, Hsieh-Shen Hsieh, Cheng-Chang Lee, Hwang-Kuen Chen, Tai-Kang Shing, Delta Electronics, Inc.

Investigation and Analysis on Ball Shear Strength using Sn-Ag-Cu Solder Alloy on Electroless Nickel-Gold Under Bump Metallization

Elsie A. Cabahug, Erwin Ian V. Almagro, Benjie B. Hornales, Fairchild Semiconductor

4:30 pm

Multilayer Adhesive Bonding under Hot Air Stream

Daniela Andrijasevic, Walter Smetana, Ioanna Gioroudi, Werner Brenner, Krzysztof Malecki, Vienna University of Technology

A Package Sealing Technique for Mercury Filled Microfluidic Devices

Daniel Harris, Robert Dean, Omkar Nadgauda, Nicole Sanders, Charles Ellis, Mike Palmer, Auburn University

Geometry and Bond Improvements for Wire Ball Bonding and Ball Bumping

Daniel D. Evans, Jr., Palomar Technologies

5:00 pm

Discoloration Kinetics of Epoxy Encapsulant Materials under Thermal and UV Treatment

Yuan-Chang Lin, Yan Zhou, Y. Z. He, Frank G. Shi, University of California, Irvine

Direct Bonding of SU-8 Cavities over MEMS Components

Donald W. Johnson, Milind P. Nagale, Joseph Molea, Michael Hornung, Volkan Cetin, MicroChem Corp.

Ultrasonic Horn Design Considerations for 100 Bump I/O Devices

Philip Couts, T. Nishioke, E. Onda, TDK Corporation of America

5:30 pm

Failure Analysis of LED using Magnetic Field Current Mapping

Sean Kim, Miky Lee, Craig Hillman, DFR Solutions

An Investigation of Focused Ion Beam Deposition as a Microjoining Technique

Gerald A. Knorovsky, J. R. Michael, B. L. Boyce, K. G. Janssens, P. C. Galambos, Sandia National Laboratories

Reliability of Gold-Solder Bump Joint

Yong-Bin Sun, Jae-Yun Kim, Kyonggi University

6:00 pm - 7:30 pm

Reception in the Exhibit Hall

Conference Registration

Advance Rate Ends:
February 15, 2006

Exhibit Booth Deadline:
February 15, 2006

Register Today

Keynote Presentation & Technical Sessions







7:00 am - 6:00 pm


7:00 am - 8:00 am


8:00 am - 8:45 am

Keynote Presentation
Wafer Level 3D Integration: A Status Report

Philip Garrou, Research Triangle Institute & TechSearch International, Inc.

9:00 am - 5:00 pm

Exhibition & Technology Showcase

9:00 am - Noon

MEMS & Optoelectronics - Waveguides and Subassemblies
Chair: Dan Popa, University of Texas at Arlington

Flip Chip - Materials

Chair: Roupen Keusseyan, DuPont Electronics


3D Packaging - Wafer Bonding

Chair: James Jian-Qiang Lu, RPI

9:00 am

Modular Microassembly System for MEMS Packaging

Dan Popa, Manoj Mittal, Rakesh Murthy, Jeongsik Sin, Harry Stephanou, University of Texas at Arlington

Dielectric Property Measurement, RF Performance and Reliability Characterization of Underfill and Glob Top Materials for Microwave Flip-Chip Interconnects

David Ihms, David Zimmerman, Michael E. Miller, Deepukumar Nair, Matthew Walsh, Delphi

System in Package Combining Flip Chip Bonding and 3-D Stacking using a Highly Flexible Device Bonder

Gilbert Lecarpentier, SUSS MicroTec; Serguei Stoukatch, IMEC

9:30 am

Fluxless Soldering for Hermetic Packaging of MOEMS

Abiodun Fasoro, Dan O. Popa, Amit Patil, Woo Ho Lee, Jeongsik Sin, Heather Beardsley, Harry E. Stephanou, Dereje Agonafer, Automation & Robotics Research Institute

Novel Techniques for Inspection and Failure Analysis of Mounted and Underfilled Flip Chip Devices

Roger M. Devaney, HI-Rel Laboratories

A New Breed of High Volume Wafer Processing Equipment In Situ Aligned Wafer Bonding Systems for 3D Integration

Gilbert Lecarpentier, SUSS MicroTec; Klaus Ruhmer, Dan Pascual, SUSS MicroTec, Inc.

10:00 am

Advances in MEMS-Based, In-Package Fiber Aligners

Jason T. Iceman, Raymond A. Pearson, Richard P. Vinci, Svetlana Tatic-Lucic, Lehigh University

Interfacial Reaction between Sn3.0Ag0.5Cu Solder Bump Wrapped with Sn57Bi1Ag and Various Pad

Si-Suk Kim, Dong-Chun Lee, Seong-Chan Han, Heui-Seog Kim, Kwang-Su Yu, Jae-Hun Choi, Hyo-Jae Bang, Samsung Electronics

Wafer Level Temporary Bonding/Debonding for Thin Wafer Handling Applications

Koen De Munck, Lieve Bogaerts, Deniz S. Tezcan, Piet De Moor, Bart Swinnen, Kris Baert, Chris Van Hoof, IMEC

10:30 am

Break in Exhibit Hall

11:00 am

Monolithic vs. Hybrid Integration for Optoelectronic Integrated Circuits

Kenneth Pedrotti, University of California, Santa Cruz


Techniques of Collective Interconnection and Assembly of a Bolometers Focal Plane for Space Application

Jean-Louis Pornin, P. Agnese, A. Beguin, F. Simoens J.C. Cigna, A. Vandeneynde, CEA - LETI; J.Martignac, L. Rodriguez, CEA-Saclay/SAP


Evaluation of Adhesive Wafer Bonding and Processes for 3D Die Stacking using TSV Technologies

Sudhakar Kukarni, Edward Prack, Leonel Arana, Yiqun Bai, Intel Corporation

11:30 am


Ceramic Microwave/Millimeter-Wave IC Packaging

Rick Sturdivant, MPT, Inc.

Direct Wafer Bonding Technology Applied to 3D Integration on Silicon: Recent Results at LETI

L. Di Cioccio, B. Charlet, B. Biasse, M. Kostrzewa, M. Zussy, J. Dechamp, M. Migette, M. Vinet, C. Lagaye, B. Aspar, J. M. Fedeli, T. Poiroux, R. Guerrieri, R. Canegallo, N. Kernevez, CEA-Grenoble LETI

Noon - 1:00 pm

Lunch in Exhibit Hall







1:00 pm - 3:00 pm


MEMS - Assembly and Applications

Chair: Ajay Malshe, University of Arkansas

Flip Chip - Underfill & Materials

Chair: Robert L. Hubbard, Lambda Tech. Inc.


3D - Stacked Die
Chair: Markus Wimplinger, EV Group

1:00 pm

Innovative MEMS Application in High Power Circuit Breaker

Bruce C. Kim, Rahim Kasim, University of Alabama

The Optimization of Underfill Properties and Process Conditions for a Molded Flip-Chip SIP Package

Zhengjue (Jack) Zhang, Michael Buckley, Chris Perabo, Michael Todd, Henkel Technologies

Electrical Interconnects for 3D Wafer Stacks

Praveen Pandojirao-Sunkojirao, Ping Zhang, Rachita Dewan, Dan O. Popa, Harry E. Stephanou, J.-C. Chiao, The University of Texas at Arlington

1:30 pm

Evaluation of a Low-Temperature Glass Frit for Wafer-Level Packaging

Daniel N. Pascual, SUSS MicroTec

High Thermally Conductive and High Reliability Underfill

Yukinari Abe, Kazuyoshi Yamada, Osamu Suzuki, Namics Corporation

A Heterogenous System-in-Stack Technology Incorporating Area-Array Interconnects, Thermal Management and Integrated Passives

Jon Stern, Volkan Ozguz, James Yamaguchi, Irvine Sensors Corp.; Paul Franzon, Steven Lipa, Stephen Mick, North Carolina State University; Leonard Schaper, Ajay Malshe, Michael Glover, Matthew Kelley, University of Arkansas; Ari Glezer, Yogendra Joshi, Georgia Institute of Technology

2:00 pm

Advanced Photodefinable Thermosetting Fluorinated Polymer for Microelectronics Application

Takeshi Eriguchi, Masahiro Ito, Kaori Tsuruoka, Asahi Glass Co. Ltd.

Characterizing Disbond Initiation Resistance of Underfill-Polyimide Interfaces

Raymond Pearson, Brian J. McAdams, Lehigh University

Stacked Die Bond Wire Optimization in a 3D Design Environment

Gordon Jensen, CAD Design Software

2:30 pm


Low Temperature Curing of Epoxies with Microwaves

Robert L. Hubbard, Iftikhar Ahmad, Lambda Technologies, Inc.


3:00 pm

Break in Exhibit Hall

4:00 pm - 6:00 pm


Flip Chip - Materials II

Chair: Andrew Strandjord, FlipChip International LLC

Copper/Low-K - Wirebonding

Chair: George G. Harman, NIST

3D - Throughhole Metallization and Etch
Chair: Markus Wimplinger, EV Group

4:00 pm

Effect of Underfill Material Properties on Low k Dielectric, First and Second Level Interconnect Reliability

Mudasir Ahmad, Sue Teng, Jie Xue, Cisco Systems, Inc.

An Overview of the Materials and Processes Necessary to Interconnect Copper Low-k Chips

George G. Harman, NIST

Latest Developments in DRIE for Integration of Passive Components and Wafer-Level Packaging

Michel Puech, B. Andrieu, L. Popin, N. Launay, N. Arnal, P. Godinat, JM Gruffat, Alcatel Vacuum Technology

4:30 pm

Impact of Substrate Material and Solder Bump Alloys on ILD Stress in Flip Chip Packages

Brett Wilkerson, Trent Uehling, Tim Pham, Torsten Hauck, Freescale Semiconductor, Inc.

Low K Ball Grid Array 44um Pitch Wire Bonding Process Development

Tu Anh Tran, Sonder Wang, Cuckoo Du, Nick Vo, Chu-Chung (Stephen) Lee, M.C. Han, Freescale Semiconductor, Inc.

Cutting-Edge Electrodeposition Technologies for 3D Chip Integration

Bioh Kim, Jim Rychwalski, Dan Schmauch, Semitool, Inc.

5:00 pm

Assembly and Reliability of Ultrathin Flip Chips on Flexible Substrates

Barbara Pahl, Christine Kallmayer, Rolf Aschenbrenner, Herbert Reichl, Fraunhofer Institute of Reliability and Microintegration IZM

Optimization of the Wire Bonding Process on Low-k Pad Structures

Jon W. Brunner, Bob Chylak, Kulicke and Soffa Industries, Inc.

Copper Plating Techniques for Through Wafer Vias

Sergey Savastiouk, ALLVIA, Inc.; Larry Moresco, DFX Solutions, Inc.

5:30 pm

Capillary Underfill Flow Modeling and Void Mechanism for Flip Chip Packages

Sung-won Moon, Chunho Kim, Intel Corporation


Via-First Inter-Wafer Vertical Interconnects Utilizing Wafer-Bonding of Damascene-Patterned Metal/Adhesive Redistribution Layers

Jian-Qiang Lu, J. J. McMahon, R. J. Gutmann, Rensselaer Polytechnic Institute

Hotel Cut-off:

February 10, 2006

Doubletree Paradise Valley Hotel
Single/Double - $199

Reserve Rooms On-line.

Keynote Presentation & Technical Sessions







7:00 am - 5:00 pm


7:00 am - 8:00 am


8:00 am - 8:45 am

Keynote Presentation
New Developments in Flip Chip Substrates

E. Jan Vardaman, Linda Matthew, TechSearch International, Inc.

9:00 am - 11:15 am


Flip Chip - Packaging Materials

Chair: Jon Aday, Amkor Technology Inc.

Copper/Low-K - Interconnects and Processing

Chair: Jamin Ling, Kulicke and Soffa

3D - Device Applications

Chair: Leonard W. Schaper, Univ. of Arkansas / Xanodics LLC

9:00 am

Overcoming Package Stress in Flip Chips with Low Outgassed Silicone Materials

Bill Riegler, Michelle Velderrain, NuSil Technology LLC

Critical Process of Wire Bond Low-k IC Packaging

Wen-Pin Huang, Sheng-Hsiung Chen, Yu-Liang Lin, ASE

Integrated Passives: An Enabling Technology for 3-D Electronics

Leonard W. Schaper, University of Arkansas / Xanodics LLC

9:30 am

Rheology and Stability of Highly Filled Thermal Pastes

Claudius Feger, Maurice McGlashan-Powell, Ijeoma Nnebe, Dilhan Kalyon, IBM T. J. Watson Research Center

Quality and Reliability Aspects in the Singulation of Complex Wafers Containing Low-k, Copper and TEGs in the Streets

Ramon J. Albalak, Gil Shetrit, Advanced Dicing Technologies (ADT)

Chip Scale Packaging Technology for Stacked 3D Electronics

Pramod C. Karulkar, David A. Bunzow, Lawrence Bowman, Juan Goula, John Hunt, David Thomas, Jami Warrick, University of Alaska Fairbanks

10:00 am


10:15 am


Lithographic Process Characterization of a Spin-On Aqueous Developable Photosensitive Epoxy for Wafer Level Package Applications

Craig Franklin, Polymer Process Consultants; Warren W. Flack, Ha-Ai Nguyen, Ultratech, Inc.; James Grambow, Kelly J. Abreau, STEAG Hamatech USA, Inc.; Michael Toben, Masaki Kondoh, Rohm & Haas Electronic Materials

Methods of Detecting and Resolving the Weak Back-End-Of-Line (BEOL) Adhesion Interface

Chu-Chung (Stephen) Lee, Tu Anh Tran, Chuck Miller, Freescale Semiconductor, Inc.

Next Generation Low Stress Plastic Cavity Package for Sensor Applications

Michael A. Zimmerman, Quantum Leap Packaging, Inc.

10:45 am

Novel Concepts for BCB Processing

Chad Brubaker, Erik Woods, EV Group, Inc.; Mike Jennison, Agilent Technologies

Au Stud Bumping for Wafer Probe Testing

Jamin Ling, Bob Werner, Luis Morales, Kulicke & Soffa Industries, Inc.

A New High-Performance Substrate Platform using Ceramic Technology

Bill Baker, Watl Sherwood, Ed Bongio, Herb Armstrong, Larry Schmitt, Starfire Systems

11:30 am - 12:30 pm








12:45 pm - 2:45 pm


Copper/Low-K & Flip Chip - Assembly and Reliability

Chair: Beth Keser, Freescale Semiconductor

3D - Assembly and Manufacturing
Chair: Flynn Carson, STATSChiPAC Inc.

12:45 pm

Materials Effects on Reliability of FC-PBGA Packages for Cu/Low-k Chips

Li Li, Jie Xue, Mudasir Ahmad, Mark Brillhart, Paul S. Ho, Min Ding, Gary Lu, Cisco Systems, Inc.

Package on Package (PoP) - Stacking and Board Level Reliability, Results of Joint Industry Study

Lee J. Smith, Moody Dreiza, Amkor Technology, Inc.; Niranjan Vijayaragavan, Jeremy Werner, Spansion; Kevin Bagaline, Ken Nagasaka, Panasonic Factory Automation

1:15 pm

Developing a 65nm Flip Chip Test Vehicle

Tim Pham, Trent Uehling, Brett Wilkerson, Harold Downey, Pat Johnston, Burt Carpenter, Min Ding, Freescale Semiconductor

Critical Aspects of Layer Transfer and Alignment Tolerances for 3D Integration Processes

Douglas C. La Tulipe, L. Shi, A. Topol, S. Steen, D. Pfeiffer, D. Posillico, D. Neumayer, S. Goma, J. Vichiconti, J. Rubino, A. Young, M. Ieong, IBM Research

1:45 pm

Low K Flip Chip Assembly and Materials

David McCann, Amkor Technology

Evaluation of Adhesive Wafer Bonding and Processes for 3D Die Stacking using TSV Technologies

Sudhakar Kulkarni, Edward Prack, Leonel Arana, Yiqun Bai, Intel Corporation

2:15 pm

Multilevel Fracture Mechanics Modeling of Cu/Low-k BEoL Delamination in Flip Chip Packages

Charlie Jun Zhai, Paul Besser, Richard Blish, Sidharth, Raj Master, Advanced Micro Devices; Umit Ozkan, Herman Nied, Lehigh University


2:45 pm


3:00 pm - 5:00 pm


Copper/Low-K & Flip Chip - Packaging Materials

Chair: Beth Keser, Freescale Semiconductor

3D - Enabling Technologies
Chair: Flynn Carson, STATSChiPAC Inc.

3:00 pm

Underfill Evaluation for Pb-Free Flip Chip Cu/Low-K Packages

Harrison Chung, Advanced Semiconductor Engineering, Inc.

Package on Package Development and Trends

Flynn P. Carson, Young Cheol Kim, Choong Bin Yim, STATS ChipPAC Inc.

3:30 pm

Underfill Chemistry and its Compatibility with Lead Free / Low-K Flip Chip Packaging

Pukun Zhu, Pierino Zappella, Ablestik Laboratories; Marvin Cowens, Texas Instruments, Inc.

Advanced Thick Film Technology Enabling Three-Dimensional Self-Shielded Microwave Microcircuits

Lewis Dove, Agilent Technologies

4:00 pm

Effects of Packaging Materials on Cu/Low-K Dielectric through Power Cycling

Ron Zhang, Eddie Lee, Sun Microsystems


4:30 pm


5:00 pm

Closing Remarks

Register On-line

(Hotel Cut-off is February 10, 2006)
Housing Accommodations must be made directly to:

Doubletree Paradise Valley Resort
5401 North Scottsdale Road
Scottsdale, AZ 85250
Ph: 480-947-5400 or 877-445-6677

Single/Double - $199

Reserve room(s) on-line at:

Please reference IMAPS when making reservations by phone.

© Copyright 2010 IMAPS - All Rights Reserved
IMAPS-International Microelectronics And Packaging Society and The Microelectronics Foundation
611 2nd Street, N.E., Washington, D.C. 20002
Phone: 202-548-4001

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