7:00 am – 11:00 am

7:00 am – 7:30 am

3D Integration Technologies and Architectures for Portable Applications
Volkan Ozguz, Irvine Sensors Corporation

Electronic Packaging for Medical Systems
Donald Hayes, MicroFab Technologies, Inc.; Donald Hicks, University of Texas at Dallas

A High Resolution Liftoff Patterning Technique for Harsh Environment Vapor Material Deposition
Jordan Neysmith, Honggang Jiang, Second Sight Medical Products Inc.

Thermal Fatigue Properties and Grain Boundary Character Distribution of Lead-Free Sn-1.2Ag-0.5Cu Solder Interconnects on WLP
Masamoto Tanaka, Takayuki Kobayashi, Shinichi Terashima, Kohei Tatsumi, Nippon Steel Corporation

7:30 am – 8:00 am

High Performance Miniature 3D RF SiPs Combining Active Silicon with a Silicon-based Integrated Passive Device
Jean-Marc Yannou, Philippe Suchet, Stephane Bellenger, NXP Semiconductors

A Component Level Approach to Medical Device Qualification
Dave Parkin, Medtronic, Inc.

Eutectic Metallurgies for MEMS Applications
Shari Farrens, Sumant Sood, SUSS MicroTec

A Novel Re-passivation/RDL CSP Technology for Minimizing Parasitic Elements in ASIP (Application Specific Integrated Passive) Products
Phil Holland, Harry Gee, Umesh Sharma, California Micro Devices

8:00 am – 8:30 am

Flex Technology for Foldable Medical Flip Chip Devices
Barbara Pahl, Thomas Loeher, Technical University Berlin;  Hans Burkard, Josef Link, Hightec MC AG; Anders E. Petersen, Oticon A/S;  Rolf Aschenbrenner, Fraunhofer Institute for Reliability and Microintegration

Laser Tacking Ribbon Wire to Battery Case in Packaging of an Implantable Biomedical Device
Yaomin Lin, Guangqiang Jiang, Alfred E. Mann Foundation for Scientific Research

Silicon Package for MEMS and Optical Devices
Akinori Shiraishi, Shinko Electric Industries Co. Ltd.

WLCSP : Challenges, Performances and Trends
Franck Dosseul, Christophe Serre, Eric Bernier, ST Microelectronics

8:30 am – 9:00 am

Advances in Flip Chip Thermal Compression Bonding Process for SIP Device Packaging
Toru Mizuno, Philip Couts, TDK Corporation

Water Penetration Study for a Wireless 3D Electronic Patch
Jakob Janting, DELTA Danish Electronics, Light & Acoustics

Application of Advanced Photosensitive Etch Protection Coating in TMAH Silicon Wet Etching
J. Dalvi-Malhotra, X. F. Zhong, C. Planje, K. Yess, Brewer Science, Inc

Mechanical Shock Robustness of Different WLCSP Types
Mikael Johansson, Pasi Nummila, Nokia Corporation

9:00 am – 9:30 am

9:30 am – 10:00 am

Lead-free Rework of Packaged Stacked CSP Components
Satyanarayan Iyer, Gurudutt Chennagiri, SMART Modular Technologies Inc.

Effect of Temperature on Carbon Nanotube Field Effect Transistors (CNTFETs) for Bio-sensors Applications
Bashirul Polash, Hasina Huq, The University of Texas-Pan American

Second Level Interconnect Mechanical Robustness
Norman Owens, Freescale Semiconductor; E. H. Wong, R. Rajoo, S. K. W. Seah, C. S. Selvanayagam, Institute of Microelectronics; W.D. van Driel, NXP Semiconductors; J. F. J. M. Caers, X. J. Zhao, Philips Applied Technologies; L. C. Tan, M. Leoni, P. L. Eu, Freescale Semiconductor, Inc.; Y.-S. Lai, C.-L. Yeh, Central Labs, ASE, Inc.

10:00 am – 10:30 am

Wafer Level Packaging; Chip to Wafer Approach Using Flux Less Soldering and Featuring Hermetic Seal Capability
Gilbert Lecarpentier, SET (Formerly SUSS Device Bonder Division)

Miniature Chemical and Bio-molecular Sensors enabled by Direct Write Micro-dispensing Technology
David Wallace, Patrick Cooley, Donald Hayes, MicroFab Technologies, Inc.

10:30 am – 11:00 am

Equipment and Process Solutions for Chip to Wafer Stacking
Hannes Kostner, Datacon Technology GmbH

1:00 pm – 6:00 pm

1:00 pm – 1:30 pm

Development of 3D High Performance Memory
Robert Patti, Tezzaron Semiconductor

A Variant of the First Fully-Differential Capacitive Sensor for use in Scanning Probe Microscopy Applications to Nano-Fabrication
Randall Peters, Sheng-Chiang (John) Lee, Mercer University Physics Department

Determining a Robust WLCSP Mounting Process Using Six Sigma Methodology
Dennis Lang, Fairchild Semiconductor

1:30 pm – 2:00 pm

DRIE Achievements for TSV Covering Via First and Via Last Strategies
Michel Puech, Jean-Marc Thevenoud, Nicolas Launay, Matthieu Horgnies, Ketan Patel, Xavier Guichenal, Jean-Marc Gruffat, Alcatel Micro Machining Systems

A Packaging Solution to Reduce Electrical Noise in MEMS Capacitive Elements Resulting from Environmental Mechanical Vibrations
Robert Dean, Seong Kim, Chen Chen, George Flowers, A. Scott, Edward Hodel, Auburn University

Single Device Tracking – Cost Benefit Analysis
Dave Huntley, KINESYS Software

2:00 pm – 2:30 pm

High Throughput Low CoO Industrial Laser Drilling Tool
Aleksej Rodin, N.Brennan, J.Callaghan, Xsil Ltd

Reliability of MEMS Vacuum Packaging at Die or Wafer Level
Joel Collet, Stéphane Nicolas, Julien Bon, Antoine Filipe, Stéphane Renard, Tronics Microsystems

Material Properties of an Epoxy Based Wafer Applied Coating Using A Novel Curative
David Zoba, Russel Stapleton, John Hill, Lynn Yanyo, LORD Corporation

2:30 pm – 3:00 pm

Cost-Effective Cu-TSV Interconnects by EMC3D
Paul Siblerud, Semitool & EMC-3D; Thorsten Matthias, EVG; Hind Beaujon, Alcaltel; Delphine Perrottet, XSil; Jürgen Wolf, FhG; Mark Scannell, Leti

Hermetic Package Leak Testing Re-Visited
Richard Kullberg, Robert Lowry, Technical Affiliate, Oneida Research Services, Inc.

Low Expansion Substrates for Wafer Level Packaging
Greg Rudd, Kalista Kusnadi, Spectra-Mat, Inc.

3:00 pm – 3:55 pm

4:00 pm – 4:30 pm

High Rate Copper Filling Within Through Silicon Vias for 3-D Chip Stacking
Charles Sharbono, Rozalia Beica, Tom Ritzdorf, Semitool Inc.

Board Level Reliability Results for Amkor’s 12x12 I/O WLCSPnl™
Rex Anderson, Robert Moody, Boyd Rogers, Dan Mis, Amkor Technology

4:30 pm – 5:00 pm

MICROFAB DVF 200: A Fast, Robust, Electrochemical Process for Thru Silicon Vias Applications
Thomas Richardson, Christian Rietmann, Cai Wang, Pingping Ye, Chen Wang, Yun Zhang, Joe Abys, Cookson Electronics, Enthone

Influence of Different Solder Ball Alloys in Combination with Various Under Bump Metallizations on Mechanical Behaviour of WLCSP Devices
Thomas Lange, Carsten Lutterloh, Arne Kraemer, NXP Semiconductors Germany GmbH

5:00 pm – 5:30 pm

Fabrication, Assembly, and Evaluation of 10um Diameter Cu/Sn and Solder Bump Bond Arrays
Alan Huffman, Matthew Lueck, John Lannon, Dorota Temple, RTI International; Bill Sepp, Technic, Inc.

Evolution of board level reliability models for WLCSP
Luu Nguyen, National Semiconductor

5:30 pm – 6:00 pm

Lead Free Wafer Level-CSP Interconnects with Improved Mechanical Performance
Anthony Curtis, Ronnie Yazzie, Anna Hiner, Michael E. Johnson, Guy Burgess, Ted Tessier, Flip Chip International

6:00 pm – 7:00 pm

Reception In The Exhibit Hall

7:00 pm – 9:00 pm

Wafer Level Packaging Panel Discussion

WLCSP reliability has been a topic of considerable interest and discussion as the usage of this highly space efficient packaging option proliferates. We are fortunate to have some of the most prominent WLCSP technology experts in the industry participating in this conference. This panel discussion will serve as a forum for the sharing of WLCSP best known practices and reliability expectations of particular interest to DPC attendees that make, sell or use WLCSP technologies in their products.

7:00 am – 11:30 am

7:00 am – 7:30 am

Advanced Bonding Technology For Wafer-Level 3D Integration
Bioh Kim, Thorsten Matthias, Markus Wimplinger, Stefan Pargfrieder, Paul Lindner, EV Group

CoreEZ™ Package Reliability with Mixed Leaded and Lead Free Flip Chip Interconnect
Deborah Schepis, David Alcoe, Glenn Dearing, David King, Cheryl Palomaki, Endicott Interconnect

Epoxy Siloxane Polymers for Micro and Nano Fabrication Applications
Pei-I Wang, Dexian Ye, Toh-Ming Lu, Ram Ghoshal, Rajat Ghoshal, Rensselaer Polytechnic Inst.

C4NP – Solder Bumps for Flip Chip and MicroBumps for 3D
Klaus Ruhmer, SUSS MicroTec, Inc.; David Hawken, James Busby, Russell Budd, David Danovitch, IBM

7:30 am – 8:00 am

Thermal Process Induced Wafer Misalignment in 3D Integration
Sang Hwui Lee, Kuan-Neng Chen, Douglas La Tulipe, Albert Young, Jian-Qiang Lu, Rensselaer Polytechnic Inst.

Molded Flip Chip
Nokibul Islam, Miguel Jimarez,
Hansen Sy, BY Jung, JY Gim, YS Jung, SC Choi, Lito Mendoza, Amkor Technology, Inc.

Study of Laser Assisted Modifications in Liquid Crystal Polymer (LCP) for Packaging of MEMS Devices
Ajay Malshe, Ujjwala Darvemulla, University of Arkansas

Optimization of the Dry Film Lithography Process For Copper Pillar Metallization Applications
Chester Balut, Pedro Jorge, DuPont Company, Electronic Technologies

8:00 am – 8:30 am

3D Integration Technologies for Wireless Sensor Systems (e-CUBES)
Peter Ramm, Fraunhofer IZM; Maaike Taklo, Sintef; M. Jürgen Wolf, Technical University of Berlin

Flip-Chip and Column-Grid Array Packaging Technology in Extreme Environmental Conditions
Keith Sturcken, C. Hagerty, J. Hughes, BAE SYSTEMS

Microfluidic Systems in PCB Technology
Lienhard Pagel, Stefan Gassmann, University of Rostock, Germany

Process to Produce High Aspect Ratio Electroplated Copper Pillars on 300 mm Wafers
Chunwei Chen, S. Lee , B. Plass, G. Pawlowski, AZ Electronic Materials; W. Flack, A. Nguyen, Ultratech; T. Ritzdorf, D. Ericksen, Semitool

8:30 am – 9:00 am

Through Silicon Vias (TSV): Physical Design and Reliability
Sergey Savastiouk, ALLVIA, Inc.; Ephraim Suhir, UCSC

Effect of Design Factors on Micro-via Reliability of Flip Chip BGA Polymeric Substrates
Dennis Leung, Xilinx; Guna Selvaduray, San Jose State University

Packaged Multi Sensor System for Fisheries Research: New Test Methods of Package
Karen Birkelund, Anders Hyldbård, Erik Thomsen, Technical University of Denmark - Department of Micro and Nanotechnology

ENIG Versus ENEPG Under Bump Metallization for Leadfree WL-CSP Solder Bumps - a Comparison of Intermetallic Properties Using High Speed Pull Test 
Thorsten Teutsch, Axel Scheffler, Hideo Mihara, Thomas Oppert, Elke Zakel, Pac Tech USA

9:00 am – 10:00 am

10:00 am – 10:30 am

Through-Silicon Via based 3D IC Technology: Electrostatic Simulations for Design Methodology
Maxime Rousseau, Olivier Rozeau, Gérald Cibrario, Gilles Le Carval, Marie-Anne Jaud, Patrick Leduc, CEA-Léti/Minatec, CNRS-LAAS & STMicroelectronics

Studies on the Thermal Cycling Reliability of Cu Column/SnAg Double-Bump Flip Chip Assemblies on Organic Substrates for Fine Pitch Applications
Ho-Young Son, Il-Ho Kim, Jin-Hyoung Park, Soon-Bok Lee, Gi-Jo Jung, Byung-Jin Park, Kyung-Wook Paik, Korea Advanced Institute of Science and Technology (KAIST)

Polymer MEMS Accelerometer Integrated with Organic Electronics
Aditi Rane, Ramesh Ramadoss, Robert Dean, Auburn University

Understanding The Wafer Bumping Business Model: A Look at a New Approach In Bumping Interconnect and Packaging Solution
Rey Alvarado, J2 Design Services LLC

10:30 am – 11:00 am

A Unique Dry Film Photoresist System for TSV Formation and Protection
Chester Balut, DuPont Company, Electronic Technologies; Colin Tsai, DuPont Company, Taiwan

Thermal Sub-modeling of Flip Chip Ceramic Package Area Array Interconnects
Mark Eblen, Kyocera America, Inc.; Ronald Jensen, Honeywell Aerospace Electronic Systems

Polymer MEMS/PCBMEMS and Packaging for BioTag Systems in the Environment
David Fries, Stan Ivanov, Heather Broadbent, Pragnesh Bhanushali, University of South Florida, College of Marine Science

Innovative Photoresist Removal Technology for Wafer Level Packaging
Cass Shang, Mihaela Cernat, David Maloney, Anthony Rardin, DuPont EKC Technology

11:00 am – 11:30 am

High Resolution DRIE Resist for High Density Through Silicon Vias
Harris Miller, Janice Collins, MicroChem Corp.

Application and Performance of non-silicone Thermal Interface Materials
Murali Sethumadhavan, Joe Chun, Rogers Corporation

2:30 pm – 6:15 pm

2:30 pm –
3:00 pm

3D Technologies at CEA-Leti Minatec
Léa Di Cioccio, D. Henry, P. Leduc, A Mathewson, J. Brun, B. Charlet, H. Moriceau, F. Grossi, D Bordel, P. Gueguen, P. Batude, P. Coudrain, J.M. Fedeli, D. Van Thourout, C. Seassal, N. Sillon, L. Clavelier, G. Passemard, G. Poupon, M. Scannell, CEA-LETI Minatec

C4NP Technology: Present and Future
Eric Perfecto, DY Shih, Bing Dang, Kamalesh Srivastava, Luc Belanger, IBM

A Proposal of Novel Micro Opto-Electro-Mechanical Gyroscope Chip
Bo Zhang, MTE Kahn, Bohua Sun, Cape Peninsula University of Technology

Embedded Wafer Level Ball Grid Array (eWLB)
Markus Brunnbauer, Thorsten Meyer, Ralf Plieninger, Infineon Technologies AG

3:00 pm –
3:30 pm

Stacking Of Known Good Rebuilt Wafers
Christian Val, 3D Plus

Ink Jet for Flip-Chip, 3D  and Wafer-Level Packaging
Donald Hayes, David Wallace, Mike Boldman, Mike Grove, MicroFab Technologies, Inc.

Development of a MEMS-based Ka-band Phased Array for Passive Electronically Steered Beam
Tracy Hudson, Janice Rock, Michael Whitley, Andrew Jenkins, Michelle Chaffin, U. S. Army RDECOM AMRDEC

Thermal Performance Evaluation and Optimization for Redistributed Chip Package (RCP) Designs
Victor Adrian Chiriac, Beth Keser, Larry Larsen, Lakshmi N. Ramanathan, Duong Trung, Freescale Semiconductor Inc.

3:30 pm – 4:00 pm

A Novel Methodology for 3D Integration Using Multilayer Organics
George White, Sidharth Dalmia, L. Carastro, V. Sundaram, M. Swaminathan, Jacket Micro Devices

Interfacial Reactions between Sn-3.0Ag-0.5Cu Solder and Cu-Coated PCB Coatings
Minerva Cruz, Guna Selvaduray, Six Sigma

A MEMS-based Gas Sensor for the Air Quality System Monitoring the Automobile Indoor
Jung-Sik Kim, Si-Dong Kim, Jin-Ho Yoon, Bum-Joon Kim, The University of Seoul, Korea

Realization of System-in-Package Modules by Embedding of Chips
Lars Boettcher, D. Manessis, Alexander Neumann, A. Ostmann, H. Reichl, Fraunhofer IZM Berlin

4:00 pm – 4:30 pm

Laser Dicing Technology for Thin Silicon Wafers
Delphine Perrottet, Kali Dunne, Billy Diggin, XSiL

Alternative Nickel-based Surface Finishes for
IC Substrate Applications in a Pb-free Environment
Hugh Roberts, Atotech USA Inc.; Sven Lamprecht, Christian Sebald, Atotech Deutschland GmbH

High Heat Flux Micro-Channel Devices Using Liquid Metals for Laser Diode Applications
Daniel Harris, Gary Wonacoot, Robert Dean, Ashish Palkar, Auburn University

Miniaturization by Component Embedding Made Reliable and Cost Effective
Thomas Gottwald, Ulrich Ockenfuss, Schweizer Electronic AG

4:30 pm – 4:45 pm

4:45 pm – 5:15 pm

Investigating Defects in 3D Packages Using 2D and 3D X-ray Inspection
Evstatin Krastev, David Bernard, Dage Precision Industries, Inc.

Comparison of Thermal and Current Effects for Electromigration Lifetime Prediction for Sputtered Al/Ni(V)/Cu-UBM in Eutectic PbSn and Pb Free Flip Chip Solder Joints
Mark Bachman, John Osenbach, Dave Crouthamel (retired), Ron Weachock, John Delucca, Frank Baiocchi, LSI Corporation

MEMS Acoustic Sensor with Direct Spectral Output
Michael Kranz, Stanley Associates, Inc.

A Stud-in-Via Interconnection for Embedded Chip Scale Package: Application to High Speed Memory Chips
Li-Cheng Shen, EOL/ITRI

5:15 pm – 5:45 pm

IR Thermal Microscopy for 3-D Microelectronics Circuits
Tom Chung, R. Sandhu, B. Poust, G. Pilkington,  M. Parlee, A. Noori, P. Chang-Chien,  R. Tsai, A. Hirschberg, Northrop Grumman Space Technology

Fundamentals of Electromigrations in a Multiphase Material
Andre Lee, K.N. Subramanian, C.E. Ho, Michigan State University

Wafer Level Device Modification for 3D Embedded Die Applications
Ted Tessier, Anthony Curtis, Michael E. Johnson, David Lawhead, John Reche, Richard Redburn, Flip Chip International

5:45 pm – 6:15 pm

Market and Cost Analysis for 3D ICs
Eric Mounier, Jerome Baron, Yole Developpement

Advances in Flip Chip Die Sorting, Handling and Inspection
Gerald Steinwasser, Muhlbauer, Inc.

Driving Advanced Packages towards a Robust Reliable Design
Vijay Sarihan, Doug Mitchell, Beth Keser, Freescale Semiconductor

7:00 pm – 8:00 pm

3D Packaging Panel Discussion

Topics cover 3D technology platforms (SiP, PoP, Die-stack, Die-wafer, Wafer-to-wafer and Device-by-Device), unit processing technologies
and equipment/material capabilities, and future trends and technology drivers (applications and benefit).

Moderators: James J.-Q. Lu, Rensselaer Polytechnic Institute; Christo Bojkov, MAXIM
Opening Remarks: Dr. Phillip Garrou, Microelectronic Consultants of NC

7:00 am – 11:30 am

7:00 am – 7:30 am

Advanced CSP (ZyCSPTM) based on 3-D LSI Technologies for Sensor Application and Beyond
Hirofumi Nakamura,  Makoto Motoyoshi, Kazutoshi Kamibayashi, Manabu Bonkohara, ZyCube Co., Ltd.

High-Density Microvia Technology on Advanced Organic Substrate For Next Generation Flip-Chip Packaging
Venky Sundaram, Fuhan Liu, Hunter Chan, Mahadevan Iyer, Rao Tummala, Georgia Tech PRC; Hugh Roberts, Sven Lamprecht, Atotech

7:30 am – 8:00 am

3D Stacking Device Technology Using Wafer-to-Wafer Stacked Method
Nobuaki Miyakawa, Honda Research Institute Japan Co., Ltd.

Novel Electrically Conductive Adhesives for Flip Chip Assembly Interconnects
Myung Jin Yim, Yi Li, Kyung W. Paik, C. P. Wong, Intel/Numonyx

8:00 am – 8:30 am

Enabling Technologies for 3D Packaging of Optical Sensors
Juergen Leib, Michael Toepper, Fraunhofer IZM;
Keith Cooper, Dietrich Toennies, Katrin Weilermann, Shari Farrens, SUSS MicroTec

Underfill for Large Size, Low-K and Pb Free Bump Flip-Chip Package
Katsuyuki Mizuike, Tatsuya Ohori, Makoto Shinohara, Nagase ChemteX Corp.

8:30 am – 9:00 am

Integrated System Development for 3-D VLSI
Yang Liu, L. Schaper, S. Burkett, A. Kamto,
I. U. Abhulimen, L. Cai, S. Jacob, G. Jampana, University of Arkansas

The Next Generation in Substrate Technology
R. Huemoeller, Amkor Technology

9:00 am – 9:30 am

9:30 am – 10:00 am

Novel Concepts to Deliver High Yield X3D-IC Packaging Based on Wafer Scale Stacking
Sadeg Faris, Reveo, Inc.

Via Filling Applications for IC Substrate and in Particular Flip Chip BGA 
Bernd Roelfs, David Baron, Atotech Germany

10:00 am – 10:30 am

3-D Packaging and SiP Co-Design – the Business Case for Standards
Ken Ball, Knowledge Based Technical Consultancy Ltd.; Georg Meyer-Berg, Infineon; Alun Jones, TS2Micro; Wolfgang Ackrodt, Bosch Automotive; Donald Radley

Fabrication Effects on the Thermal Behavior of a Flip Chip - Low Temperature Cofired Ceramic Package
Markus Norén, C. Hoffmann, W. Salz, K. Aichholzer, EPCOS OHG

10:30 am – 11:00 am

Design, Fabrication, and Testing of GSM/EDGE Mobile Phone Module in RCP Technology
George Leal, Robert Wenzel, Trung Duong, George Leal, Marc Mangrum, Beth Keser, Doug Mitchell, Craig Amrine, Chuck Egan, Phu Tran, Freescale Semiconductor Inc.

Photoformable Thick Film Dielectric Process Optimization for Reduced Via Size
Doug Link, Starkey Laboratories, Inc.; Mike Skurski, DuPont