IMAPS - International Conference and Exhibition on Device Packaging 2010 (3D, Flip Chip, LEDs, MEMS, Passive Integration, Wafer Level Packaging)

EARLY REGISTRATION CUT-OFF: FEBRUARY 19, 2010
HOTEL DEADLINE: FEBRUARY 4, 2010

SUNDAY, MARCH 7

Global Business Council Spring Conference

12:45 pm

12:45 pm – GBC Golf Tournament
Firerock Country Club -- Fountain Hills, AZ

6:00 pm - 7:00 pm

Registration

6:00 pm

GBC Welcome Reception
(Beverages and appetizers)

MONDAY, MARCH 8

GBC Spring Conference & Device Packaging Professional Development Courses (PDCs)

7:00 am -
7:00 pm

GBC and Device Packaging Registration

7:00 am -
8:00 am

Continental Breakfast

8:00 am -
5:00 pm

GBC Spring Conference

8:00 am - Noon

Morning Professional Development Courses (PDCs)
* Click on PDC title to see full description *

PDC1 -
3D Integration: Technology, Applications & Markets for 3D Integrated Circuits
Instructor: Philip Garrou
Microelectronic Consultants of NC

PDC2 -
Area Array Microelectronics Package Reliability
Instructor: Amaneh Tasooji, Arizona State University

PDC3 –
MEMS Reliability and Packaging
Instructor: Slobodan Petrovic, Oregon Institute of Technology

PDC4 –
Addressing the Thermal Challenges in Stacked Die Packages with Advanced Thermal Interface Materials (TIMs)
Instructor: Ron Hunadi, RJ Industries, LLC CANCELLED

10:00 am - 10:20 am

Break

12:00 pm - 1:00 pm

Lunch
Only provided for those attendees registered for both Morning and Afternoon PDCs

1:00 pm - 5:00 pm

Afternoon Professional Development Courses (PDCs)
* Click on PDC title to see full description *

PDC5 –
3D Integration and Packaging Technologies, Assessment, Status and Applications
Instructor: James J.-Q. Lu
Rensselaer Polytechnic Institute

PDC6 –
Guide to Component Chip Attach - Including Flip Chip
Instructor: Phillip Creter, Creter & Associates

PDC7 –
Near Hermetic Packaging Concepts for Military and Medical Devices
Instructor: Thomas J. Green, TJ Green Associates LLC

PDC8 –
Wire Bonding in Microelectronics
Instructor: Lee Levine, Process Solutions Consulting

3:00 pm - 3 20 pm

Break

5:00 pm - 7:00 pm

Welcome Reception (All Attendees Are Invited To Attend)

Welcome Reception

Monday, March 8th
5:00 pm – 7:00 pm

All Attendees are Invited!

$100 Discount

when you register for the
Device Packaging Conference &
the Global Business Council Conference (GBC)

TUESDAY, MARCH 9

Morning Technical Sessions

7:00 am - 7:00 pm

Registration

7:00 am -
8:00 am

Continental Breakfast

8:00 am - 8:15 am

OPENING COMMENTS

8:15 am -
9:05 am

KEYNOTE – 3D Packaging
3D Interconnect: The Challenges Ahead
Brandon Prior, Senior Consultant
Prismark Partners

9:05 am -
9:55 am

KEYNOTE – MEMS
A New Wave of Innovation in Micro-Technology for Positioning, Navigation, and Timing (muPNT)
Andrei Shkel, Program Manager
Micro Technology Office (MTO), Defense Advanced Research Program Agency (DARPA)

10:00 am –
7:00 pm

Exhibition and Technology Showcase

10:00 am –
10:30 am

Break in Exhibit Hall

3D PACKAGING

MEMS

FLIP CHIP

TA1
3D Integration Technology, Cost and Applications

Chairs: James Lu, Rensselaer Polytechnic Institute; Jeff Calvert, DOW Electronic Materials

TA2
Polymer & Laminated MEMS

Chairs: Lee Levine, Process Solutions Consulting; Mathias Nowottnick: University of Rostock

TA3
Flip Chip Processes

Chairs: Lou Nicholls, Amkor Technology; Steve Adamson, Asymtek

10:30 am –
11:00 am

3D iTSV™ Integration and Cost Reduction with EMC3D
Paul Siblerud, Rozalia Beica, Bioh Kim, Erik Young, EMC-3D

Fluidic Devices in PCB Technology
Mathias Nowottnick, Lienhard Pagel, Stefan Gassmann, University of Rostock

Electrolytic Solder Deposition for Next Generation Flip Chip Solder Bumping
Stephen Kenny, Kai Matejat, Nina Dambrowski, Sven Lamprecht, ATOTECH

11:00 am –
11:30 am

The European 3D Technology Platform (e-CUBES)
Peter Ramm, Josef Weber, Thomas Fritzsch, Fraunhofer IZM-M; Maaike Taklo, Nicolas Lietaer, SINTEF ICT; Walter De Raedt, IMEC-SSET; Thierry Hilt, CEA-LETI

Implementing Fringing Field Sensors in PCB Technology
Robert Dean, Auburn University; Aditi Rane, Colin Stevens, Michael Baginski, Zane Hartzog, David Elton

No Flow Underfill Process Development for Fine Pitch Flip Chip Silicon to Silicon Wafer Level Integration
Zhaozhi Li, Auburn University; Sangil Lee, Paul N. Houston, Brian J. Lewis, Daniel F. Baldwin, Eugene A. Stout, Theodore G. Tessier, John L. Evans

11:30 am –
12:00 pm

Advances in 3D Memory and Logic Devices
Robert Patti, Tezzaron Semiconductor

PCBMEMS as a Flexible Path to Devices and Systems across Spatial Scales
David Fries, University of South Florida; Stan Ivanov, Geran Barton, Ross Willoughby, Heather Broadbent, Liesl Hotaling

Impact of Process Mechanical Simulation Methodology on Electronic Package Reliability Assessment
James Burrell, Zhongping Bao, Qualcomm Inc.

12:00 pm –
12:30 pm

Integration Aspects of the Implementation ofThrough Silicon Vias (TSV) for CMOS Image Sensors
Dave Thomas, SPP Process Technology Systems (SPTS); Jean Michailos, Nicolas Hotellier, Gilles Metellus, Francois Guyader, Alain Inard, Keith Buchanan, Dorleta Cortaberria Sanz, Yiping Song, Tony Wilby

Integration of Electroactive Polymers in MEMS Ultrasonic Sensors
Michael Kranz, Stanley Associates; Michael Whitley, Sharon Sanchez, Michael Allen

The Introduction of Tensile Ratcheting in Solder Bumps Encapsulated in Low Tg Underfill
Craig Hillman, DfR Solutions; Randy Schueller, Greg Caswell

12:30 pm – 2:00 pm

Lunch In The Exhibit Hall
(Food served from 12:30 pm – 1:30 pm)

A SPECIAL THANKS
TO THE
DEVICE PACKAGING CONFERENCE
SPEAKERS & ORGANIZERS!

YOUR COMMITMENT IS GREATLY APPRECIATED!

TUESDAY, MARCH 9

Afternoon Technical Sessions

3D PACKAGING

MEMS

WAFER LEVEL PACKAGING

TP1
3D Integration and Through-Si-Vias (TSV)

Chairs: Peter Ramm, Fraunhofer; Bob Patti, Tezzaron Semiconductor

TP2
MEMS Processing, Packaging & Analysis

Chairs: Li-Anne Liew, NIST and University Of Colorado at Boulder; Robert Dean, Auburn University

TP3
Wafer Level Materials and Process Integration

Chairs: Luu Nguyen, National Semiconductor Corporation; Andrew Strandjord, PacTech Packaging Technologies USA

2:00 pm –
2:30 pm

An Advanced Deep Silicon Etch Approach for TSV with Improved via Profile and Process Control
Brad Eaton, Applied Materials; Sharma Pamarthy, Ajay Kumar

A Robust Thin- Film Wafer-Level Packaging Approach for MEMS Devices
Krishnan Seetharaman, NXP Semiconductors; Bart van Velzen, Johannes van Wingerden, Hans van Zadelhoff, Cadmus Yuan, Frank Rietveld, Coen Tak, Peter H.C.Magnée, Herman C.W. Beijerinck

Hermetic Wafer Level Packaging of SAW Duplexer for Module Integration
Christophe Zinck, TriQuint Semiconductor; Pierre Alexandre Girard, George Grama

2:30 pm –
3:00 pm

Direct Cu Wet Seed on Barrier of TSV Wafer
Jianwen Han, Xuan Lin, Yun Zhang, Joseph Abys, Enthone; Thierry Mourier, CEA-LETI, MINATEC

Localized Parylene-C Bonding For Micro Packaging and Cell Encapsulation Using Reactive Multilayer Foils
Xiaotun Qiu, Arizona State University; David Welch, Jennifer Blain, Christen, Rui Tang, Jie Zhu, Jonathon Oiler, Cunjiang Yu, Ziyu Wang, Hongyu Yu

Enabling Thin Wafer Metal to Metal Bonding Through Integration of High Temperature Polyimide Adhesives and Effective Copper Surface Cleaners
Anthony Rardin, DuPont WLP Solutions; Mel Zussmann, Simon Kirk

3:00 pm –
3:30 pm

Advanced TSV Copper Electrodeposition for 3D Interconnect Applications
Rozalia Beica, Semitool; Paul Siblerud, Dave Erickson

Scalable Device to Wafer Level Packaging for MEMS
M. Shahriar Rahman, Murali Chitteboyina, Zeynep Çelik-Butler, Donald P. Butler, University of Texas, Arlington; Sergio Pacheco, Ronald McBean, Freescale Semiconductor

Process Control for Wet Etching for Silicon Wafer Thinning
Laura Mauer, Solid State Equipment Corporation; Herman Itzkowitz, John Taddei

3:30 pm –
4:15 pm

Break in Exhibit Hall

4:15 pm –
4:45 pm

Integration of Electrografted Layers for the Metallization of Deep TSVs
Claudio Truzzi, Alchimer; F. Raynal, V. Mevellec, N. Frederich, D. Suhr, I. Bispo, B. Couturier

Novel Polymeric Protective Coatings for Vapor HF Etching During MEMS Release
Tingji Tang, Brewer Science; Curt Planje, Xie Shao

ALX Polymer for Wafer Level Packaging: Mechanical Property Evaluation After Multiple Lead-free Solder Reflows
Takeshi Eriguchi, Asahi Glass Co.; Orson Wang, Kaori Tsuruoka, Yuichiro Ishibashi, Yong Zhang

4:45 pm –
5:15 pm

Via Last Using Polymer Liners and Their Reliability
Deniz Sabuncuoglu Tezcan, IMEC; Bivragh Majeed, Yann Civale, Philippe Soussan, Eric Beyne

Processing of Smooth Sidewalls on Lithographically Defined Apex Glass
Khalid H.M. Tantawi, University of Alabama, Huntsville; Janeszcka Oates, John Williams

ZoneBOND Thin Wafer Support Process for Temporary Wafer Bonding Applications
Jeremy McCutcheon, Brwer Science; Robert Brown, JoElle Dachsteiner

5:15 pm –
5:45 pm

Using Permanent and Temporary Polyimide Adhesives in 3D-TSV Processing To Avoid Thin Wafer Handling
Mel Zussman, DuPont Wafer Level Packaging; Chris Milasincic, Anthony Rardin, Simon Kirk

The Use of Metallographic and SEM Analysis for Characterization of Sidewall Surfaces in MEMS Devices with DRIE Processing
Lee Levine, Process Solutions Consulting; Robert Dean, Colin Stevens, Auburn University; Samuel Lawrence, Lehigh University

Thin Film Packaging Reinforcement for Overmolded MEMS
Gillot Charlotte, CEA-LETI-MINATEC; Jean-Louis Pornin, Christophe Billard, Emannuelle Lagoute, Mihel Pellat, Guy Parat, Nicolas Sillon

5:45 pm –
7:00 pm

Reception In The Exhibit Hall

7:00 pm –
8:30 pm

3D Panel Discussion: 3D Integration Technologies, Applications, and Roadmaps
Topics will cover 3D technology platforms (SiP, PoP, Die-Stack, Die-Wafer, Wafer-to-Wafer, and Device-by-Device), unit processing technologies and equipment/material capabilities, and future trends and technology drivers (applications and benefit).

Moderator: Jan Vardaman, President, TechSearch International, Inc.

Panelists:
Robert Patti, CTO, Tezzaron
Paul Sibelrud, General Manager, Wafer Level Packaging Group, Applied Materials
Matt Nowak, Director Engineering/QCT Technology, Qualcomm
Michael Wright, President and CEO, Advanced Inquiry Systems, Inc.
Ron Huemoeller, VP Advanced 3D Interconnect Technology, Amkor Technology
Phil Garrou, IMAPS Fellow, MCNC .

WEDNESDAY, MARCH 10

Morning Technical Sessions

7:00 am -
6:00 pm

Registration

7:00 am -
8:00 am

Continental Breakfast

8:00 am -
8:45 am

KEYNOTE – Emerging Technologies - LEDs
High Brightness LED Packaging: A Review of Technology and Trends
Jeff Perkins, General Manager - Business Development
Yole, Inc.

8:45 am -
9:30 am

KEYNOTE – Flip Chip
Migration to FC in the Wireless Application Space and Associated Challenges
Steve Bezuk, Director of Package Development
Qualcomm CDMA Technologies

9:30 am -
10:00 am

Break in Exhibit Hall

9:00 am -
3:00 pm

Exhibition and Technology Showcase

3D PACKAGING

MEMS

FLIP CHIP

EMERGING TECHNOLOGIES - LEDS

WA1
3D Integration Unit Processing Technology

Chairs: Paul Siblerud, SEMITOOL; Kathy Cook, Alchimer S. A

WA2
MEMS Gyroscopes & Resonant Sensors

Chairs: Tracy Hudson, U.S. Army RDEDCOM AMRDEC; Robert Dean, Auburn University

WA3
Flip Chip: Design/Reliability

Chairs: Linda Bal, Freescale Semiconductor; Lou Nicholls, Amkor Technology

WA4
LED Packaging-Materials

Chairs: Dave Saums, DS&A LLC

10:00 am – 10:30 am

3D TSV Interposer Technology with Cu/SnAg Microbump Interconnections
Seung Wook Yoon, STATS ChipPAC

A Parametrically Amplified MEMS Gyroscope
Barry Gallacher, Newcastle University; Z.X. Hu, J.S. Burdess

Chip-Package Interaction Failure Mechanisms in Flip-Chip Packages
Melida Chin, GLOBALFOUNDRIES (formerly part of Advanced Micro Devices - AMD); Amit Marathe

Thermally Conductive (TC) Plastics: a Demonstration of the Suitability of TC-Plastics as a Metal Replacement in LED Lamp Holders
R.H.C. Janssen, DSM Engineering Plastics; L. Douven, H. K. van Dijk

10:30 am – 11:00 am

TLP Bonding Technologies for Micro joining and 3D Packaging
Kei Murayama, Shinko Electric Industries Co.; Mitsuhiro Aizawa, Mitsutoshi Higashi

Vacuum Packaged High-Q MEMS Gyroscope
Alexander Trusov, University of California, Irvine; Adam Schofield

Electroplated Copper Pillar Feature Effects
Jim Zhang, NEXX Systems; Arthur Keigler, Zhen Liu, Richard Hollman

Boron Nitride in Thermoplastics
Thomas Rappelt, Momentive Performance Materials Quartz GmbH; Chandrashekar Raman

11:00 am – 11:30 am

Thin Wafer Handling and Processing for TSV Integration
Bioh Kim, EV Group; Burggraf Juergen, Burgstaller Daniel, Thorsten Matthias

Micro IMU Utilizing Folded Cube Approach
Montgomery Rivers, University of California, Irvine; Alexander Trusov, Sergei Zotov, Andrei Shkel

Flip Chip Bump Electromigration Reliability: A Comparison of Cu Pillar, High Pb, SnAg, and SnPb Bump
Ahmer Syed, Amkor Technology; CJ Berry, Karthikeyan Dhandapani, Lou Nicholls, Robert Darveaux

New Packaging Technology Through Micro Molding and LDS
Tamim Sidiki, DSM Engineering Plastics

11:30 am – 12:00 pm

Die-to-Wafer bonding of thin dies using a 2-Step approach; High Accuracy Placement, then Gang Bonding
Gilbert Lecarpentier, SET (Smart Equipment Technology); Rahul Agarwal, Wenqi. Zhang, Paresh Limaye, Riet Labie, A. Phommahaxay, P. Soussan (IMEC)

A High-sensitivity Resonant Sensor Realised Through the Exploitation of Nonlinear Dynamic Behaviour
William Waugh, Newcastle University; B.J. Gallacher

Underfill Design for Low-K Dielectrics and Lead Free Applications
Brian Schmaltz, NAMICS; Yukinari Abe

Improved Heat Dissipation and Optical Performance of High-power LED Packaging with Sintered Nanosilver Die-attach Material
Paul Panaccione, Luminus Devices; Tao Wang, Guo-Quan Lu, Virginia Tech; Xu Chen, Tianjin University; Susan Luo, NBE Technologies

12:00 pm – 12:30 pm

Journey toward Process-Flow Convergence in TSV Fabrication
Sesh Ramaswami, Applied Materials; John Dukovic

Challenges Facing Resonant MEMS Sensors
Michael Kranz, Stanley Associates

Coreless Substrate Design, Assembly and Reliability for High Speed Applications
Jon Aday, Amkor Technology; Nozad Karim, Mike Devita, Steven Lee

12:30 pm –
1:30 pm

Lunch In The Exhibit Hall

1:30 pm –
3:00 pm

Interactive Poster Session
In The Exhibit Hall: 1:30 pm – 3:00 pm
(Poster Presenter Setup - 1:00pm - 1:30 pm)

Mechanical Characterization of Polymer Passivation Layer in Semiconductor Applications Using IIT and FEA
Gyujei Lee, Hynix Semiconductor

A High Performance and Cost Effective Molded Array
Philip Rogren, EoPlex Technologies

Moisture Ingress Properties of Silicon-Laponite Encapsulants for Electrical Applications
G. Poliskie, D. Donahoe, 1000 kilometers

A Comparison of Passivation Techniques for Corrosion Protection of Metal Core Substrates
Nathan Schneck, North Dakota State University CNSE

Developing Acid Copper Plating Capability on a Novel Dielectric Material
Greg Strommen, North Dakota State University CNSE

RF and Thermal Testing of Quilt Packaging Systems
David Kopp, University of Notre Dame; M. Ashraf Khan, Jason Kulick, Alfred Kriman, Patrick Fay, Gary Bernstein

Removal of Positive Photoresist for a Lower Cost of Ownership Process
Nichelle Wheeler, Dynaloy, LLC; Jeff Griffin, Michael Phenis, Kimberly Pollard

DYCONEX Develops New Features for High-Frequency LCP Package Substrates
Marc Hauer, DYCONEX

Optimal Thermal Management of Microelectronic Packages
Victor Chiriac, Freescale Semiconductor

System Level Thermal Performance Evaluation of Inverted Exposed Pad Packages
Victor Chiriac, Freescale Semiconductor

WEDNESDAY, MARCH 10

Afternoon Technical Sessions

3D PACKAGING

MEMS

EMERGING TECHNOLOGIES - PASSIVE INTEGRATION

EMERGING TECHNOLOGIES - LEDS

WP1
3D Electrical Thermal Design and Processing Evaluation

Chairs: Rozalia Beica, Semitool; Nicolas Sillon, CEA LETI

WP2
MEMS Devices

Chairs: Thomas Baginski, Daniel Harris, Auburn University

WP3
Passive Integration

Chairs: Bob Heistand, AVX Corporation; Kai Liu, STATSChipPAC

WP4
LED Packaging-Applications

Chairs: Frank Wall, Philips Lumileds

2:30 pm –
3:00 pm

Making Precise Electrical and Thermal Models for Unlimited Combinations of 3D Chip-on-Chip/Package-on-Package Designs Compatible with Most Mainstream Analysis Tools
John Sovinsky, CAD Design Services

An Experimental Investigation in the Performance of Liquid Metal-Filled Silicon Micro-Heat Pipe Arrays
Daniel K. Harris, Auburn University; Robert Dean, Ashish Palkar, Gary Wonacott

Advanced SiP Packaging Technologies of IPD for Mobile Applications
Geun Sik Kim, STATS ChipPAC; Seung Wook Yoon, Meenakshi Padmanathan, Flynn Carson

Pumped Liquid Multiphase Cooling System for a High-Brightness LED Projector
David Saums, DS&A LLC

3:00 pm –
3:30 pm

Thermal Stress Analysis for Geometry Dependence in 3-D Packaging with Through-Silicon-Via using Finite Element Method
Sung-Hwan Hwang, Seoul National University; Byoung-Joon Kim, Sung-Yup Jung, Ho-Young Lee and Young-Chang Joo

Development of MEMS Power Sensor Package
Bruce Kim, University of Alabama; Rahim Kasim

3D Passive Integrated Capacitors Towards Even Higher Integration
Sophie Gaborieau, IPDIA; Catherine Bunel, Franck Murray

Thermal Design of the High Brightness Thin LED Backlights
D. Chestakov, Philips Research

3:30 pm –
4:00 pm

Study of Thermo-Mechanical Reliability of TSV for 8-layer Stacked Multi Chip Package
Sung-Hoon Choa, Seoul National University of Technology; Jin Young Choi, Cha Gyu Song, Haeng Soo Lee

Design of a MEMS Force Sensor for Quantitative Measurement in the Nano- to Pico-Newton Range
Li-Anne Liew, National Institute of Standards and Technology; John Moreland, Jon Pratt

High Directivity Couplers Using Multilayer Organics (MLO)
George White, AVX Corporation; Minu Valayil, Sidharth Dalmia, Charlie Russell

Thermal Dissipation-It's Not Rocket Science
Franklin Wall, Philips Lumileds Lighting Company; Sal Cassarino

4:00 pm –
4:30 pm

Break in Foyer

4:30 pm –
5:00 pm

Thermal Ridge Design for 3D Multi-core Systems with Micro-fluidic Cooling
J. H. Chien, Industrial Technology Research Institute; C. L. Lung, C. C. Hsu, Y. F. Chou, D. M. Kwai

A Micromachined Robust Planar Triggered Sparkgap Switch for High Power Pulse Applications
Thomas Baginski, Auburn University; Robert Dean, Ed Wild

Flexible On-chip Inductors and Transformer
James Wang, Power Gold

5:00 pm –
5:30 pm

Evaluation of Cu-Based Bump Bonding Processes for 3D Integration Using Fluxing No Flow Underfills
Alan Huffman, Jason Reed, Matthew Lueck, Christopher Gregory, John Lannon, Dorota Temple, RTI International

Bimorph Diaphragm Formed by Two PZT Sheets on Micromachined Silicon for Sound Generation
Youngki Choe, University of Southern California; Shih-Jui Chen, Eun Sok Kim

Matched Integrated Capacitors - An Enabling Technology for Precision Differential Capacitance Bridges
Michael Fortner

5:30 pm –
6:00 pm

Analysis of Silicon Micromachining by UV Lasers, and Implications for Full Cut Laser Dicing of Ultra-Thin Semiconductor Device Wafers
Andy Hooper, Electro-Scientific Industries; Daragh Finn

Introduce a New Structure to Sort Two Kinds of Bio-Particles Continuously Using Dielectrophoresis Method
Majid Taghavi, University of Tabriz; Mehdi Molaei

Passive Device Integration from Silicon Technology
Kai Liu, STATS ChipPAC; YongTaek Lee, HyunTai Kim, Gwang Kim, Guruprasad Badakere, Yaojian Lin, Billy Ahn

6:00 pm – 7:30 pm

Wafer Level Packaging Panel Discussion: Fan Out, WLCSP, Drop Test Standards, RDL
We are fortunate to have some of the most prominent WLP technology experts in the industry participating in this conference. This panel discussion will serve as a forum for the sharing of WLP best known practices and reliability expectations of particular interest to DPC attendees that make, sell or use WLP technologies in their products.

Moderators: Andrew Strandjord, Pac Tech USA; Ted Tessier, FlipChip International

Panelists:
Rex Anderson: WLCSP Technology Manager at Amkor, Research Triangle Park, North Carolina
Steve Bezuk: Director of Package Development at Qualcomm, San Diego, California
Andrew Strandjord: Senior Manager of Adv. Packaging at PacTech-USA, Santa Clara, California
Tom Strothmann: WLCSP Business Development Manager at STATS ChipPAC, Phoenix, Arizona
Ted Tessier: Chief Technical Officer at FlipChip International, Phoenix, Arizona

THURSDAY, MARCH 11

Technical Sessions

3D PACKAGING

FLIP CHIP

WAFER LEVEL PACKAGING

7:00 am –
11:30 am

Registration

7:00 am –
8:00 am

Continental Breakfast

THA1
3D Packaging Technology and Applications

Chairs: Flynn Carson, STATS ChipPAC; Lee Smith, Amkor Technology

THA2
Flip Chip: Alternative Flip Chip / Bumping Technologies

Chairs: Linda Bal, Freescale Semiconductor; Peter Elenius, EG Tech Partners

THA3
Wafer Level Interconnects

Chairs: Ted Tessier, FlipChip International; Christo Bojkov, Freescale Semiconductor

8:00 am –
8:30 am

Thru Mold Via (TMV™) Package on Package Development and Surface Mount Validation
Bob Bancod, Amkor Technology; Robert Lanzone, JS Kim, JH Yoon

Ultrathin 3D ACA Flip Chip-In-Flex Technology
Julian Haberland, Fraunhofer IZM; Christine Kallmayer, Rolf Aschenbrenner

Nano-Porous Gold Interconnect
Hermann Oppermann, Fraunhofer IZM; Lothar Dietrich, Matthias Klein, Bernhard Wunderle, Herbert Reichl

8:30 am –
9:00 am

Stacking of Known Good Rebuilt Wafers without TSV - Applications to memories and SiP
Christian Val, 3DPLUS; Pascal Couderc, Nadia Boulay

ENEP – A Cost-Effective Alternative for High-Reliability Soldering Applications
Gustavo Ramos, Mustafa Oezkoek, Sven Lamprecht, Atotech Deutschland GmbH; Hugh Roberts, Atotech USA

Advances in WLCSP Technologies to Enable Cost-Reduction
Rex Anderson, Amkor Technology; R. Chilukuri, B. Rogers, A. Syed

9:00 am –
9:30 am

Next Generation System in a Package Manufacturing by Embedded Chip Technologies
Lars Boettcher, Fraunhofer IZM; D. Manessis S. Karaszkiewicz , A. Ostmann, H. Reichl

Low Cost Wafer Bumping of GaAs Wafers
Andrew Strandjord, Pac Tech Packaging Technologies USA; Thorsten Teutsch, Axel Scheffler, Jing Li

Cost Modeling for Wafer Level Packaging
Chet Palesko, SavanSys Solutions LLC

9:30 am –
10:00 am

Break in Foyer

10:00 am –
10:30 am

Effect on Reliability of Bending Flexible Circuits
John Dzarnoski, Starkey Labs; Kexia Sun

Characterization of Wafer Level Metal Thermo Compression Bonding
Erkan Cakmak, EV Group; Bioh Kim, Dragoi Viorel

10:30 am –
11:00 am

Aerosol Jet Printing of High Density, 3-D Interconnects for Multi-Chip Packaging
Michael Renn, Optomec; Bruce King, Michael O’Reilly

Electromigration Performance of WLP with Polymer Core Solder Balls
Luu Nguyen, National Semiconductor Corporation; H. Nguyen, A. Prabhu

11:00 am –
11:30 am

A Review of Wafer Backside Coating Methods
Steve Adamson, Asymtek; Stephen Ruatta, Tony Winster, Raj Peddi, Jeffery Leon, Henkel

Enabling Wafer Level Processes for CIS Manufacturing
Eric Pabo, EV Group; Paul Lindner, Garrett Oakes, Ron Miller, Gerald Kreindl, Thorsten Matthias

11:30 am –
11:45 am

Closing Remarks

Conference Registration

Early Rate Ends:
February 19, 2010

Register Today

Hotel Cut-off:

February 4, 2010

Radisson Fort McDowell Resort & Casino
$149/night