IMAPS - International Conference and Exhibition on Device Packaging 2011 Program (3D, Flip Chip, LEDs, MEMS, Passive Integration, Wafer Level Packaging)

EARLY REGISTRATION/EXHIBIT CUT-OFF: FEBRUARY 3, 2011
HOTEL DEADLINE: FEBRUARY 3, 2011

SUNDAY, MARCH 6

Global Business Council Spring Conference

6:00 pm - 7:00 pm

Registration

6:00 pm - 7:30 pm

GBC Welcome Reception
(Beverages and appetizers)

MONDAY, MARCH 7

GBC Spring Conference
& Device Packaging Professional Development Courses (PDCs)

7:00 am -
7:00 pm

GBC and Device Packaging Registration

7:00 am -
8:00 am

Continental Breakfast

8:00 am -
5:00 pm

GBC Spring Conference

8:00 am - Noon

Morning Professional Development Courses (PDCs)
* Click on PDC title to see full description *

PDC1 -
3D Integration: Technology, Applications & Markets for 3D Integrated Circuits
Instructor: Philip Garrou
Microelectronic Consultants of NC

PDC2 -
Guide to Component Chip Attach - Including Flip Chip
Instructor: Phillip Creter, Creter & Associates

PDC3 –
MEMS Reliability and Packaging
Instructor: Slobodan Petrovic, Oregon Institute of Technology

PDC4 –
Fundamentals of Microelectronic Packaging
Instructor: Casey Krawiec, Consultant

10:00 am - 10:20 am

Break

12:00 pm - 1:00 pm

Lunch
Only provided for those attendees registered for both Morning and Afternoon PDCs

1:00 pm - 5:00 pm

Afternoon Professional Development Courses (PDCs)
* Click on PDC title to see full description *

PDC5 –
Introduction to MEMS Design and Fabrication
Instructor: Philip J. Reiner, CGI Federal

PDC6 –
Polymers in Semiconductor Packaging
Instructor: Jeff Gotro, InnoCentrix, LLC

PDC7 –
Hermetic Sealing and Testing of Small Volume MEMS Packages
Instructor: Thomas J. Green, TJ Green Associates LLC

PDC8 –
Area Array Microelectronics Package Reliability
Instructor: Amaneh Tasooji, Arizona State University

3:00 pm - 3 20 pm

Break

5:00 pm - 6:30 pm

Welcome Reception (All Attendees Are Invited To Attend)

7:00 pm - 10:00 pm

Microelectronics Foundation Texas Hold'Em Tournament (Separate Registration - Limited Seating)
To Benefit the IMAPS Microelectronics Foundation

Welcome Reception

Monday, March 7th
5:00 pm – 6:30 pm

All Attendees are Invited!

$100 Discount

when you register for the
"Combo Registration" with Device Packaging Conference &
the Global Business Council Conference (GBC)

TUESDAY, MARCH 8

Morning Technical Sessions

7:00 am - 7:00 pm

Registration

7:00 am -
8:00 am

Continental Breakfast

8:00 am - 8:20 am

OPENING COMMENTS

8:20 am -
9:05 am

KEYNOTE – 3D Packaging
Demand and Applications for 3D TSV
Jerome Baron, Analyst
Yole Développement, Inc.

9:10 am -
9:55 am

KEYNOTE – Flip Chip & Wafer Level Packaging
Flip Chip and Wafer Level Packaging - Past, Present and Future
Peter Elenius, Managing Partner
E&G Technology Partners LLC

10:00 am –
7:00 pm

Exhibition and Technology Showcase

10:00 am –
10:30 am

Break in Exhibit Hall

3D PACKAGING

MEMS

WAFER LEVEL PACKAGING

TA1
3D: Marketing & Products

Chairs: Ron Huemoeller, Amkor Technology, Inc.

TA2
MEMS: Laminate and Polymer MEMS

Chairs: Stefan Gassmann, University of Rostock; Robert Dean, Auburn University

TA3
Wafer Level Packaging – Process Technologies

Chairs: Lars Boettcher, Fraunhofer-IZM; Andrew Strandjord, Pac Tech USA

10:30 am –
11:00 am

3D TSV Market
TBD

High Throughput Fluidic PCBs for Medical Devices
Stefan Gassmann, Lienhard Pagel, University of Rostock

SUEX Laminates for Fan-Out and eWLB Development
Donald W. Johnson, Bin-Hong Tsai, DJ DevCorp.

11:00 am –
11:30 am

Can High Density 3D Through Silicon Stacking Replace Lithography-Driven CMOS Scaling as the Engine for the Semiconductor Industry
Matt Nowak, Qualcomm, Inc.

Flexible Metamaterials RF Filters Implemented through Micromachining LCP Substrates
Jonathan Richard, Robert Dean, Auburn University

Evaluation of Low Stress Photo-Sensitive Spin On Dielectric Layers for Through Silicon Via (TSV) Copper Redistribution Layers
Christopher Jahnes, IBM, T. J. Watson Research Center; Eric Huenger, Scott Kisting, The Dow Chemical Company

11:30 am –
12:00 pm

EMC3D Products
P. Sibelrud, Applied Materials

3D Transmission Line Design for High Power RF Components in Laminates
Sungjun Kim, Arthur Yang Zhang, Mark Bachman, G. P. Li, University of California, Irvine

300mm Wafer-Level Image Sensor Packaging
Thorsten Matthias, Bioh Kim, Gerald Mittendorfer, Paul Lindner, Moshe Kriman, Andrey Grinman, Alex Feldman, EV Group

12:00 pm –
12:30 pm

Results and Learning from 3D-IC MPW Runs
Robert Patti, Tezzaron Semiconductor Corporation

Flex PCB Based Microsystems for Mobility Applications
David Fries, Liesl Hotaling, Geran Barton, Stan Ivanov, Michelle Janowiak, Matt Smith, University of South Florida

Process and Cost Reduction Improvements in Tin Silver Electroplating of Wafers
Bob Forman, The Dow Chemical Company

12:30 pm – 2:00 pm

Lunch In The Exhibit Hall
(Food served from 12:30 pm – 1:30 pm)

A SPECIAL THANKS
TO THE
DEVICE PACKAGING CONFERENCE
SPEAKERS & ORGANIZERS!

YOUR COMMITMENT IS GREATLY APPRECIATED!

TUESDAY, MARCH 8

Afternoon Technical Sessions

3D PACKAGING

MEMS

WAFER LEVEL PACKAGING

TP1
3D: Assembly & Packaging

Chairs: Ron Huemoeller, Amkor Technology, Inc.

TP2
MEMS Fabrication and Packaging

Chairs: Philip Reiner, CGI Federal; Bruce C. Kim, University of Alabama

TP3
Embedded Die and Fan-Out Wafer Level Packaging

Chairs: Theodore Tessier, FlipChip International; Eric Huenger, Dow Chemical

2:00 pm –
2:30 pm

Logic Assy on Interposer for TSV
Mike Kelly, Amkor Technology, Inc.

Permanent Attachment of Silicon Structures via Joule Heat Induced Welding
Adam R. Schofield, System Planning Corporation; Alexander A. Trusov, University of California, Irvine; Andrei M. Shkel, DARPA

Cost Comparison of Fan-Out WLP vs. Embedded Die
Alan Palesko, SavanSys Solutions LLC; Jan Vardaman, TechSearch International, Inc.

2:30 pm –
3:00 pm

Advanced 3DIC Stacking for Memory and Mobile Applications
Dave Hiner, Amkor Technology, Inc.

Packaging Related Failure Modes of Microelectronic Components
Michael Hertl, Insidix

Realization of Power Modules by Chip Embedding Technology
Lars Boettcher, D. Manessis, S. Karaszkiewicz, A. Ostmann, Fraunhofer IZM

3:00 pm –
3:30 pm

Novel Die-to-Wafer Interconnect Process for 3D-IC Utilizing a Thermo-Decomposable Adhesive and Cu-Cu Thermo-Compression Bonding
Daniel N. Pascual, SEMATECH

Packaging Strategies for Mitigation of Mechanical Noise in Sensor Systems
Philip Reiner, Calvin W. Long, CGI Federal

300mm Large Scale eWLB(embedded Wafer Level BGA) : Cost Effective Solution with Performance
Seung Wook Yoon, Yaojian Lin, Pandi C. Marimuthu, Yeong J. Lee, STATS ChipPAC Ltd.

3:30 pm –
4:15 pm

Break in Exhibit Hall

4:15 pm –
4:45 pm

A Novel Approach to 3D Chip Stacking
Mark Vandermeulen, Andrew Smith, Ron Csermak, ON Semiconductor

Packaging of MEMS for Integrated RF Circuit Verifications
Bruce C. Kim, Sai Evana, University of Alabama; Rahim Kasim, Intel Corporation

Ultrathin WLP Die Embedded Polyimide Multi-Layer Wiring Board
Satoshi Okude, M. Okamoto, Y. Sano, N. Ueta, O. Nakao, Fujikura Limited

4:45 pm –
5:15 pm

Hetero-Structure Integration using an Atmospheric Plasma Treatment for Surface Preparation before its Interconnection
Barbara Charlet, B. Charlet, L. Di Cioccio, N. Rochat, O. Renault, L. Clavelier, C. Deguet, CEA-LETI / MINATEC

Cu MEMS
Charles Ellis, Aubrey Beal, Robert Dean, Auburn University

Impact of Process Improvements on Reliability of RCP Technology During Scale-up to Large Panel Format
George R. Leal, Scott Hayes, Dominic Koey, Tony Gong, Doug Mitchell, Gao Wei, Jason Wright, Tony Vessa, Freescale Semiconductor Inc.

5:15 pm –
5:45 pm

Commercial-off-the-Shelf 3-Dimensional Integration using Low Temperature Wafer Bonding
Sang Hwui Lee, Michael Khbeis, University of Maryland

Silica Diatom Nanopore Membranes Combined with Silicon MEMS
Michael Goryll, Xiaofeng Wang, Shankar Ramakrishnan, Kai-Chun Lin, Kaushal Rege, Sandwip Dey, B. L. Ramakrishna, Arizona State University

Stacking of Known Good Rebuilt Wafers without TSV Industrial Applications
Christian Val, Pascal Couderc, Nadia Boulay, 3D PLUS

5:45 pm –
7:00 pm

Reception In The Exhibit Hall

Sponsored by:

7:00 pm –
8:30 pm

Fan-Out and Embedded Panel Discussion

Moderators: Andrew Strandjord, Pac Tech USA; Linda Bal, Freescale Semiconductor

Please join us for an interactive panel discussion on Fan-Out and Embedded Technologies. An executive panel has been assembled from several of the leading microelectronics companies and institutes from around the world to discuss the latest Technologies, Market Tends, and Infrastructure. The panel will be soliciting questions from the audience.

Images Courtesy of: Stats ChipPAC, IZM, Freescale, ASE, & Infineon

Panelists:

Tom Strothmann, Director of Business Development, STATS ChipPAC, Ltd.

Lars Boettcher, Embedded Die Manager, Fraunhofer IZM

Navjot Chhabra, Director of Advance Packaging, Freescale Semiconductor

John Hunt, Director of Engineering, ASE, Inc.

Thorsten Meyer, eWLB Project Manager, Infineon Technologies AG

WEDNESDAY, MARCH 9

Morning Technical Sessions

7:00 am -
6:00 pm

Registration

7:00 am -
8:00 am

Continental Breakfast

8:00 am -
8:45 am

KEYNOTE – MEMS
Advanced Packaging for Multi-Axis Resonant MEMS Gyroscopes
Dr. Farrokh Ayazi, Professor & Co-Director
Georgia Institute of Technology

8:45 am -
9:30 am

KEYNOTE – Passives
RF System-in-Packages: History and Trend
Kai Liu, Senior Engineering Manager
STATS ChipPAC Ltd.

9:30 am -
10:00 am

Break in Foyer

3D PACKAGING

MEMS

EMERGING TECHNOLOGIES - LEDS

WA1
3D: Materials & Processing

Chairs: Paul Siblerud, EMC3D

WA2
MEMS Gyroscope Devices & Systems

Chairs: Barry J. Gallacher, Newcastle University; A. A. Trusov, University of California, Irvine

WA3
LED Packaging

Chair: Jeff Perkins, Yole, Inc.

10:00 am – 10:30 am

Aerosol Jet® Printer as an Alternative to Wire Bond and TSV Technology for 3D Interconnect Applications
Michael O'Reilly, Michael J. Renn, Stephen Barnes, Optomec, Inc.

Fundamentals of a MEMS Rate Integrating Gyroscope that Exploits Wave Inertia
Barry J. Gallacher, Newcastle University

Silicon-Based Wafer-Level Packaging for Cost Reduction of High Brightness LEDs
Thomas Uhrmann, B. Kim, T. Matthias, P. Lindner, EV Group

10:30 am – 11:00 am

Cost Effective Production of Glass Interposers for 3D ICs Using APEX™ Glass Ceramic
Jeb H. Flemming, Kevin Dunn, James Gouker, Carrie Schmidt, Life MicroFab

Temperature and Humidity Effects on MEMS Vibratory Gyroscope
Chandradip Patel, F. Patrick McCluskey, David Lemus, University of Maryland

Advanced Laser Scribing for Emerging LED Materials
Marco Mendes, Jeffrey Sercel, Mathew Hannon, Cristian Porneala, Xiangyang Song, Jie Fu, Rouzbeh Sarrafi, JP Sercel Associates, Inc. (JPSA)

11:00 am – 11:30 am

3D-IC Integration Using C2C or C2W Alignment Schemes Together with Local Oxide Reduction
Gilbert Lecarpentier, Jean-Stephane Mottet, Keith Cooper, Michael Stead, SET - Smart Equipment Technology

Towards a Parametrically Pumped Xylophone Microbar Magnetometer: Design Optimisation of Xylophone Bar Resonators
Harry T.D. Grigg, Newcastle University

Packaging of High Brightness LED's
Lidia Lee, Paul Panaccione, Luminus Devices, Inc.

11:30 am – 12:00 pm

Cu-Cu Thermocompression Bonding using Ultra Precision Cutting of Cu Bumps for 3D-SIC
Taiji Sakai, Akamatsu Toshiya, Nobuhiro Imaizumi, Miyajima Toyoo, Masataka Mizukoshi, Fujitsu Laboratories Ltd.

Design and Packaging of Ultra-High Q-Factor MEMS for Inertial Applications
A. A. Trusov, I. P. Prikhodko, S. A. Zotov, University of California, Irvine; A. M. Shkel, DARPA

Packaging HB LEDs with Integrated Beamshaping
Michael Schilling, Plan Optik AG

12:00 pm -
4:30 pm

Exhibition and Technology Showcase

12:00 pm –
1:00 pm

Lunch In The Exhibit Hall

1:30 pm –
4:30 pm

Interactive Poster Session
In The Exhibit Hall: 1:30 pm – 4:30 pm
(Poster Presenter Setup - 1:00 pm - 1:30 pm)

High Temperature Gold Based Lead Free Solder
Heiner Lichtenberger, Williams Advanced Materials

Advances in Carrier Technologies for WLP and TSV Stacking
Bioh Kim, Garrett Oakes, Burggraf Jurgen, Burgstaller Daniel, Thorsten Matthias, EV Group

Integrated Design and Full-Wave Analysis of Mixed Signal 3D Package Designs
Antonio Ciccomancini Scogna, Taranjit Kukal, Cadence Design Systems, CST

Towards Making 3D Submicron Interconnects by Motion Controlled Direct-Writing of Metal Wires
Min-Feng Yu, Jie Hu, University of Illinois at Urbana-Champaign

Reliability Challenges with Leadless Near Chip Scale Packages
Cheryl Tulkoff, DfR Solutions

Effect of Abnormal Intermetallic Compounds Growth of Component Side on Board Level Mechanical Reliability
Jae-Hoon Choi, Jeong-Sam Lee, Hui-Soek Kim, Samsung Electronics

New Cleaning Technology Solutions for Lead-Free Micro-Bumping Processes
Kimberly D. Pollard, Nichelle Wheeler, Allison Rector, Dynaloy LLC

Anisotropic Conductive Adhesive for Wafer-to-Wafer Bonding
M.M.V. Taklo, T. Bakke, H.R. Tofteberg, L.G.W. Tvedt, H. Kristiansen, SINTEF IKT

Low-Cost and High Throughput PR Stripping Solutions for Bumping Processes
John Moore, Jared Petit, Alex Brewer, Daetec, LLC; Neil Yoshizawa, Walter Albers, CBC (America)

Vertical LED with Diamond-Like Carbon (DLC) Interface for High-Power Illumination
Michael Sung, Chien-Min Sung, Kevin Kan, SinoDiamond LED

High Power Module Packaging Design for Harsh Environments
Andreas Larsson, O. Storstrom Barros, T.A.T. Seip, M.M.V. Taklo, T. Fallet, SINTEF ICT

IC Packaging Trends Causing Concern in Complete Removal of Solder Flux
Rich Brooks, Mike Bixenman, Kyzen Corporation

WEDNESDAY, MARCH 9

Afternoon Technical Sessions

3D PACKAGING

MEMS

FLIP CHIP

EMERGING TECHNOLOGIES - PASSIVE INTEGRATION

WP1
3D - Materials & Processing…cont.

Chairs: Rozalia Beica, Applied Materials

WP2
MEMS Sensors and Actuators

Chairs: Tom Baginski, Auburn University; Michael Kranz, Stanley Associates

WP3
Flip Chip

Chairs: Alan Huffman, RTI International; Linda Bal, Freescale Semiconductor

WP4
Passive Integration

Chairs: Bob Heistand, AVX Corporation; Franck Murray, IPDIA

2:00 pm –
2:30 pm

Through-Sapphire Via Development
Syed Sajid Ahmad, Frederik Haring, Justin Vignes, Kaycie Gestner, Aaron Reinholz, North Dakota State University

A New Robust One-Shot Switch for High-Power Pulse Applications
Thomas A. Baginski, Robert N. Dean, Steven P. Surgnier, Auburn University

Flip-Chip Technology: Technologies, Market Trends and Supply Chain
Christophe Zinck, Jean-Marc Yannou, Jérôme Baron and Phil Garou, Yole Développement

Low Profile 3D-IPD for Advanced Wafer Level Packaging
Catherine Bunel, Stephane Bellenger, Sebastien Leruez, Lionel Lenoir, Franck Murray, IPDIA

2:30 pm –
3:00 pm

Laser Technology for Through-Silicon Via and Microvia Drilling in Silicon for 3D Packaging Applications
Andy Hooper, Daragh Finn, Shane Noel, Gregg Anderson, Jim O'Brien, Chi-Cheng Lin, Electro-Scientific Industries

Miniature MEMS Interface Circuits Using Nanoparticle Conductors and Embedded Components
C. Paul Christensen, Potomac MesoSystems

Flip Chip Fine Pitch PBGA Yield Study
Tim Pham, Betty Yeung, Trent Uehling, Brett Wilkerson, Freescale Semiconductor Inc.

Laser Processing of 2-D and 3-D Structures for Tunable Embedded Capacitors
Rabindra N. Das, Timothy E. Antesberger, Francesco Marconi, Frank D. Egitto, Mark D. Poliks, Voya R. Markovich, Endicott Interconnect Technologies, Inc.

3:00 pm –
3:30 pm

Novel Wet Chemical Copper Metallization for Glass Interposers
Simon Bamberg, Ralf Bruening, Johannes Etzkorn, Frank Bruening, ATOTECH Deutschland GmbH

Ultra High Temperature Sensor RFIDS
Yang Zhang, Mark Bachman, G. P. Li, University of California - Irvine

3D X-Ray CT Analysis of Solder Joints in Area Array Electronic Package Assemblies
Rajen Chanchani, Sandia National Laboratories

RF System in Packages (SiP) using Integrated Passive Devices
Kai Liu, YongTaek Lee, HyunTai Kim, Gwang Kim, Billy Ahn, STATS ChipPAC, Ltd.

3:30 pm –
4:30 pm

Break in Foyer

4:30 pm –
5:00 pm

Evaluation of Electrodeposited Photoresists for use in the Fabrication of an Optochip Silicon Interposer
Cornelia Tsang, Janet Okada, Eric Huenger, IBM, T. J. Watson Research Center

Electro-Magnetically Actuated Frequency Addressable Switch
Minfeng Wang, Yang Zhang, G. P. Li, Mark Bachman, University of California - Irvine

Effects of Under-Fill Curing on Flip-Chip Substrate Warpage
Robert L. Hubbard, Lambda Technologies Inc.

High-Frequency On-Chip Inductors with Patterned CoZrTa Films
Hao Wu, Wei Xu, Donald S. Gardner, Saurabh Sinha, Tawab Dastagir, Bertan Bakkaloglu, Yu Cao, Hongbin Yu, Arizona State University

5:00 pm –
5:30 pm

TSV Resist and Residue Removal
Laura Mauer, John Taddei, Ramey Youssef, Solid State Equipment Corporation; Kimberly Pollard, Allison Rector, Dynaloy

In-Situ Wafer-Level Polarization of Electret Films in MEMS Acoustic Sensor Arrays
Michael Kranz, Mark Allen, Stanley Associates; Tracy Hudson, U.S. Army RDECOM AMRDEC

Z-Axis Interconnection in Organic Packaging
Frank Egitto, T. Antesberger, R. Das, V. Markovich, S. Rosser, M. Schadt, W. Wilson, Endicott Interconnect Technologies

Silicon Interposers Enable High Performance Capacitors
Sergey Savastiouk, Phil Marcoux, Jim Hewlett, ALLVIA

5:30 pm –
6:00 pm

Formulation of Percolating Thermal Underfill by Sequential Convective Gap Filling
T. Brunschwiler, J. Goicochea, H. Wolf, C. Kuemin, B. Michel, IBM Research GmbH

A 0.18um CMOS Analog Front-End IC for Gas Sensors
Hyuntae Kim, Bertan Bakkaloglu, Arizona State University

Flip Chip for Image Sensor Packaging
Deok-Hoon Kim, Young-Sang Cho, OptoPAC; Peter Elenius, E&G Technology Partners

Manufacturing Substrates with Embedded Passives
Rabindra N. Das, Konstantinos I. Papathomas, John M. Lauffer, Mark D. Poliks, Voya R. Markovich, Endicott Interconnect Technologies, Inc.

6:00 pm – 7:30 pm

3D Panel Discussion: Memory Cube Readiness, Use and Logistical Challenges
Topics will cover the use of the Memory Cube in new products/applications, its readiness in the industry in general and all the associated challenges with ownership of the logistical flow.

Moderator: Matt Nowak, Qualcomm, Inc.

Panelists:
Ron Huemoeller, Amkor Technology, Inc.
Bryan Black, Fellow, AMD
Dr. Philip. Garrou, IEEE Fellow, Yole Developpment
Eric Strid, Cascade Microtech, Inc.

THURSDAY, MARCH 10

Technical Sessions

3D PACKAGING

WAFER LEVEL PACKAGING

FLIP CHIP

7:00 am –
11:30 am

Registration

7:00 am –
8:00 am

Continental Breakfast

THA1
3D - Design, Thermal & Metrology

Chairs: Ahmer Syed, Amkor Technology, Inc.

THA2
Wafer Level Packaging - Applications

Chairs: Rey Alvarado, Maxim Integrated Products; In Soo Kang, NEPES

THA3
Flip Chip: Cu Pillar and Solder Bumps

Chairs: Peter Elenius, E&G Technology Partners LLC; Steve Adamson, Asymtek

8:00 am –
8:30 am

Failure Analysis and Reliability of 3D Integrated System
Peter Ramm, Armin Klumpp, Fraunhofer EMFT; German Franz, Laurens Kwakman, FEI Electron Optics

3D SiP(System in Package) Solutions with Wafer Level Package Technology
In Soo Kang, Jong Heon (Jay) Kim, NEPES

Cu Pillar Bumping Technology with Solder Alloy Versatility
Guy Burgess, Anthony Curtis, Tom Nilsson, Gene Stout, Theodore G. Tessier, FlipChip International

8:30 am –
9:00 am

3D Coaxial Through-Strata-Via (TSV) Evaluation and Modeling
Zheng Xu, James Jian-Qiang Lu, Rensselaer Polytechnic Institute

300mm Scaling of Critical Silicon Etches for Image Sensor Wafer-Level Packaging Based on Tessera’s MVP (TSV) Technology
Dave Thomas, Matthew Muggeridge, Mike Steel, Dorleta Cortaberria Sanz, Hefin Griffiths, Oliver Ansell, SPP Process Technology Systems Ltd.; Moshe Kriman, Andrey Grinman, Hagit Gershtenman-Avsian, Tessera Technologies Inc.

fcCSP with Cu Pillar is Ready for Prime Time
Bernd K Appelt, Harrison Chung, Raymond Wang, ASE Group

9:00 am –
9:30 am

Thermal Analysis for a Novel 3D Heterogenous Integrated Platform MorPack
Shih-Lun Chen, Chun-Ming Huang, Chien-Ming Wu, Chih-Chyau Yang, Jin-Ju Chue, Shih-Lun Chen, Chi-Shi Chen, Jiann-Jenn Wang, Tzi-Dar Chiueh, National Chip Implementation Center (CIC)

Processing and Reliability Assessment of Silicon Based, Integrated Ultra High Density Substrates
Brian J. Lewis, D. F. Baldwin, P. N. Houston, Engent Inc.; B. Smith, P. Kwok, J. Thompson. A. Mueller, L. Racz, Draper Laboratory

Electromigration Reliability of Cu Pillar on Substrate Interconnects in High Performance Flip Chip Packages
Rajesh Katkar, Michael Huynh, Laura Mirkarimi, Tessera Inc.

9:30 am –
10:00 am

Break in Foyer

10:00 am –
10:30 am

Through Package Defect Localization by Lock-In Thermography
Rudolf Schlangen, Herve Deslandes, DCG Systems, Inc.; Toru Toda, Toshinobu Nagatomo, DCG Systems, KK; Shigeki Sako, J-Device Co., Ltd; Hiromichi Sawaya, Toshiba Semiconductor

Wafer Level Package for MEMS with TSVs and Hermetic Seal
Akinori Shiraishi, Mitsutoshi Higashi, Kei Murayama, Yuichi Taguchi, Kenichi Mori, Shinko Electric Industries Co., Ltd.

Electrolytic Solder Deposition for IC-Substrates: From Deposition Uniformity to Solder Ball Geometry
Bernd Roelfs, Kai Matejat, Atotech Germany

10:30 am –
11:00 am

2D/3D Inspection of mBumps & mPillars
Hubert Altendorfer, KLA - Tencor

Strategies for WLCSP Board Level Reliability Enhancement
Tony Curtis, Senthil Sivaswamy, Ronnie Yazzie, David Lawhead, Theodore G. Tessier, FlipChip International

Copper Migration in Flip-Chip Substrates Under Biased-HAST Conditions
Matthew E. Stahley, John W. Osenbach, LSI Corporation

11:00 am –
11:30 am

3D-TSV Test Options and Process Compatibility
Ken Smith, Peter Hanaway, Mike Jolley, Reed Gleason, Eric Strid, Cascade Microtech, Inc.

Electromigration in Solder Joints for High Temperature Flip-Chip Application
Mathias Nowottnick, Andreas Fix, University of Rostock

11:30 am –
11:45 am

Closing Remarks

1:00 pm Start

2011 IMAPS Microelectronics Foundation Spring Golf Invitational
1:00pm Shotgun Start – “Best Ball” Scramble
Desert Canyon Golf Club
10440 Indian Wells Drive
Fountain Hills, AZ

Conference Registration

Early Rate Ends:
February 3, 2011

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