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9th International Conference and Exhibition on
Device Packaging

www.imaps.org/devicepackaging

Radisson Fort McDowell Resort and Casino
Scottsdale/Fountain Hills, Arizona USA



Conference and Technical Workshops
March 12-14, 2013
Exhibition and Technology Showcase
March 12-13, 2013
Professional Development Courses
March 11, 2013
GBC Spring Conference
March 10-11, 2013

In conjunction with the Global Business Council (GBC) Spring Conference, March 10-11


Courtesy of Rensselaer Polytechnic Institute

Courtesy of US Army RDEDCOM AMRDEC


General Chair:

James Lu
Rensselaer Polytechnic Institute

General Chair-elect (PDCs):
Ron Huemoeller
Amkor Technology
Past General Chair (Panels):
Peter Elenius
E&G Technology Partners

3D & 2.5D Packaging
Topical Workshop
Flip Chip & Wafer Level Packaging
Topical Workshop
MEMS & Microsystems
Topical Workshop
LED Packaging for SSL
Topical Workshop
Technical Chair:
Rozalia Beica
Lam Research AG
Technical Chair:
Linda Bal
Freescale Semiconductor
Technical Chair:
Tracy Hudson
US Army
Technical Chair:
Thomas Goodman
E&G Technology Partners
Technical Co-Chair:
Peter Ramm
Fraunhofer EMFT
Technical Co-Chair:
Luu Nguyen
Texas Instruments
Technical Co-Chair:
Russell Shumway
Amkor Technology
Technical Co-Chair:
Bob Karlicek
Rensselaer Polytechnic Institute


Early Registration & Hotel Deadlines: February 8, 2013



Technical Program | Download Program PDF | Speaker Info | Professional Development Courses (PDCs)
Exhibition Details | Floorplan | 2013 Exhibitors | 2012 Exhibitors
Global Business Council (GBC) Spring Conference
Spring Golf Invitational | Texas Hold'em Tournament


Technical Program

SUNDAY, MARCH 10

5:30 pm - 7:30 pm

Registration

5:30 pm - 7:30 pm

GBC Welcome Reception
(Beverages and appetizers)

Thank you to the GBC Reception Sponsors:
DPC/GBC Premier Sponsor: Solid State Equipment Corp. DPC/GBC Premier Sponsor: Amkor Technology DPC/GBC Premier Sponsor: ASE US, Inc.

 

7:30 pm - 9:00 pm

GBC Speaker Dinner
(By Invitation Only)

Thank you to the GBC Speaker Dinner Sponsors:
GBC Speaker Dinner Sponsor: Solid State Equipment Corp. GBC Speaker Dinner Sponsor: Amkor Technology GBC Speaker Dinner Sponsor: ASE US, Inc. GBC Speaker Dinner Sponsor: Kyocera America

MONDAY, MARCH 11

7:00 am -
7:00 pm

GBC and Device Packaging Registration

7:00 am -
8:00 am

Continental Breakfast

8:00 am -
5:00 pm

8:00 am - Noon

Morning Professional Development Courses (PDCs)
* Click on PDC title to see full description *

PDC1: 2.5D/3D, Flip Chip WLP, MEMS & LED Packaging Trends, Updates & Advances
Course Leader: Phil Creter, Creter & Associates
PDC2: Recent Advances in Glass and Silicon Interposers for 2.5D and 3D Integration
Course Leader: Venky Sundaram, Georgia Institute of Technology (PRC)
PDC3: High-Temperature Electronics - with an Emphasis on Assembly & Packaging
Course has been cancelled
PDC4: Hermetic Sealing and Testing of Small Volume MEMS Packages
Course Leader: Thomas J. Green, TJ Green Associates LLC
PDC5: Failure Mode Analysis of Flip Chip and Advanced Package and Board Assemblies
Course Leader: Daniel Baldwin, Engent Inc.

10:00 am - 10:20 am

Break

12:00 pm - 1:00 pm

Lunch
Only provided for those attendees registered for both Morning and Afternoon PDCs

1:00 pm - 5:00 pm

Afternoon Professional Development Courses (PDCs)
* Click on PDC title to see full description *

PDC6: Fundamentals of Glass Technology and Applications for Advanced Semiconductor Packaging
Course Leaders: TJ Kiczenski, Aric Shorey, Corning, Inc.
PDC7: Polymers in Semiconductor Packaging
Course Leader: Jeffrey Gotro, InnoCentrix, LLC
PDC8: Thermal and Mechanical Simulation Techniques - An Introductory Course for 3D Enablement Professionals
Course Leader: Kamal Karimanal, Cielution LLC
PDC9: MEMS Reliability and Packaging
Course Leader: Slobodan Petrovic, Oregon Institute of Technology
PDC10: Basics of Conventional and Advanced Packaging
Course Leader: Syed Sajid Ahmad, NDSU - CNSE

3:00 pm - 3 20 pm

Break

5:15 pm - 6:45 pm

Welcome Reception (All Attendees Are Invited To Attend)

Thank you to the Device Packaging Reception Sponsors:
DPC/GBC Premier Sponsor: Solid State Equipment Corp. DPC/GBC Premier Sponsor: Amkor Technology DPC/GBC Premier Sponsor: ASE US, Inc.

7:00 pm - 10:00 pm

Microelectronics Foundation Texas Hold'Em Tournament (Separate Registration - Limited Seating)
To Benefit the IMAPS Microelectronics Foundation


Welcome Reception

Monday, March 11th
5:15 pm – 6:45 pm

All Attendees are Invited!


$100 Discount

when you register for the
"COMBO" Registration with Device Packaging Conference &
the Global Business Council Conference (GBC)

DPC Sponsor: SANTIER

 

TUESDAY, MARCH 12   
Morning Technical Sessions

7:00 am -
6:00 pm

Registration

7:00 am -
8:00 am

Continental Breakfast

Sponsored by:
Breakfast Sponsor: ASE US, Inc.

8:00 am -
8:20 am

OPENING COMMENTS
General Chair: James Lu, Rensselaer Polytechnic Institute

8:20 am -
9:05 am

KEYNOTE – 3D Packaging
2.5 and 3D - Scaling Walls
Dr. Sitaram R. Arkalgud, Vice President of 3D Technology
INVENSAS CORPORATION

Abstract: Stacking chips, either on a 2.5D interposer or in true 3D ICs, is an industry game changer since it promises the benefits of higher performance, functionality and density at lower power consumption. With advent of the first 2.5D products in volume production, the need to reduce cost, particularly for consumer applications, is gaining prominence. Lithographic scaling has driven performance and cost vectors in the semiconductor industry for decades. Comprehensive models, developed to understand the impact of scaling on device performance, reliability and cost, make it easier to develop scaling roadmaps. In a similar fashion, credible models for 3D interconnects are critical, since these will underpin the development of future 3D technology "nodes" by providing performance and cost estimates. The roadmaps, in turn, will drive the development of materials, equipment, EDA tools and products. This presentation will examine some of the near term manufacturability concerns as well as key areas for 3D scaling, together with the electrical and thermo-mechanical challenges that accompany them.

Dr. Sitaram R. Arkalgud is Vice President of 3D Technology at Invensas Corporation, a complete Interconnectology solutions provider for advanced mobile applications. Previously, Arkalgud started and led 3D IC development at SEMATECH, where the focus was on delivering manufacturable process technologies for 3D interconnects. In addition, he has worked in a variety of roles spanning R&D and manufacturing in memory and logic technologies at Infineon/Qimonda and Motorola. Arkalgud holds a doctorate and master's degree in materials engineering from Rensselaer Polytechnic Institute in Troy, NY, and a bachelor's degree in metallurgical engineering from Karnataka Regional Engineering College, Suratkal, India. He is the author of several publications and holds 14 U.S. patents.

9:10 am -
9:55 am

KEYNOTE – Flip Chip & Wafer Level Packaging
Semiconductor Packaging Trends and Materials Challenges
Dr. Mahadevan "Devan" Iyer, Director of Worldwide Semiconductor Packaging operations
TEXAS INSTRUMENTS

Abstract: Semiconductor advancements continue to enable many new applications to enable the Internet of Things, and transform areas such as cloud computing, health care, safety and security, and consumer electronics. As exciting new capabilities emerge, customers are demanding smaller, thinner, faster and more power efficient solutions. In his keynote presentation, Dr. Mahadevan "Devan" Iyer will discuss these trends, and how packaging technology is playing an increasingly important role in delivering these benefits in IC products. Dr. Iyer will outline the materials requirements and challenges for increased electrical, thermal and reliability performance.

As Director of TI's Worldwide Semiconductor Packaging operations, Dr. Mahadevan "Devan" Iyer, oversees a global team that drives a process to determine the packaging design and technologies that best meet the requirements of our customers in measures of miniaturization, performance cycle time, and cost. Dr. Iyer joined TI in 2008 to lead the global SC Packaging team. He has more than 25 years of experience in the microelectronics industry. Dr. Iyer is a recognized authority in semiconductor packaging technologies. He has more than 150 technical publications and 28 patents to his credit.

10:00 am -
10:30 am

Break in Exhibit Hall

Sponsored by:
STATSChipPAC - Coffee Break Sponsor Applied Materials - Coffee Break Sponsor SETNA Corporation - Coffee Break Sponsor

DPC Sponsor: Applied Materials

10:00 am -
7:00 pm

Exhibition and Technology Showcase

 
Advanced 3D Packaging
Flip Chip & Wafer Level Packaging
MEMS & Microsystems

 

TA1
3D Packaging Applications

Chairs: Peter Ramm, Fraunhofer EMFT; Franck Murray, IPDIA

TA2
Flip Chip & Cu Pillar Assembly Reliability

Chairs: Richard McKee, Pac Tech-USA; Alan Huffman, RTI International

TA3
MEMS Devices and Processes

Chairs: Robert Dean, Auburn University; Philip Reiner, CGI Federal Systems

10:30 am – 11:00 am

Cost Drivers for 2.5D and 3D Applications
Chet Palesko, SavanSys Solutions LLC (E. Jan Vardaman TechSearch International, Inc.; Alan Palesko, SavanSys Solutions LLC)

Reliability of Die to Wafer Bonding Using Copper-Tin Interconnections
Arnaud Garnier, CEA-LETI, MINATEC (Remi Franiatte David Bouchu, Romain Anciant, Severine Cheramy)

MEMS Parallel Plate Actuator Pull-in Detection and Mitigation
Colin Stevens, Auburn University (Robert Dean)

11:00 am – 11:30 am

Stacked 3d Package with Improved Bandwidth and Power Efficiency
Dev Gupta, APSTL LLC

Thermal Modeling Approach for Enhancing TCNCP Process for Manufacturing Fine Pitch Copper Pillar Flip Chip Packages
Siddharth Bhopte, Amkor Technology (Jesse Galloway, Kyung-Rok Park, Hyun-Jin Park, Jeong-Han Choi, Ho-Beob Yu, Sung-Hwan Yang)

Design, Simulation and Testing of High Density, High Current Micro-machined Embedded Capacitors
Aubrey Beal, Auburn University (C. Stevens, T. Baginski, M. Hamilton, R. Dean)

11:30 am – 12:00 pm

ChipsetT: Embedded Die Substrate Applications
Jon Aday, FlipChip International, LLC (Ted Tessier, FlipChip International; Kazuhisa Itoi, Satoshi Okude, Fujikura Ltd.)

Groove Geometry and Mold Shrinkage Effects on Die Stress in Flip Chip Molded BGAs (FCMBGA)
Bora Baloglu, Amkor Technology (Corey Reichman, Miguel Jimarez Ahmer Syed)

Sealing Dispensing Requirements to Meet MEMS Packaging and Throughput Impact
Heakyoung Park, Nordson ASYMTEK

12:00 pm – 12:30 pm

Lithography Challenges for TSV and 2.5D Applications
Doug Shelton, Canon U.S.A., Inc

Spheron Fan-In WLCSP Technology Qualification and Scale Up – 200mm to 300mm
Andre Cardoso, Nanium S.A (Rui Almeida, Felandorio Fernandes; Ted Tessier, Anthony Curtis, FlipChip International)

Assembly Standardization for the Diverse Packaging Requirements of MEMS & Sensors
Russell Shumway, Amkor Technology

12:30 pm –
2:00 pm

Lunch In The Exhibit Hall
(Food served from 12:30 pm - 1:30 pm)

Sponsored by:
DPC/GBC Premier Sponsor: Solid State Equipment Corp. Applied Materials - Event Sponsor

DYCONEX

TUESDAY, MARCH 12   
Afternoon Technical Sessions
 
Advanced 3D Packaging
Flip Chip & Wafer Level Packaging
MEMS & Microsystems

 

TP1
2.5D Interposer Packages

Chairs: Cristina Chu, TEL NEXX; Alan Huffman, RTI International

TP2
Topics in Bump and Die Interconnect

Chairs: Gilles Poupon, LETI; Luu Nguyen, Texas Instruments

TP3
MEMS Packaging and Testing

Chairs: Russell Shumway, Amkor Technology; Robert Dean, Auburn University

2:00 pm –
2:30 pm

Assembly Challenges and Learnings for Large 2.5D TSV Products
Michael Kelly, Amkor Technology (Marnie Mattei, Rick Reed)

Development of Plating Process for Micro Bump Formation
Takuma Katase, Mitsubishi Materials Corporation (Koji Tatsumi, Tekeshi Hatta, Masayuki Ishikawa, Akihiro Masuda)

Microfluidic Technology Using SU8 on Top of PCBs
Stefan Gassmann, University of Rostock (Lienhard Pagel)

2:30 pm –
3:00 pm

3D Integration of System-in-Package (SiP): Toward SiP-Interposer-SiP for High-End Electronics
Rabindra Das, Endicott Interconnect Technologies, Inc. (Frank Egitto, Steven Rosser, Erich Kopp, Barry Bonitz)

Production of Uniform Dimension Copper Pillars for Flip Chip CSP
Stephen Kenny, Atotech Germany (Kai Matejat, Carsten Schauer, Sven Lamprecht)

Characterization of Aluminum-Germanium Wafer Bonding for MEMS Packaging
Sumant Sood, SUSS MicroTec (Robert Hergert, Oliver, Oliver Treichel, Sean Peng, Mars Chuang)

3:00 pm –
3:30 pm

Novel Low-Loss Photodefined Electrical TSVs for Silicon Interposers
Paragkumar Thadesar, Georgia Institute of Technology (Muhannad Bakir)

Semiconductor Fluxes for Wafer Bumping in 3D Assembly
Maria Durham, Indium Corporation (Laura Mauer, Solid State Equipment Corp.; Andy Mackie, Indium Corporation)

CoC (Chip on Chip) or FtoF (Face to Face) - PossumTM Technology for 3D MEMS and ASIC Eliminating the Need of TSV or Wire Bonding
Jemmy Sutanto, Amkor Technology (D. H. Kang, J. H. Yoon, K. S. Oh, Michael Oh, Amkor Technology Korea; R. Lanzone, R. Huemoeller, Amkor Technology)

3:30 pm –
4:15 pm

Break in Exhibit Hall

Sponsored by:
STATSChipPAC - Coffee Break Sponsor Applied Materials - Coffee Break Sponsor SETNA Corporation - Coffee Break Sponsor
4:15 pm –
4:45 pm

Polymer Based Interposer with Si Matched CTE
Karen Shrier, Electronics Polymer Newco Inc

Micro-tube Insertion into Aluminum Pads: Simulation and Experimental Validations
Alexis Bedoin, CEA- LETI, MINATEC (B. Goubault de Brugiere, F. Marion, F. Berger, M. Fendler, M. Volpert, H. Ribot)

Package Level Self-Test System for Electronic Compass
Dario Paci, STMicroelectronics

4:45 pm –
5:15 pm

Ultra High Density Capacitors Merged with Through Silicon Vias to Enhance Performances.
Catherine Bunel, IPDIA

Lead Free Paste with Under 3um Solder Particles for Fine Pitch C4 Bumping and Pre-Coating Solder Applications
Hironori Uno, Mitsubishi Materials Corporation (Masayuki Ishikawa, Akihiro Masuda, Hiroki Muraoka, Kanji Kuba)

A Design Tool Fully Adapted to the Development of the Thin Film Encapsulation Used for MEMS Devices
Souchon Frederic, CEA-LETI, MINATEC (Gervais Anne-Charlotte, Thouy Laurent, Saint-Patrice Damien, Pornin Jean Louis)

5:15 pm –
5:45 pm

3D Packaging- Through Glass Vias TGV with Alkali Free Glass for Advanced Packaging
Vern Stygar, AGC (Tim Mobley, Shintarou Takahashi)

 

 

5:45 pm –
7:00 pm

Exhibit Hall Reception

Sponsored by:
Applied Materials - Event Sponsor

DPC Sponsor: Applied Materials

 


Conference Registration

Early Rate Ends:
February 8, 2013

All registration fees increase after the deadline

Register Today


STATS ChipPAC

 

WEDNESDAY, MARCH 13   
Morning Technical Sessions

7:00 am -
6:00 pm

Registration

7:00 am -
8:00 am

Continental Breakfast

Sponsored by:
Breakfast Sponsor: ASE US, Inc.

8:00 am -
8:45 am

KEYNOTE – MEMS
MEMS and MEMS Packaging for High Temperature and Other Harsh Environments
Dr. F. Patrick McCluskey, Associate Professor
UNIVERSITY OF MARYLAND

Abstract: Recent advances in Microelectromechanical systems (MEMS) technology have resulted in relatively low cost MEMS gyroscopes. Their unique features compared to macro-scale devices have made them popular in many applications. Nowadays, MEMS gyroscopes are lighter, smaller and consume less power and therefore, are considered to be the best low-cost solution compared to spinning disk or wheel type mechanical gyroscopes. These low-cost MEMS gyroscopes have opened up a wide variety of applications with environmental conditions ranging from mild-to-harsh. Many of these harsh environments include high temperature, high humidity, high-G mechanical shock/drop, high-frequency mechanical vibration and high frequency acoustic noise. This web seminar will review the studies conducted to understand the effect of such harsh environment on MEMS gyroscopes. It also examines the effects of an elevated temperature and sustained exposure to temperature combined humidity on the MEMS vibratory gyroscope.

Dr. Patrick McCluskey is an Associate Professor of Mechanical Engineering at the University of Maryland, College Park. He is associated with the CALCE center where he is the principal investigator for projects related to packaging and reliability of electronic components for high power and high temperature environments. He is the author or co-author of over 100 technical articles on his research, and the co-author of three books. He has served as the technical program chair for several symposia and conferences in these research areas. He is a fellow of IMAPS and is a member of ASME, IEEE, and SAE.

8:45 am -
9:30 am

KEYNOTE – LEDs
Packaging Innovation: The Key to the Future of Solid State Lighting
Robert F. Karlicek, Jr., Professor & Director, Smart Lighting Engineering Research Center
RENSSELAER POLYTECHNIC INSTITUTE

Abstract: LED technology development has progressed very rapidly since the first lighting class blue LEDs were introduced more than 20 years ago. Today, LED chip performance for solid state lighting is closing in on theoretical limits of performance and high volume manufacturing of LED devices for solid state lighting is rapidly driving down die prices. Increasingly, barriers to delivering cost effective high performance solid state lighting are driven by the limitations of conventional LED packaging technologies where optical management adds complexity to conventional packaging methods and the limitations of conventional pick and place technology add barriers to cost reduction. New approaches to LED packaging are borrowing tricks from state-of-the-art silicon device packaging methods, and continued packaging innovation is required to realize the full potential of solid state lighting. This talk reviews the status of LED lighting from the chip, packaging and lighting system perspective, and describes some key areas where packaging innovation is still required to drive adoption of solid state lighting systems.

Dr. Robert F. Karlicek, Jr. is the Director of the Smart Lighting Engineering Research Center at Rensselaer Polytechnic Institute, an NSF and industry funded program exploring advanced applications for next generation solid state lighting systems. Prior to joining RPI, he spent over 30 years in industrial research and R&D management positions with corporations including AT&T Bell Labs, EMCORE, General Electric, Gore Photonics, Microsemi, Luminus Devices and SolidUV. Dr. Karlicek is well known globally as an LED industry expert, and is a frequent presenter at conferences and workshops. He obtained his Ph.D. in Physical Chemistry from the University of Pittsburgh and has over 40 published technical papers and 26 U.S. patents.

9:30 am -
10:00 am

Break in Foyer

Sponsored by:
Sikama - Break Sponsor Break Sponsor: Amkor Technology
 
Advanced 3D Packaging
Flip Chip & Wafer Level Packaging
LED Packaging for Future Solid-State Lighting

 

WA1
Substrates & Materials for 3D IC Processing

Chairs: Jeff Calvert, Dow Chemicals; Phil Garrou, Microelectronic Consultants of NC

WA2
Substrate Effects and Materials

Chairs: Lars Boettcher, Fraunhofer IZM; Linda Bal, Freescale

WA3
Packaging for Advanced LED SSL Systems

Chairs: Thomas Goodman, E&G Technology Partners; Bob Karlicek, Rensselaer Polytechnic Institute

10:00 am – 10:30 am

Precision Glass Carriers and Metrology for Wafer Thinning Operations
Aric Shorey, Corning Inc. (Bor-Kai Wang, Joe Canale, Windsor Thomas)

Effect of Substrate Layer Variation on Package Warpage
Brendan Wells, Amkor Technology (Wei Lin, HyunJin Park)

LEDs for SSL - Market Trends, Drivers, and Applications
Vrinda Bhandarkar, PennWell / Strategies Unlimited

10:30 am – 11:00 am

Temporary and Permanent Adhesives for Thin Wafer Handling and Assembly
Mark Oliver, Dow Electronic Materials (Jong-Uk Kim, Zidong Wang, Janet Okada, Elissei Iagodkine, Anupam Choubey, Ed Anzures, David Fleming, Avin Dhoble, Chi Truong, Michael Gallagher; Kai Zoschke, Matthias Wegner, Michael Toepper, Fraunhofer IZM)

From Mechanical Adhesion to Chemical Adhesion: Challenges in Obtaining Sufficient Adhesion Between Electroless Copper and Dielectrics
Robin Taylor, Atotech USA (Meng Hsieh, Ellina Libman, Lutz Brandt)

A Solder Joint Reliability Model for the Philips Lumileds LUXEON Rebel LED Carrier Using Physics of Failure Methodology
Greg Caswell, DfR Solutions (Rudi Hechfellner, Michiel Kruger, Tewe Heemstra, Philips Lumileds; Nathan Blattau, Gregg Kittlesen, Vikrant More, DfR Solutions)

11:00 am – 11:30 am

Versatile Z-Axis Interconnection for High Performance Electronics
Rabindra Das, Endicott Interconnect Technologies, Inc. (J. M. Lauffer, F.D. Egitto)

Adopt advanced RDL Rule to Apply Flip Chip Packaging for Next Generation Si Technology: Feasibility Study
Shengmin Wen, Amkor Technology (KyungRok Park, Patrick Thompson, JeongSeok Lee, HyunJin Park)

Lithography for Wafer Level Packaging for LED Manufacturing
Tim McCrone, SUSS MicroTec Lithography GmbH

11:30 am – 12:00 pm

Electrografted Insulator Layer as Copper Diffusion Barrier for TSV Interposers
Vincent Mevellec, ALCHIMER (Dominique Suhr, Thomas Dequivre, Frederique Raynal)

Direct Palladium-Gold on Copper as a Surface Finish for Next Generation Packages
Mustafa Ozkok, Atotech (Sven Lamprecht, Gustavo Ramos, Arnd Kilian)

Advanced Passive Thermal Management for LED Bulb Systems
James Petroski, Rambus

12:00 pm – 12:30 pm

Wafer Level Interconnects for 2.5D/3D Enroute to Manufacturing
Sesh Ramaswami, Applied Materials

 

High Thermal Conductivity Die Attach Technology for LED Die Attach and Chip-on-Board Applications
Ravi Bhatkal, Alpha, an Alent plc Company
12:30 pm -
4:30 pm

Exhibition and Technology Showcase

12:30 pm –
2:30 pm

Lunch In The Exhibit Hall
(Food served from 12:30 pm - 1:30 pm)

Sponsored by:
Lunch Sponsor: Amkor Technology
 
2:00 pm –
4:30 pm

Interactive Poster Session
In The Exhibit Hall: 2:00 pm – 4:30 pm
(Poster Presenter Setup - 1:30 pm - 2:00 pm)

 

Elimination of Delamination in Flexible Circuits Due to Chemical Solvent Absorption by
Implementing Post-Assembly Laser Excising

Susie Krzmarzick, Starkey Hearing Technologies (John Dzarnoski, Yangjun Xing)

Development of Embedded High Power Electronics Modules for Automotive Applications
Lars Boettcher, Fraunhofer IZM (S. Karaszkiewicz, D. Manessis, A. Ostmann)

Development of Substrate Embedded Magnetics for DC-DC Buck Converters
Jeff Aggas, Auburn University (Aubrey Beal, Robert Dean)

Singulation Blades and Physics
Edward Perry, Kim & Ed PTE LTD Singapore

A Novel Silicone Material for 3D Flex Package with Multi Chips
Bo Zhang, Institute of Microelectronics Chinese Academy of Sciences
(Wen Yin, Yuan Lu, Liao Anmou, Du Tianmin, Dongkai Shangguan, Lixi Wan)

CO2 Composite Spray (TM) Cleaning for Wire Bonding
David Jackson, Cleanlogix LLC

Poster Session Sponsored by:
Sponsor: Lam Research


 

WEDNESDAY, MARCH 13   
Afternoon Technical Sessions
 
Advanced 3D Packaging
Flip Chip & Wafer Level Packaging
Advanced 3D Packaging 2

 

WP1
Processing Challenges & Solutions for 3D Packages

Chairs: Laura Mauer, Solid State Equipment Corp.; Rozalia Beica, Lam Research

WP2
Wafer Level Fan-Out Packages & Materials

Chairs: Eric Huenger, Dow Chemical; Curtis Zwenger, Amkor

WP3
Stress & Thermal Management in 3D IC Processing

Chairs: Gilles Poupon, CEA Leti; Keith Cooper, SETNA

2:30 pm –
3:00 pm

Fabrication of 3D-IC Interposers
Aric Shorey, Corning Inc. (John Keech, Garret Piech, Scott Pollard)

Robust Reliability Performance of Large Size eWLB (Fan-out WLP)
Seung Wook Yoon, STATSChipPAC, Ltd.

A Process Dependent Warpage and Stress Model for 3D Packages Considering Incoming Die/Substrate Warpage and Assembly Process Impacts
Wei Lin, Amkor Technology (Ahmer Syed, KiWook Lee, Karthikeyan Dhandapani)

3:00 pm –
3:30 pm

Low Temperature MOCVD TiN Barrier Deposition for High Aspect Ratio TSVs : A Solution for 3D Integration
Arnaud Garnier, CEA-LETI Minatec (Thierry Mourier, Stephane Minoret, Larissa Djomeni , Sylvain Maitrejean, Anne Roule, Laurent Vandroux; Sabrina Fadloun, Steve Burgess, Andy Price, Chris Jones, SPTS Technologies SAS)

Reliability and Performance Improvements of 3D System-in-Packages in Fan-Out Wafer Level Packaging
Scott Hayes, Freescale (Tony Gong, Doug Mitchell, Michael Vincent, Jason Wright, Yap Weng Foong)

Thermal & Mechanical Challenges for 3DIC Integration
Severine Cheramy, CEA-LETI

3:30 pm –
4:00 pm

Through Si Vias Using Liquid Metal Conductors for Re-workable 3D Electronics
George Hernandez, Auburn University (Daniel Martinez, Stephen Patenaude, Charles Ellis, Michael Palmer, Michael Hamilton)

Innovative 3D Structures Utilizing Wafer Level Fan-Out (WLFO) Technology
Curtis Zwenger, Amkor Technology (JinYoung Khim, YoonJoo Khim, SeWoong Cha, SeungJae Lee, JinHan Kim, Amkor Technology, Korea)

Thermal Performance Evaluation of xFD Packages
Ron Zhang, Invensas Corporation (H. Shaba, J. Tseng, E. Chau, W. Zohni, L. Mirkarimi)

4:00 pm –
4:30 pm

Break in Exhibit Hall

Sponsored by:
Sikama - Break Sponsor Break Sponsor: Amkor Technology
4:30 pm –
5:00 pm

Strain in Electroless Copper Films: Analysis by In Situ X-Ray Diffraction and Curvature Methods
Simon Bamberg, Atotech Deutschland GmbH (Tobias Bernhard ( Laurence Gregoriades, Frank Bruning, Ralf Broening, Johannes Etzkorn, Wolfgang Friz, Michael Merschky, Bruce Muir, Laura Perry, Tanu Sharma)

A New Embedded Package Structure and Technology for the Next Generation of WLP, the Wafer level Fun-Out Package - WFOP (TM)
Akio Katsumata, J-Devices Corporation

Techniques and Tools for Collaborative Thermal and Mechanical Modeling of 3D ICs
Kamal Karimanal, Cielution LLC

5:00 pm –
5:30 pm

Extending the Strip Window for Advanced Packaging Photoresists
Mani Sobhian, TEL NEXX

Development of a Low Residual Stress and High Performance Dielectric for WLP (Wafer Level Packaging) Applications
Raymond Thibault, Dow Electronic Materials (Michael Gallagher, Kevin Wang, Matthew Yonkey, Duane Romer, Xiang Qian Liu, Kim Ho, Greg Prokopowicz, Joe Lachowski, Mark Oliver, Eric Huenger, Seiji Inaoka, Scott Kisting, Lynne Mills, Sue McNamara, Rosemary Bell)

Development of Embedded High Power Electronics Modules for Automotive Applications
Lars Boettcher, Fraunhofer IZM (S. Karaszkiewicz, D. Manessis, A. Ostmann)

5:30 pm –
6:00 pm

Copper, Nickel, and Lead-Free Solder Electroplating Solutions for Pillar and Micro-Pillar Capping Applications
Julia Woertink, Dow Electronic Materials (Erik Reddington, Inho Lee, Yi Qin, Jonathan Prange, Pedro Lopez Montesinos, Jui-Ching Lin, Masaaki Imanari, Jianwei Dong, Wataru Tachikawa, Jeff Calvert)

Integration of Passive Components into 3D PoP Fan-Out Packages
Tom Strothmann, STATSChipPAC

3D ICs with Embedded Microfluidic Cooling and High Aspect Ratio TSV Integration
Paragkumar Thadesar, Georgia Institute of Technology

6:00 pm – 7:30 pm


Panel Discussion: 3D Integration - Applications and Production Challenges
Please join us for an interactive panel discussion on 3D Integration - Applications and Production Challenges. An executive panel has been assembled from several of the leading microelectronics organizations from around the world to discuss the latest applications, trends in the industry, challenges, reliability, and production readiness. The panel will be soliciting questions from the audience.

Panel Food/Beverage Sponsored by:
3D Panel Sponsor: Invensas

Moderators: Rozalia Beica, Lam Research AG; Peter Ramm, Fraunhofer EMFT

Panelists:
Sitaram Arkalgud, Invensas;
Rich Rice, ASE US;
Arif Rahman, Altera
Matt Nowak, Qualcomm
E. Jan Vardaman, TechSearch International

 

Post-Conference Presentations USB Flash Drive

This year the Conference technical & exhibitor presentations will be published and distributed to all "full conference" attendees & exhibitors on USB Flash Drives. These drives will be mailed to attendees and exhibitors following the Conference.

Sponsored by:

ALLVIA - Event Sponsor

 

THURSDAY, MARCH 14   
Technical Sessions

7:00 am –
11:30 am

Registration

7:00 am –
8:00 am

Continental Breakfast

Sponsored by:
Breakfast Sponsor: ASE US, Inc.

8:00 am -
8:45 am

KEYNOTE – 3D
2.5 D Options: Organic Vs. Silicon.Vs Glass; Technologies, Costs and Applications
Dr. Rao R .Tummala, Director PRC
GEORGIA INSTITUTE OF TECHNOLOGY

Abstract: Transistor scaling, starting with the invention of transistor in 1940s, made electronics the largest global industry, serving a variety of individual industries that span computing, communications, consumer, automotive and others . A new industry that integrates all these into so-called Smart Mobile Systems promises to be the next frontier in electronics hardware, performing every imaginable function in smallest size and lowest cost that every global person could afford. Such revolutionary systems, however, require revolutionary technologies referred to as system scaling, in contrast to transistor scaling during the last 60 years. Current hardware approaches based on organic laminates has four main limitations: 1) lithographic ground rules, 2) thermal performance, 3) mismatch in TCE-driven, and moisture-driven reliabilities, and 4) warpage, as these are processed as ultra-thin packages. Inorganic packages such as Glass or Silicon address these fundamental problems. These can be combined appropriately and selectively with ultra-thin and special polymers as dielectrics, liners and stress-relief members. This presentation will try to clarify the role and regimes of each of these organic, silicon and glass interposers for 2.5 and 3D applications.

Professor Rao Tummala is a Distinguished and Endowed Chair Professor, and Founding Director of NSF ERC, called PRC at Georgia Tech, known as the world's premier systems packaging Center pioneering System Scaling technologies, producing the most cross-disciplinary engineers and transferring both to global industry. Prior to joining Georgia Tech, he was an IBM Fellow, pioneering the first plasma display and low temperature co-fired(LTCC) multichip electronics for mainframes and servers. Prof. Tummala published about 500 technical papers, holds 90 patents and inventions; authored the first modern Microelectronics Packaging Handbook, the first undergrad textbook, "Fundamentals of Microsystems Packaging", and first book introducing the System-On-Package technology. His Georgia Tech PRC Center is considered the number 1 Academic Center having produced more than 1000 Ph.D, MS and BS students, 2000 publications and collaborating with more than 100 companies in US, Europe, Japan and Korea. He is a Fellow of IEEE, and a member of National Academy of Engineering in US and India . He was a past President of IEEE-CPMT and the IMAPS Societies.

8:45 am -
9:30 am

KEYNOTE –3D
Future of Package for Computing Electronics
Ram S. Viswanath, Assembly Technology Planning and Pathfinding
INTEL CORPORATION

Abstract: Computing, communication and entertainment media have rapidly converged creating a wide range of "smart" devices, driven by the Internet and the need and desire to be "always connected." New device categories are emerging at a rapid pace to bring computing experiences into every aspect of our lives. Consumers are demanding consistency and interoperability across all of their devices, from phone to PC to tablet to TV to gadget, making computing a seamless experience regardless of where you are, what you are doing or what your needs at the time may be. This computing continuum or convergence is predicted to result in more than 10B connected devices by 2015 with significant challenges and opportunities for microelectronic packaging. This presentation will focus on explaining these challenges and potential future solutions with regard to increased demand for memory bandwidth, multi functionality, and higher wiring density to meet the Si scaling requirements, thinner and smaller form factors, multi-chip and embedded packaging while also addressing the challenges associated with demand for lower cost and environmental sustainability.

Ram Viswanath leads the Package Architecture and Technology Definition for all Intel products. He has been with the Assembly and Test Technology organization for the past twenty years. His recent focus is in developing ultra thin small form factor packaging for mobile computing and high performance interconnects for server CPU's. He has numerous patents in the areas of thermal sciences, sockets, high speed interconnects and 3D packaging. Ram received his doctorate from Rutgers University in Mechanical and Aerospace Engineering.

9:30 am –
9:45 am

Break in Foyer

Sponsored by:
STATSChipPAC - Coffee Break Sponsor Applied Materials - Coffee Break Sponsor SETNA Corporation - Coffee Break Sponsor
 
Advanced 3D Packaging
Flip Chip & Wafer Level Packaging
Advanced 3D Packaging 2

 

THA1
Reliability Considerations in 3D Packaging

Chairs: Severine Cheramy, CEA Leti; James Lu, Rensselaer Polytechnic Institute

THA2
Applications of FC & WLP Packages

Chairs: Scott Hayes, Freescale; Jon Aday, FlipChip International

THA3
3D and WLP Metrology & Inspection

Chairs:Jianwei Dong, Dow Chemicals; Rozalia Beica, Lam Research

9:45 am –
10:15 am

The Continued Adoption of ZiBond® and DBI® in Volume Applications
Kathy Cook, Ziptronix, Inc.

High Reliability Fine Pitch WLCSP
David Lawhead, FlipChip International (Ronnie Yazzie, Tony Curtis, Guy Burgess, Ted Tessier)

Multi-Scale Materials Data for 3D TSV Stack Performance Simulation and Model Validation
Ehrenfried Zschech, Fraunhofer IZFP (Kong Boon Yeap, Christoph Sander, Uwe Mohle, Fraunhofer IZFP-D; Valeriy Sukharev, Mentor Graphics)

10:15 am –
10:45 am

Integration, Electrical Performance and Reliability Investigation of TSV
Shih-Wei Lee, National Chiao Tung University (Yu-Chen Hu, Cheng-Hao Chiang, Kuo-Hua Chen, Chi-Tsung Chiu, Ching-Te Chuang, Wei Hwang, Jin-Chern Chiou, Ho-Ming Tong, Kuan-Neng Chen)

RF Devices: from WLSCP to Smart Interposers
Yann Lamy, CEA-LETI (O. El Bouayadi, C. Ferrandon, S. Joblot, A. Jouve, L. Dussopt, T. Lacrevaz, C. Bermond, B. Flachet, G. Simon)

Metrology and Inspection of 3D IC TSV Integration Processes
G. Fresquet , Fogale NANOTECH

10:45 am –
11:15 am

The Reliability Study of a High Density Multi Chip Packaging with Folding Flexible Substrate
Yin Wen, Inst. of Micro., Chinese Academy of Sciences (Bo Zhang, Yuan Lu, Liao Anmou, Du Tianmin, Lixi Wan)

Electrical Characterization on a High-Speed Wafer-Level Package
Kai Liu, STATSChipPAC (YongTaek Lee, HyunTai Kim, MaPhooPwint Hlaing, Susan Park, Billy Ahn)

Discover, Analyze and Monitor Yield-limiting Events in a WLP process
Reza Asgari, Rudolph Technologies

11:15 am –
11:45 am

Ultra-Fine Pitch Package on Package Solution for High Bandwidth Mobile Applications
Rajesh Katkar, Invensas Corp. (Zhijun Zhao, Ron Zhang, Rey Co, Laura Mirkarimi)

Advanced Microelectronics Packaging Solutions for Miniaturized Medical Devices
Rabindra Das, Endicott Interconnect Technologies (Steven Rosser, Frank Egitto)

An Innovative 2.5D IC Interconnection Reliability System
Doug Goodman, Ridgetop Group (Andrew Levy , Hans Manhaeve, Ridgetop; Ed McBain, ALLVIA)

11:45 am –
12:00 pm

Closing Remarks (in Main 3D Session Room)

1:15 pm Start

2013 IMAPS Microelectronics Foundation Spring Golf Invitational
1:15pm Shotgun Start -- "Best Ball" Scramble

Desert Canyon Golf Club
10440 Indian Wells Drive
Fountain Hills, AZ

Golf Sponsors

Premier - "Eagle" Sponsor:
DPC/GBC Premier Sponsor: Solid State Equipment Corp.
3 Holes Sponsor

Premier - "Eagle" Sponsor:
DPC/GBC Premier Sponsor: ASE US, Inc.
3 Holes Sponsor

Premier - "Birdie" Sponsor:

Golf Hole Sponsor: Amkor Technology
Hole Sponsor
Hole Sponsor: NAMICS
Hole Sponsor
Golf Hole Sponsor: Infinite Graphics
Hole Sponsor
Golf Hole Sponsor: SETNA
Hole Sponsor
Premier "Birdie" Sponsor: Invensas
Hole Sponsor
Golf Hole Sponsor: Coining Inc/SPM
Hole Sponsor

Golf Hole Sponsor: AGC Electronics America
Hole Sponsor

Golf Hole Sponsor: PUTTIST, 3-Putt Killer
Hole Sponsor
Golf Hole Sponsor: Dixon Golf
Hole Sponsor



Hotel Cut-off:

February 8, 2013
Rates and availability will not be guaranteed after the deadline

Radisson Fort McDowell Resort & Casino
$155/night

 

 

 

Professional Development Courses (PDCs) | Exhibition Information

 


Housing
Hotel Reservation Deadline - February 8, 2013

Housing accommodations must be made directly to:

Radisson Fort McDowell Resort & Casino
10438 North Fort McDowell Road
Scottsdale/Fountain Hills, AZ 85264

$155 single/double

 

Hotel Scams Alert!
Beware of Hotel Scams! Exhibition Housing Services has been soliciting several exhibitors indicating that they are the official housing vendor for IMAPS Device Packaging 2013 Please note that they are NOT affiliated with the show at all and are not working in your best interest. Booking rooms through companies such as Exhibition Housing Services could result in false reservations and a loss of deposit money.

The only way to book a room in the official IMAPS Housing Block using the reservations information above.



Speaker Dates/Information:

  • Abstracts Deadline Extended Until: December 7, 2012
  • Speaker Notification Emails: January 14, 2013
  • Extended Abstract or Abstract Book Materials due: February 8, 2013
  • Hotel Reservation Deadline: February 1, 2013
  • Early Registration Deadline: February 1, 2013
  • Speaker Bios Due: March 1, 2013
  • Powerpoint/Presentation file for CD-Rom due not later than: March 14, 2013 (Last day of Conference)
  • Powerpoint/Presentation file used during session: Speaker's responsibility to bring to session on USB and/or CD (recommended to have back-up on personal laptop or email to bschieman@imaps.org prior to event)
  • Technical Presentation Time: 30 minutes (25 to present; 5 for Q&A) - Keynotes: 45 minutes (40 to present; 5 for Q&A)

Presentation Format/Template:
IMAPS does not require you to use a conference powerpoint template.
You are able to use your regular company/preferred powerpoint templates.
Please include the IMAPS show name and dates on your template and/or an IMAPS logo.

Dress Code:
There is no officially "dress code" for IMAPS Conferences. We ask you to be BUSINESS CASUAL or whatever more you prefer. Most speakers tend to be in business pants and button down/company logo shirts (Women in dresses or the same). Suits, sport coats and ties are common as well. We do not recommend casual attire.

Session rooms will be equipped with:
Screen, projector, podium, IMAPS laptop (with Microsoft Windows and recent OFFICE suite), microphone, and slide remote/laser pointer.

All session presentations are 25 minutes followed by 5 minutes for Questions
You are required to load your powerpoint/presentation onto the session laptop yourself using your USB drive.
Speak with your session chair if you need assistance.

About the Session:
Sessions begin with Session Chairs making general announcements. Session Chairs will then introduce speakers by reading BIOs. Speaker will present for 25 minutes, followed by 5 minutes for questions. Session Chairs will thank the speakers. This process is repeated for each speaker in the session. Many sessions will take refreshment breaks (see program).

Photography is not permitted in the session rooms.

Silence all mobile phones during session attendance.



DPC/GBC Premier Sponsors:

DPC/GBC Premier Sponsor: Solid State Equipment Corp.

DPC/GBC Premier Sponsor: Amkor Technology

DPC/GBC Premier Sponsor: ASE US, Inc.


 

Sponsor - Post-Conference Presentations USB Drives:

ALLVIA - Event Sponsor

Sponsor - Exhibit Reception, Lunch & Break:

Applied Materials - Event Sponsor

Sponsor - Conference Lanyards:
Hole Sponsor: NAMICS

Sponsor - 3D Panel:
3D Panel Sponsor: Invensas

Sponsor:
Sponsor: SANTIER

Sponsor:
Sponsor: Dow Corning

Sponsor:
Sponsor: Lam Research

Sponsor - Refreshment Breaks:
SETNA Corporation - Coffee Break & Golf Sponsor

Sponsor - Refreshment Breaks:
STATSChipPAC - Coffee Break Sponsor

Sponsor - Refreshment Breaks:
Sikama - Coffee Break Sponsor

Sponsor - GBC Speaker Dinner:
Kyocera - GBC Speaker Dinner Sponsor


 

"Eagle" Golf Sponsors:
"Eagle" Golf Sponsor: Solid State Equipment Corp.

DPC/GBC Premier Sponsor: ASE US, Inc.

"Birdie" Golf Sponsor:
"Birdie" Golf Sponsor: Amkor Technology


Golf Hole Sponsors:

Golf Hole Sponsor: NAMICS

Golf Hole Sponsor: Infinite Graphics

Golf Hole Sponsor: SETNA

Premier "Birdie" Sponsor: Invensas

Golf Hole Sponsor: Coining Inc/SPM

Golf Hole Sponsor: AGC Electronics America

Golf Hole Sponsor: PUTTIST, 3-Putt Killer

Golf Hole Sponsor: Dixon Golf


 

Student Paper Competition
Sponsor:


Student Paper Competition Sponsor - The Microelectronics Foundation


 

Media Sponsors:

Yole Developpement

I-Micronews

3D InCites - Media Sponsor

MEPTEC


© Copyright 2010 IMAPS - All Rights Reserved
IMAPS-International Microelectronics And Packaging Society and The Microelectronics Foundation
611 2nd Street, N.E., Washington, D.C. 20002
Phone: 202-548-4001

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