13th International Conference and Exhibition on

WekoPa Resort and Casino
Fountain Hills, Arizona USA

IMAPS Device Packaging

Conference and Technical Workshops
March 7-9, 2017
Exhibition and Technology Showcase
March 7-8, 2017
Professional Development Courses
March 6, 2017
GBC Plenary Session
March 8, 2017
Device Packaging (Amkor Image)
Courtesy of Amkor Technology
Device Packaging (RDEDCOM image)
Courtesy of US Army RDEDCOM AMRDEC

General Chair:
Gilles Poupon

General Chair-Elect:
Peter Ramm
Fraunhofer EMFT Munich

Past General Chair:
Rozalia Beica
Dow Electronic Materials

Past General Chair:
Ron Huemoeller
Amkor Technology



Courtesy of Amkor Technology

The Largest 2017 Conference Dedicated to...

Interposers, 3D IC & Packaging;

Fan-Out, Wafer Level Packaging
& Flip Chip;

Engineered Micro Systems/Devices
(including MEMS/Sensors, 3D Printing...)

Courtesy of Amkor Technology

We hope to see you March 6-9, 2017 for this year’s Device Packaging Conference!
**2016 Conference presentations available at WWW.IMAPSOURCE.ORG**
The 12th International Conference and Exhibition on Device Packaging welcomed 526 total participants from 19 countries, sold out an 11th consecutive exhibit hall, and enjoyed a successful technical program! The conference also proudly welcomed: • A 10% increase in full conference attendees • 15% international attendees • 3 new sponsoring companies • Standing room only in the brand new SiP Sessions • Plus, much more!


Thank you to our Premier PLATINUM Sponsor:
Thank you to our Premier GOLD Sponsors:
DPC Premier Gold Sponsor: Amkor Technology
DPC Premier Gold Sponsor: NAMICS
DPC Premier Gold Sponsor: Nanium
DPC Premier Gold Sponsor: Cadence


2017 Conference Overview:

The 13th Annual Device Packaging Conference (DPC 2017) will be held in Fountain Hills, Arizona, on March 6-9, 2017. It is an international event organized by the International Microelectronics Assembly and Packaging Society (IMAPS).

The conference is a major forum for the exchange of knowledge and provides numerous technical, social and networking opportunities for meeting leading experts in these fields. The conference will attract a diverse group of people within industry and academia. It provides a chance for educational interactions across many different functional groups and experience levels. People who will benefit from this conference include: scientists, process engineers, product engineers, manufacturing engineers, professors, students, business managers, and sales & marketing professionals.


MONDAY, MARCH 6, 2017 -- Professional Development Courses (PDCs) & Welcome Reception
7:00 am - 7:00 pm
7:00 am - 8:00 am
Continental Breakfast
8:00 am - 12:00 pm
Morning Professional Development Courses (PDCs)
PDC1:Introduction to Copper Pillar Flip Chip Interconnect
Course Leader: Mark Gerber, ASE US

PDC2: Fundamentals of Aligned Wafer Bonding
Course Leaders: Eric Pabo, Viorel Dragoi, EV Group


PDC3: Trends & Analyses of Adv. Packaging Technologies and their Applications: from Smart Phones to Super Computers
Course Leader: Dev Gupta, APSTL, LLC
PDC4: Polymers in Semiconductor Packaging
Course Leader: Jeffrey Gotro, InnoCentrix, LLC
10:00 am - 10:20 am
12:00 pm - 1:00 pm
Lunch Only provided for those attendees registered for both Morning AND Afternoon PDCs
1:00 pm - 5:00 pm
Afternoon Professional Development Courses (PDCs)
PDC5: Electrical Modeling & Test Strategies for 3D Packages
Course Leader: Bruce Kim, City University of New York
PDC6: Fan Out Packaging - Technology Overview and Evolution
Course Leaders: John Hunt, ASE US
PDC7: Emerging Challenges in Semiconductor Packaging
Course Leader: Raja Swaminathan, Intel
PDC8: Stencil Printing Technology for Advanced Semiconductor and Assembly Applications
Course Leader: Phani Vallabhajosyula, Photo Stencil
3:00 pm - 3:20 pm
5:00 pm - 7:00 pm

Welcome Reception (All Attendees Are Invited To Attend)


Thank you to our Premier PLATINUM Sponsor:
Thank you to our Premier GOLD Sponsors:
DPC Premier Gold Sponsor: Amkor Technology
DPC Premier Gold Sponsor: NAMICS
DPC Premier Gold Sponsor: Nanium
DPC Premier Gold Sponsor: Cadence




TUESDAY, MARCH 7, 2017  -- Morning Keynote Presentations

7:00 am -
7:00 pm


7:00 am -
8:00 am

Continental Breakfast Sponsored by:
DPC Premier Gold Sponsor: NAMICS

8:00 am -
8:20 am

General Chair:
Gilles Poupon, CEA Leti

Keynote Sessions Sponsored by:

SPTS - Corporate Sponsor

SPTS - Corporate Sponsor

8:20 am -
9:05 am

Heterogeneous Integration: Packaging the Future

Technology innovation in the semiconductor industry continues to march forward at an incredible pace, with advancements in new silicon node technology continuing on one end of the spectrum with innovation in packaging solutions coming forward at the other in a complementary fashion. As the pace of innovation has quickened, so has the investments required to bring such technologies to production.  At the packaging level, the investments required to support the advancements in silicon miniaturization and heterogeneous integration have now reached well beyond $500M USD per year.  One needs to look no further than the complexity of the most advanced package technologies being used today and coming into production over the next year to understand why.

Advanced packaging technologies have increased in complexity over the years, transitioning from single to multi-die packaging, enabled by 3-dimensional integration, system-in-package (SiP), wafer-level packaging (WLP) and creative approaches to embedding die. These new innovative packaging technologies enable more functionality and offer higher levels of integration within the same package footprint, or even more so, in an intensely reduced footprint.  Today, the latest in advancements in heterogeneous integrated semiconductor packaging is able to provide reduced form-factor, increased data transfer rate, improved signal integrity and memory bandwidth, all with reduced power and improved thermal performance.  As we truly live in a connected world and the proliferation of connected devices is forcing continually higher system level performance, not surprisingly, it is semiconductor packaging that has stepped up to play a pivotal role in providing the solutions to the new system level requirements. 

Keynote - Ron Huemoeller

Ron Huemoeller, Amkor
Ron is Corporate Vice President, Worldwide R&D, at Amkor Technology. Ron joined Amkor in 1995 and has since served in multiple senior to executive level roles. Currently, Ron is responsible for global R&D and technology strategy.

Prior to joining Amkor, Ron was Director of Engineering at Cray Computer Corp. in Colorado Springs for 5 years, leading the facilitation, startup and development of state of the art motherboards for the world’s fastest supercomputer. Ron has authored numerous technical publications, co-authored a chapter in the Handbook of 3D Stacking (McGraw Hill) and has been granted more than 100 U.S. patents. Ron holds a B.S. in Chemistry from Augsburg College with highest honors, a MBA in Business Management from Arizona State University and a Masters in Technology Management from the University of Phoenix.

9:10 am -
9:55 am

Neither IoT nor 5G without new Technology!

5G networks are expected to unleash solutions that will help overcome barriers to widespread IoT adoption, such as technology hurdles leading to high connectivity costs, limited impact on user experience as well as security and privacy concerns.

Beyond the 28-nm node, new design costs increase exponentially. We cannot continue focusing on tinier transistors in the More-than-Moore era, when technology roadmaps call for heterogeneous integration, 3D and advanced packaging. Microelectronics is now led by system-driven roadmaps, and new drivers for 5G systems are diverging IoT services that require innovative flexibility and scalability from the technology. There is a new complexity in the drive of the technology roadmap since the transistor takes part of advanced system architectures where the software part is increasing.

The next step along the path of the digital era is a leap as roadmapping should be re-invented. Trends and examples of new integrated systems for IoT and 5G will be discussed in this presentation.

Keynote - Lionel Rudant

Lionel Rudant, CEA-Leti
Lionel Rudant is currently Strategic Marketing Manager at Leti. He draws up innovation strategies for conquering IoT markets through key enabling technologies that unleash innovative business. He has successfully transferred Leti wireless technologies to automotive, aeronautics, and industrial and consumer electronics industries, among others. He works on projects in France, Europe and the USA, and regularly presents technologies and system roadmaps at conferences and workshops.

He was awarded a postgraduate degree in electronics and digital technology by Nantes University (France) and a technology research degree by Grenoble Institute of Technology in 2003 and 2004 respectively. He then managed antenna projects for Radiall automotive and military systems. He joined Leti in 2006 and has since undertaken electromagnetics and antenna and propagation research, prompting publications on compact smart and disruptive super-directivity antennas.

10:00 am -
6:30 pm


10:00 am -
10:30 am

Break in the Exhibit Hall Sponsored by:

DPC Premier Gold Sponsor: Amkor Technology

Exhibit Reception Sponsor: Metalor


Advertisement: Smoltek


TUESDAY, MARCH 7, 2017  -- Morning Technical Sessions

Interposers, 3D IC & Packaging

Fan-Out, Wafer Level Packaging & Flip Chip

Engineered Micro Systems/Devices
(including MEMS & Sensors)



Chair: Lars Böttcher, Fraunhofer IZM; Stevan Hunter, ON Semi.


Chairs: Steffen Krõhnert, Nanium; Chris Scanlan, Deca

In this session we will have an opportunity to review the latest technical advancements in fan-out wafer level packaging (FOWLP) and the market forces driving the rapid adoption of fan-out wafer level packaging.


Chairs: Robert Weikle II, University of Virginia; Chase Harrison, Auburn University

This session focuses on advanced sensors and sensor systems.

10:30 am – 11:00 am

What is Driving the 3D TSV Technologies Business: Market Update and Technical Trends

Santosh Kumar, Yole Developpement (Thibault Buisson)

Fan-Out Wafer-Level-Packaging: Market and Technology Trends
Jerome Azemar, Yole Developpement

A Wireless Hay Bale Status Sensor Suite Using PCB Sensor Technology
Jeff D. Craven II, Auburn University (Andrew Muscha, R. Chase Harrison, Markus Kreitzer, Robert Dean, Beth Guertal)

11:00 am – 11:30 am

Development of High Yield and Reliability Design for High-performance Ultra Large Scale 3DLSI Processor
Hideki Kitada, Fujitsu Limited

Application of 3D PLUS WDoD Technology for the Manufacturing of Electronic Modules in Implantable Medical Products
Pascal Couderc, 3D PLUS

Evaluation of an In-Situ Atmospheric System for Real Time Weather Monitoring
J. Craig Prather, Auburn University (Michael Bolt, Haley Harrell, Tyler Horton, Mark Adams)

11:30 am – 12:00 pm

RDL Multilayer Metallization Approaches for TGV 
Roupen Keusseyan, SAMTEC (Tim Mobley,  Elizabeth Young-Dohe)

Cost Comparison of Fan-out Wafer Level Packaging and Flip Chip Packaging                
Amy Lujan, SavanSys Solutions LLC

A PCB Sensor Suite for Monitoring the Effects of Annual Variations in Precipitation Rates on Alpine Lakes in Rocky Mountain National Park          
Robert Dean, Auburn University (Isabella Oleksy, Daniel Bowker)

12:00 pm – 12:30 pm

Glass Solutions for Next Generation Packaging Needs
Aric Shorey, Corning Inc. (Rachel Lu, Gene Smith)

FOWLP Technology as an Wafer Level System in Packaging (SiP) Solution
Lewis(In Soo) Kang, nepes Corporation

Advanced Wireless Sensor Nodes - MSFC 
Kosta Varnavas, NASA

12:30 pm –
2:00 pm

Lunch In The Exhibit Hall Sponsored by:
(Food served from 12:30 pm - 1:30 pm)

DPC/GBC Premier Sponsor: ASE US, Inc.

Corporate Sponsor - NGK NTK



TUESDAY, MARCH 7, 2017  -- Afternoon Technical Sessions, Exhibit Hall Reception & Evening Panel on Fan-Out


Interposers, 3D IC & Packaging

Fan-Out, Wafer Level Packaging & Flip Chip

Engineered Micro Systems/
Devices - 1
(including MEMS & Sensors)

Engineered Micro Systems/
Devices - 2
(including MEMS & Sensors)



Chair: Rahul Agarwal, AMD; Peter Ramm, Fraunhofer EMFT


Chairs: Scott Hayes, NXP; Eric Huenger,  Dow     

In this session we will focus on identifying some of the key design attributes and challenges associated with the implementation of Fan-out WLP packaging design into various integration schemes and industrial application space as the use of organic substrate platforms continue to take hold in the industry.


Chairs: Catherine Bunel, IPDiA; Maaike M. Visser Taklo, SINTEF

This session focuses on packaging and integration technologies for engineered micro devices and systems.


Chairs: Ned Corron, U.S. Army; Edmon Perkins, Auburn University

This session focuses on the utilization of chaos theory to enhance engineered systems.

2:00 pm –
2:30 pm

Technology Review of System in Package
Yashashree Wase, University of Idaho (Feng Li)

Development of High Density Fan Out (HD-FO) Package Platform for High Performance and RF Applications
Gaurav Sharma, GlobalFoundries (Adam Beece, Gao Shan, Marcel Wieland)

Curved CMOS Image Sensors: Applications and Roadmaps
Bertrand Chambion, Univ. Grenoble Alpes, CEA-LETI (G.Moulin, S.Caplet, C. Gaschet, S.Getin, A.Vandeneynde, W. Jahn, D.Henry, E.Hugot)

Electronic Chaotic Oscillator Realization with Potential Uses in Communication Systems
Benjamin Rhea, Auburn University (F. T. Werner, R. C. Harrison, A. N. Beal, R. N. Dean)

2:30 pm –
3:00 pm

First Demonstration of Fine Line RDL Yield Enhancement Using an Innovative Ozone Treatment Process for Panel Fan-out and Interposers
Atul Gupta, MKS Instruments (Eric Snyder, Christiane Gottschalke, Kevin Wenzel, James Gunn, Hao Lu, Yuya Suzuki, Venky Sundaram, Rao Tummala)

Development of Embedded Silicon Fan-Out Technology for Low Cost Wafer Level Packaging
Hong Xie, Flip Chip International, a division of Hua Tian Technology Group (Daquan Yu, Zhenrui Huang, Zhiyi Xiao, Li. Yang, Min Xiang)

New Packaging Concept for Power LEDs
Marion Volpert, CEA-LETI (B. Soulier, P. Peray, N. Ait-Mani, A. Gasse, D. Henry, C. Tallet, V. Beix, A. Aboulaich, C. Zheng-Sung, J. L. Diot)

A Compact and Low Power Realization of a High Frequency Chaotic Oscillator
R. Chase Harrison, Auburn University (Benjamin Rhea, Frank Werner, Robert Dean)

3:00 pm –
3:30 pm

3D High Density: Technology, Roadmap and Applications
Lucile Arnaud, CEA-Leti (Severine Cheramy, Amandine Jouve, Claire Fenouillet, Perrine Batude, Maud Vinet)

Application of SU-8 photoresist as a Multi-functional Structural Dielectric Layer in FOWLP
Raquel Pinto, NANIUM S.A. (André Cardoso, Sara Ribeiro, Carlos Brandão, NANIUM S.A; Joe Gaspar, Rizwan Gill, Helder Fonseca, Margaret Costa, INL Braga Portugal)

Low ESL and Low Profile Decoupling Silicon Capacitor for Power Delivery Network
Catherine Bunel, IPDiA , a Murata Company (Franck Murray)

Modeling Nonlinear MEMS Beams and the Chaotic Duffing Oscillator in SPICE
Aubrey Beal , U.S. Army AMRDEC / Oakridge (PRESENTED BY ROBERT DEAN)

3:30 pm –
4:00 pm

Break in Exhibit Hall Sponsored by:

DPC Premier Gold Sponsor: Nanium
DPC Premier Gold Sponsor: Cadence

4:00 pm –
4:30 pm

3D Modular Power Electronic Packages and Modules for Different Power Classes - from 50W to 50kW
Lars Böttcher, Fraunhofer IZM ( S. Karaszkiewicz , D. Manessis , A. Ostmann)

Silicon Wafer Integrated Fan-out Technology Packaging
Suresh Jayaraman, Amkor Technology (Curtis Zwenger, George Scott, Bora Bolaglu, Amkor Technology, Inc.; WonChul Do, WonGeol Lee, JiHun Yi, Amkor Technology, Korea)

Multi-Scale Modeling of Self Heating Effects on Power Consumption in Silicon CMOS Devices
Robin Daugherty, Arizona State University (Dragica Vasileska)

Nonlinear Channelizer
Visarath In, SPAWAR Systems Center Pacific (Patrick Longhini, Antonio Palacios)

4:30 pm –
5:00 pm

The Effect of Conductor Resistance and Surface Roughness for RF Mobile and Medical Devices
Vern Stygar, AGC (Shin Takahashi, Youichirou Satou)

Advanced 3D eWLB-SiP (embedded Wafer Level Ball Grid Array – System in Package) Technology
Vinayak Pandey, STATS ChipPAC Pte Ltd (Seung Wook Yoon)

Pillar Density Modulation in a Semi-packed MEMS Column
Ryan Chan, Virginia Tech (Bishnu Regmi, Ana Lopez Marcano, Sarah El-Helw, Masoud Agah)

Nonlinear Dynamics and Quantum Entanglement in Optomechanical Systems
Guanglei Wang, Arizona State University (Liang Huang, Ying-Cheng Lai, Celso Grebogi)

5:00 pm –
5:30 pm

System Level Packaging - Module Integration, Current and Future
Mike Kelly, Amkor Technology (Curtis Zwenger, Jesse Galloway, Rama Alapati, Ron Huemoeller)

Integration of MEMS/ Sensors in Fan-Out Wafer-Level Packaging Technology based System-in-Package (WLSiP)
Steffen Kroehnert, NANIUM S.A. (André Cardoso, Raquel Pinto, Elisabete Fernandes, Isabel Barros)

Ultra-Stable MicroTorr-Level Vacuum Packaging for High Performance Inertial Sensors
Mohammad Asadian, University of California, Irvine (Sina Askari, Andrei Shkel)

Superpersistent Currents and Whispering Gallery Modes in Relativistic Quantum Chaotic Systems
Hongya Xu, Arizona State University

5:30 pm –
6:30 pm

Exhibit Hall Reception
Sponsored by:

DPC/GBC Premier Sponsor: ASE US, Inc.

Exhibit Reception Sponsor: Metalor

EMD Performance Materials - Corporate Sponsor

Exhibit Hall Reception Sponsor: Mentor Graphics

6:30 pm –
8:00 pm

The Fan-Out Breakout

Organized by Yole Développement

Fan-Out is the most dynamic solution in the Advanced Packaging playground at the moment. All attendees are welcome to attend and interact in the panel discussion organized by Yole Développement. It will be the opportunity to learn and debate with key industrial players willing to share their different points-of-view and visions on Fan-Out, related strategy, business, and technology trends.

MODERATOR: Jérôme Azemar, Yole Développement

- Yole Développement, Santosh Kumar, Senior Analyst
- ASE Global, Rich Rice, Senior VP of Business Development
- Intel, Islam Salama, Director: Pathfinding Department, Substrate and Packaging Technology Development
- JCET / STATS ChipPAC, Vinayak Pandey, Product and Technology Marketing Director
OR Scott Sikorski, Product Technology Marketing Vice-President
- Infineon, Johannes Lodermeyer, Wafer Level Technology Development Responsible


Session & Refreshments Sponsored by:

Panel Session Sponsor: Unity SC

Panel Session organized by YOLE

8:00 pm


GBC Speaker Dinner | 8:00 pm
(By Invitation Only)

Thank you to the GBC Speaker Dinner Sponsors:

DPC/GBC Premier Sponsor: ASE US, Inc.
DPC Premier Gold Sponsor: Amkor Technology
DPC Premier Gold Sponsor: NAMICS
DPC Premier Gold Sponsor: Nanium
DPC Premier Gold Sponsor: Cadence



WEDNESDAY, MARCH 8, 2017 -- GBC Keynote & Plenary Session

7:00 am -
6:00 pm


7:00 am -
8:00 am

Continental Breakfast Sponsored by:
DPC Premier Gold Sponsor: NAMICS


Welcome to the Global Business Council (GBC) Keynote & Plenary Session on
* Consolidation of Customer and Supply base * Impacts of Technology Transitions * Financial Challenges

8:00am – 8:15am

GBC Chairs: 
Lee Smith, (UTAC) United Test & Assembly Center; Rich Rice, ASE Group

8:15am – 9:00am


Since the Great Recession, the global economy has definitely had its tumultuous times.  Financial and political instability along with low interest rates have resulted in “muddle through” worldwide growth.  For the semiconductor industry, smartphone growth has somewhat peaked.  Many are hoping that the IoT is the next growth driver, but it hasn’t blossomed yet. 

The last two years have seen practically no growth in the semiconductor marketplace.  What about 2017?  Will it be any better?  How will the semiconductor industry relate now to the “Make America Great Again” movement? 

To understand this key issue, an overview analysis of the semiconductor market will be presented and its relationship to worldwide GDP, electronic products, capital spending, Foundry, and the SATS/OSAT markets.

GBC Keynote - Jim Walker

Jim Walker, WLP Concepts
Jim Walker is the recent President of World Level Packaging Concepts (WLP).  Previously, he conducted research of semiconductor packaging and test, printed circuit board manufacturing and assembly, MEMS, and related outsourcing services assembly and test (OSAT) markets for Gartner, Inc.   Mr. Walker is a founding member and past national president of the Surface Mount Technology Association (SMTA), and has served on the advisory boards of Advanced Packaging Magazine, MEPTEC, Bridgewave Communications and Surfect Technologies, a MEMS and nanotech materials/equipment company.

Prior industry experience further includes co-founder and vice president of marketing for Hana USA, serving as the surface mount (SMT) packaging marketing manager at National Semiconductor (now part of Texas Instruments), and performing research, development, and quality assurance of polymeric materials for adhesive, composite, electronic, and semiconductor applications at Dexter Electronic Materials and E.I. DuPont. 

Mr. Walker holds a Bachelor of Science degree in chemistry from California State Polytechnic University with postgraduate work at California State University Los Angeles.

9:00am – 9:30am

Market Drivers and Packaging Trends for Automotive Electronics
Jan Vardaman, TechSearch International
Electronic content in automotive applications has increased dramatically over the past few years.  Automobiles are on the threshold of a radical change in technology.  Vehicles have increased connectivity, improved self-diagnostics, a greater number of safety features including crash avoidance technology and advanced driver assistance.  What type of semiconductor packages are used in automotive electronics and what are the future challenges as new package types are adopted?

9:30am – 10:00am

What’s Happening in China Advanced Semiconductor Packaging Landscape?
Santosh Kumar, Yole Developpement
This talk will discuss about the advanced packaging market in China including forecast by the packaging technology, key Chinese & global player’s activities and government IC policy / initiatives. Further it will include the supply chain evolution and analysis about the strategy / direction of OSATs as well as the opportunities/ challenges of both local and global players in China advanced packaging space.

10:00 am -
4:00 pm


10:00 am - 10:45 am

Break in the Exhibit Hall Sponsored by:

DPC Premier Gold Sponsor: Amkor Technology

Exhibit Reception Sponsor: Metalor

10:45am – 11:15am

Integrated Packaging and Substrate Technologies for Next-Generation Smart Devices
Eric Huenger, Rozalia Beica – Dow Electronic Materials
The presentation will provide an overview of the global trends driving the growth of Advanced Packaging, highlighting the trends of packaging platforms and substrates seen today in mobile applications. An overview of the various materials and interconnect processes required at both wafer and PCB/Substrate level, across various packaging platforms (WLP, SiP, 3DIC) will be included, highlighting current industry challenges and the solutions that Dow Electronic Materials are bringing to enable current and future development of smart devices.

11:15am – 11:45am

The Changing Landscape in the Back End
Brandon Prior, Prismark
The last several years have seen notable changes in the supply chain of electronics hardware as well as significant consolidation of semiconductor players.  Separately, the landscape of package assembly for both captive and merchant players has also evolved.  Much of this change is due to growth in package platforms such as SiP and FO-WLP.  How will these new platforms impact the role of semiconductor companies, wafer foundries, and OSATs?   What , if any impact, will the re-integration of component and hardware suppliers have on the back end?

11:45am – 12:00pm

GBC Closing Remarks

12:00 pm -
1:30 pm

Lunch in the Exhibit Hall Sponsored by:
(Food served from 12:00 pm - 1:00 pm)

DPC/GBC Premier Sponsor: ASE US, Inc.

Corporate Sponsor - NGK NTK

Corporate Sponsor: Evatec

Corporate Sponsor: Takaoka Toko Co. Ltd.


WEDNESDAY, MARCH 8, 2017 -- Afternoon Sessions

Interposers, 3D IC & Packaging

Fan-Out, Wafer Level Packaging & Flip Chip

Engineered Micro Systems/Devices
(including MEMS & Sensors)



Chairs: Yann Guillou, Unity SC; Lars Böttcher,  Fraunhofer IZM


Chairs: Jon Aday, Qualcomm; Bora Baloglu, Amkor 

This session focuses on advancements in fan-out wafer level assembly, equipment, and materials, with an emphasis on increased thru-put, enhanced metrology methods, optimized plating chemistries, and improved photo lithography techniques.

Chair: Dinesh Thanu, Intel Corporation

This follow-on session focuses on the utilization of chaos theory to enhance engineered systems.

1:30 pm –
2:00 pm

The Package Becomes the System
Bruce Barbara, Aurora Semiconductor LLC.

Wafer Thinning for Advanced Packaging Applications
Laura Mauer, Veeco Precision Surface Processing (John Taddei, Scott Kroeger)

True Random Source from Integratable Chaotic Circuit
Ned Corron, US Army AMRDEC (Marko Milosavljevic, Jon Blakely)

2:00 pm –
2:30 pm

Backside Shield against Physical Attacks for Secure ICs
Stéphan Borel, CEA-LETI (Edouard Deschaseaux, Jean Charbonnier, Philippe Medina, Stéphanie Anceau, Jessy Clediere, Romain Wacquez, Jacques Fournier, Eric Jalaguier, Christophe Plantier, Gilles Simon)

Advanced Packaging Lithography and Inspection Solutions for Next Generation FOWLP-FOPLP Processing
Elvino Da Silveira, Rudolph Technologies (Keith Best, Gurvinder Singh, Roger McCleary)

Stochastic Effects on a Chaotic Duffing Oscillator
Edmon Perkins, Auburn University

2:30 pm –
3:00 pm

Integration of Chemically Amplified Photoresist and High-Speed Copper Plating Products for Advanced Packaging Applications
Rosemary Bell, The Dow Chemical Company (Joseph Lachowski, Mitsuru Haga, Inho Lee, Regina Cho, Matthew Thorseth, Jonathan Prange, Mark Scalisi, Yi Qin, Yun-Hyeon Kim, Wataru Tachikawa, Yoon Joo Kim,Mark Lefebvre, Jeff Calvert)

Optimization of Speed and Accuracy for Fan-Out Die Placement
Tom Strothmann, Kulicke & Soffa Industries, Inc

Characteristic Mode Analysis and Design of Optimized Fractal-Inspired Antennas - SPEAKER CANCELLED              
Daniel Faircloth, IERUS Technologies

3:00 pm –
4:00 pm

Break in Exhibit Hall Sponsored by:

DPC Premier Gold Sponsor: Nanium
DPC Premier Gold Sponsor: Cadence

4:00 pm –
4:30 pm

Electromigration in Sintered Nanoporous Copper
Sebastian Gerke, IBM Research GmbH (Xiaoyu Chen, Luca Del Carro, Jonas Zuercher, Thomas Brunschwiler)

eDiagnostics and Fault Detection
Eric Dunton, Tokyo Electron Nexx Systems 


Chair: Kosta Varnavas, NASA; Robert Dean, Auburn University

This session focuses on thermal applications and modelling for engineered micro devices and systems.

Thermomechanical Modeling of Sintered Silver – A Fracture Mechanics-Based Approach
Paul Paret, National Renewable Energy Laboratory (Douglas DeVoto, Sreekant Narumanchi)

4:30 pm –
5:00 pm

Sintering Pastes for Interconnection of Embedded Discrete Passives in Substrates
Catherine Shearer, Ormet Circuits, Inc.

Cu Pillar, RDL and Via Fill Challenges facing FOWLP
Eric Gongora, MacDermid Enthone Electronics Solutions (Elie Najjar, Thomas Richardson, Leo Linehan, John Commander)

Glass Capillary Based Joule-Thomson Coldstage for Low Pressure and Low Flowrate Applications
Collin Coolidge, University of Colorado (Li-Anne Liew, Ray Radebaugh, Y. C. Lee)

5:00 pm –
5:30 pm

The Effect of Processing Parameters on the Physical and Microwave Electrical Properties of Low Temperature Co-fired Ceramics
Jim Walker, Ferro Corporation (Jerry Aguirre, Kyocera International, Inc.; Ed Graddy, Jim Henry, Ferro Corp.)

Modern Analysis of Lead Free Plating Baths Utilized for Bump Plating in Wafer Level Packaging 
Vinh Nguyen, ECI Technology 

Silicon Chip-based Compressor for Joule-Thomson Micro-coolers Operating at 2:1 Pressure Ratio
Li-Anne Liew, University of Colorado /National Institute of Standards and Technology (Ching-Yi Lin, Collin Coolidge, Ryan Lewis, Y.C. Lee)


Device Packaging Poster Session

5:30 pm -
6:30 pm

Outside On Patio Overlooking Desert: 5:30 pm - 6:30 pm
(Poster Presenter Setup - 4:00 pm - 5:00 pm)

Poster Session & Happy Hour Sponsored by:

Poster Session Sponsor: Quantum Analytics
Poster Session Sponsor: SAMTEC
Mobile Station & Poster Session Sponsor: VEECO
Poster Session Sponsor: Applied Materials

3D Metrology for FO-WLP and Advanced Packaging using Multi-Sensor Interferometry             
Julia Herz, Sentronics Metrology GmbH (Moritz Jurgschat, Matthias Weber)

The Effect of Cu Block and Dense Via-cluster design on Thermal Performance of Package-On-Package
HoJoneg Lim, Amkor Technology Inc.

Ultra-Thin, Fine-Pitch Step Stencils For Miniature Component Assembly
Phani Vallabhajosyula, Photo Stencil LLC

Thermal Warpage Measurement System for Environmental Test of Automotive Devices
Mitsuhiro Ishihara, Takaoka Toko Co., Ltd.

Metallization of Interconnections on Liquid Crystal Polymers: Microcontact Printing as a Tool for 3D Molded Interconnect Devices and Packaging
Michel Cabrera, AMPERE-lab (Kevin Cheval, Vincent Semet, Philippe Lombard, Bruno Allard)

Fabrication of Low Melting Cu/Sn Alloy Nanoshells by Sputter Deposition on Polymeric Nanofiber Templates
Said J Cifuentes Maury, University of Puerto Rico (Ricky Valentín, Wilfredo Otaño)

Superpersistent Currents and Whispering Gallery Modes in Relativistic Quantum Chaotic Systems
Hongya Xu, Arizona State University

Minimizing Film Stress and Degradation in Thin-Film Niobium Superconducting Cables              
Vaibhav Gupta, Auburn University (John Sellers, Charles Ellis, Bhargav Yelamanchili, Simin Zou, Yang Cao, David Tuckerman, Michael Hamilton)

Analysis of Insulated Gate Bipolar Transistor Degradation due to Power Cycling
Nathan Valentine, University of Maryland (Diganta Das, Michael Pecht)

Silicon Chip-based Compressor for Joule-Thomson Micro-coolers Operating at 2:1 Pressure Ratio
Li-Anne Liew, University of Colorado / National Institute of Standards and Technology (Ching-Yi Lin, Collin Coolidge, Ryan Lewis, Y.C. Lee)

Automation of Die Attach using BondFlow™
Jim Fraivillig, Fraivillig Technologies (Rich Koba, Kent Hutchings, Materion; Peter Cronin, MRSI Systems)

Surviving the Heat Wave – a Presentation on Thermally Induced Failures and Reliability Risks Created by Advancements in Electronics Technologies
Greg Caswell, DfR Solutions

Experimental Study on RDL Contact Interface Engineering in Advanced Packaging
Frantisek Balon, Evatec Ltd. (P. Carazzetti, J. Weichart, A. Erhart, Evatec, Ltd.; K. Viehweger, Fraunhofer IZM)

Presentation of Different Interconnection Technologies for Fine Pitch and Heterogeneous Assembly  
Marion Volpert, CEA-LETI (Gilles Lasfargues, Francois Marion, Francois Templier, Frederic Berger, David Henry)

Comprehensive In-Line Metrology for Advanced RDL Process Monitoring
Johnny Dai, Rudolph Technologies (J. Chen, M. Mehendale, M. Alves, J. Ding, F. Shen, R. Mair, P. Mukundhan, J. Shen, C. Kim)

The Influence that a Photosensitive System and Polymer Structure of the Photosensitive Polyimide Affect to Copper Insulation Reliability
Masao Tomikawa, Toray Industries Inc. (Kazuyuki Matsumura, Yu Shoji, Yoshiko Tatsuta, Yutaro Koyama, Ryoji Okuda)

Wafer Bumping Fluxes and Spin Coating Parameters for Enabling 2.5D and 3D Technology
Maria Durham, Indium Corporation (Phil Skeen, Sikama International)

EMI Shielding: Improving Sidewall Coverage with Tilt Spray Coating
Akira Morita, Nordson Asymtek (Michael Szuch, Hiroaki Umeda)

Low Temperature Curable PI/PBO for Advanced Packaging 
Daisaku Matsukawa, Hitachi Chemical DuPont Microsystems, Ltd. (Tadamitsu Nakamura, Tetsuya Enomoto, Noriyuki Yamazaki, Masayuki Ohe, Takeharu Motobe, Masato Nishimura)

Silicon-Package Co-Verification for FOWLP Applications 
Alex Caravajal, Mentor Graphics

3D Packaging from Mold Interconnect Substrate (MIS) Technology
Kai Liu, MISpak Technology of JCET Group

Importance of EOS and ESD Control: Introducing Industry Council Whitepaper 4
Stevan Hunter, ON Semi

Cost Comparison of Fan-out Wafer Level Packaging and Flip Chip Packaging                
Amy Lujan, SavanSys Solutions LLC

Plasma Dicing, the Fastest Path to Reduce Die Costs
Christopher Johnston, Plasma Therm

(additional abstracts in regular session will also be invited to participate)
In event of inclement weather, the poster session will be held in the foyer of the conference center



THURSDAY, MARCH 9, 2017 -- Keynote Presentations

7:00 am –
11:30 am


7:00 am –
8:00 am

Continental Breakfast Sponsored by:

DPC Premier Gold Sponsor: NAMICS

8:00 am -
8:45 am

Keynote Sessions Sponsored by:

SPTS - Corporate Sponsor

Trends in MEMS and Sensor Integration

The recent years have seen an exponential proliferation in the use of sensors, especially the image, motion, environmental and acoustic types. The smartphone is the best example of this phenomenon, integrating all of the above into what was once a humble phone. In its turn, the IoT revolution promises to drastically increase the usage of both smart and passive sensors as they get adopted into the personal and commercial aspects of our lives.

With the current and anticipated growth, the sensors themselves have become more sophisticated. Their performance and functionality have increased, while ASPs and power consumption have dropped. This evolution has been driven by the basic building blocks of 3D interconnects - stacking, bonding and TSVs. While TSV technology has matured considerably over the last few years, the industry relies on a variety of wafer and die bonding options, each with its own pros and cons. The goal is an optimum combination of high throughput, high accuracy and low temperature bonding for cost, performance and reliability reasons. This presentation will assess current and promising wafer and die bond technologies, while also examining the overall trends in MEMS and sensor technology.

Keynote - Sitaram Arkalgud

Sitaram Arkalgud, Xperi
Sitaram Arkalgud is driving the utilization of Ziptronix bonding technologies (ZiBond® and DBI ®) in 3D applications since January 2016. Prior to this role, he led the 3D group as VP, 3D Technology and Portfolio at Invensas. Before joining Invensas, he started and led 3D-IC development at SEMATECH, where the focus was on delivering manufacturable process technologies for TSV, wafer/die bonding and wafer thinning for 3D IC. Previously, Sitaram worked in a variety of roles spanning R&D and manufacturing in memory and logic technologies at Infineon/Qimonda and Motorola. He is the author of several publications and holds 24 U.S. patents. Sitaram holds a master’s degree and a Ph.D. in materials engineering from Rensselaer Polytechnic Institute in Troy, N.Y., and a bachelor’s degree in metallurgical engineering from Karnataka Regional Engineering College (NIT-K), Surathkal, India.

8:45 am -
9:30 am

Embedded Components in PCB – the Most Important Step Towards Modularization in the Last Decade?

The continuing digitalization of the world will change this decade and define the growth of the electronics industry. The driving forces behind these trends are the nearly ubiquitous access to the Internet and the continuous price pressure for electronic devices, data transmission and sensors. Today’s, society is at the start of the Internet of Things (IoT) and has already evolved   much broader than just an idea. It has morphed to ”Internet of Everything“ (IoE).The majority of the 50 billion connected devices, machines, vehicles, etc. in 2020 will be used to link and direct systems in a variety of areas such as industry, smart homes, smart cities, smart energy, smart mobility, smart healthcare, wearables and much more. This trend will have significant influence on the future growth in all segments of the entire electronics industry.

In order to offer solutions from electronics industry for these we have to realize and understand that the systems of the future require a more holistic “interconnection technology”. We have to form electronic modules at a minimum consumption of speed, space and energy. Over the last years embedding of components in PCBs has offered some answers for these modules of the future already. Now it is time to reflect the first experiences and check what is feasible in the up-coming years.

Keynote - Markus Leitgeb

Markus Leitgeb, AT & S Austria Technologie & Systemtechnik Aktiengesellschaft
Markus Leitgeb studied Polymer Engineering at the University of Leoben, Austria. He joined AT&S in December 2000 and was responsible for the screening, evaluation and qualification of base materials with improved reliability performance as well as for the implementation of new measurement technologies and testing methodologies (e.g. Drop Test). Out of this experience, he started to work on alternative concepts for flexible interconnections and mechanical miniaturization within the PCB, which succeeded in the 2.5D® Technology to enable cavities and advanced Rigid-flex solutions. Markus supported the roll out of the 2.5D® Technology to the plants in Leoben (Austria) and Shanghai and was responsible for the Product Development.

In 2012, Markus took over the Mechanical Integration Team within the R&D department of AT&S, which is developing alternative concepts for miniaturization and integration of additional functions such as Thermal Management and High Frequency into electronic devices. Markus holds 24 patents and published several papers. He is member of IPC, SMTA, iMAPS and the Advanced Packaging Committee of ECTC.

9:30 am -
9:45 am

Break in the Foyer Sponsored by:

DPC Premier Gold Sponsor: Amkor Technology

Exhibit Reception Sponsor: Metalor



THURSDAY, MARCH 9, 2017 -- Morning Sessions

Interposers, 3D IC & Packaging

Fan-Out, Wafer Level Packaging & Flip Chip

Engineered Micro Systems/Devices
(including MEMS & Sensors)



Chair: Kathy Cook, Tessera; Lucile Arnaud, CEA-Leti


Chairs: Linda Bal, TechSearch; Amy Lujan, SavanSys

This session focuses on advanced flip chip packaging Advancements in underfill technology are explored, and the growing capabilities of flip chip designs to meet more stringent requirements are evaluated.


Chairs: Li-Anne Liew, University of Colorado, Boulder / NIST; Keaton Rhea, Auburn University

This session focuses on high frequency applications for engineered micro devices and systems, from GHz to optical frequencies.

9:45 am -
10:15 am

Plasmonic Rulers for 3DIC Alignment             
Bozena Kaminska, Simon Fraser University / NanoMedia Solutions (J. Patel, H. Jiang)

Precise, High-throughput Underfill Dispense in Chip-on-Wafer Packaging 
Hanzhuang Liang, Nordson Asymtek

Multiscale Modeling of Transport in Silicon Heterojunction Solar Cells
Pradyumna Muralidharan, Arizona State University (Stephen Goodnick, Dragica Vasileska)

10:15 am -
10:45 am

Laser Debonding for 2.5D, 3D and Emerging Advanced Packaging Solutions
Thomas Uhrmann, EV Group (Elisabeth Brandl, Thomas Uhrmann, Martin Eibelhuber, Harald Wiesbauer, Julian Bravin, Markus Wimplinger, Paul Lindner)

Advanced Packaging for Automotive Dashboard Application
Nokibul Islam, StatsChipPAC Inc

Micromachined Interfaces for Metrology and Packaging Applications in the Submillimeter-Wave Band
Robert Weikle II, University of Virginia (H. Li, A. Arsenovic, S. Nadri, L. Xie, M.F. Bauwens, N. Alijabbari, N. Scott Barker, A.W. Lichtenberger)

10:45 am -11:15 am

Plasma Dicing, the Fastest Path to Reduce Die Costs
Christopher Johnston, Plasma Therm

Manufacturability Trade-Offs of Bare-Die FCBGA Package Using Thin or Core-Less Substrate: Package Design Solutions to Maximize Thermal Performance, Improve Package Reliability & Eliminate Warpage Failures Utilizing Bare Die FCBGA
Ankita Verma, Quantenna Communications Inc (Baqar Tabrez, Lam Duong, Martin Wuest)

Hygrothermal Aging of Flip-chip Assembled MOEMS
Maaike M. Visser Taklo, SINTEF (Daniel Nilsen Wright, Sigbjørn Kolberg, Astrid-Sofie B. Vardøy, Faycal Hamou, Andreas Vogl, Helge Kristiansen, Erik Kalland, Thor Bakke)

11:15 am -
11:45 am

The Influence of Intermetallic Compounds, (IMC), on High Speed Shear Testing, (HSS), with a Specific Interest in Electroless Palladium / Autocatalytic Gold (EPAG)
Richard John Nichols, Atotech Deutschland GmbH

The Effect of Underfill on Thermal Stresses Transferred to DSP and its Electrical Performance
Babak Talebanpour, Starkey Hearing Technologies (Doug Link)

Minimizing Film Stress and Degradation in Thin-Film Niobium Superconducting Cables              
Vaibhav Gupta, Auburn University (John Sellers, Charles Ellis, Bhargav Yelamanchili, Simin Zou, Yang Cao, David Tuckerman, Michael Hamilton)

11:45 am

Conference Ends

1:00 pm Tee Time – “Shotgun” Start

2017 IMAPS David Virissimo Memorial Charity Golf Outing
1:00pm Shotgun Start -- "Scramble"

SunRidge Canyon Golf Club
Fountain Hills, AZ




Registration Information: (Early Registration Deadline: February 17, 2017)

Member, Non-member, Speaker/Chair, Student and Chapter Officer registration fees include: access to all technical sessions, exhibits, meals, refreshment breaks, and one (1) DOWNLOAD of presentations; DOWNLOAD will contain the extended abstract and presentation as submitted by the presenter. DOWNLOAD will be emailed 15 approximately business days after the event. Also includes a one-year IMAPS individual membership or membership renewal at no additional charge which does not apply to corporate or affiliate memberships. All prices below are subject to change.

Early Fee
Through 2/17/17
Advance/Onsite Fee
After 2/17/17
IMAPS Member
Chapter Officer
Exhibits Only Pass w/ Lunch Included
Exhibits Only Pass NO Lunch Included
8x10 Exhibit (Member)
8x10 Exhibit (Non-Member)
Professional Development Course:
Each Course Registration is additional to the conference registration. Maximum of 1 morning course and one afternoon course can be selected. Attendees can opt for $0 exhibits only pass if they wish to take a PDC but NOT attend the conference/sessions.


Speaker Dates/Information:

  • Abstracts Deadline Extended to: November 18, 2016
  • Speaker Notification Emails: December 9, 2016
  • Extended Abstract Deadline extended to: February 10, 2017
  • Hotel Reservation Deadline: February 1, 2017
  • Early Registration Deadline: February 17, 2017
  • Speaker Bios Due: February 15, 2017
  • Powerpoint/Presentation file for DOWNLOAD due not later than: March 9, 2017 (Last day of Conference)
  • Powerpoint/Presentation file used during session: Speaker's responsibility to bring to session on USB (recommended to have back-up on personal laptop or email to prior to event)
  • Technical Presentation Time: 30 minutes (25 to present; 5 for Q&A) - Keynotes: 45 minutes (40 to present; 5 for Q&A)

Presentation Format/Template:
IMAPS does not require you to use a conference powerpoint template.
You are able to use your regular company/preferred powerpoint templates.
Please include the IMAPS show name and dates on your template and/or an IMAPS logo.

Poster Session/Information
The poster session is planned to be an INTERACTIVE presentation. This means you do not start and complete a scheduled talk without interruption like in a regular/oral session. Speakers should have talking points and be at their poster throughout the entire session (Wednesday, March 8 from 5:30pm-6:30pm). You can "present" your scheduled materials, but more often the attendees will review your slides and ask questions. Or you can watch them and talk to them depending on which slide they are on. Authors may either print out each of their powerpoint slides on regular paper and tack them up in order, or prepare a large poster (or 2 even). Recommended poster size is typically 3x4 feet, with the max space on the board being 4 ft high x 8 ft wide. IMAPS staff will provide tacks to secure your print outs. The session is first-come-first-serve so there are not assigned poster boards/locations. POSTER SETUP FROM 4PM UNTIL 5:00PM on Wednesday, March 8.

Dress Code:
There is no officially "dress code" for IMAPS Conferences. We ask you to be BUSINESS CASUAL or whatever more you prefer. Most speakers tend to be in business pants and button down/company logo shirts (Women in dresses or the same). Suits, sport coats and ties are common as well. We do not recommend casual attire.

Session rooms will be equipped with:
Screen, projector, podium, IMAPS laptop (with Microsoft Windows and recent OFFICE suite), microphone, and slide remote/laser pointer.

All session presentations are 25 minutes followed by 5 minutes for Questions
You are required to load your powerpoint/presentation onto the session laptop yourself using your USB drive.
Speak with your session chair if you need assistance.

About the Session:
Sessions begin with Session Chairs making general announcements. Session Chairs will then introduce speakers by reading BIOs. Speaker will present for 25 minutes, followed by 5 minutes for questions. Session Chairs will thank the speakers. This process is repeated for each speaker in the session. Many sessions will take refreshment breaks (see program).

Photography is not permitted in the session rooms.

Silence all mobile phones during session attendance.


Hotel Reservation Deadline - February 1, 2017

Housing accommodations must be made directly to:

WeKoPa Resort & Casino - SOLD OUT
10438 North Fort McDowell Road
Scottsdale/Fountain Hills, AZ 85264

IMAPS Discounted Single/Double Room Rate: $175/night + taxes + fees - SOLD OUT

IMAPS DOES NOT have another room block, but we can point you to another area hotel:

IMAPS recommends another area hotel for those unable to get a room at WeKoPa Resort:

Comfort Inn


Book your hotel reservation today! We have reserved a block of rooms at the host hotel to accommodate our attendees. The discounted room rates are only available until the hotel deadline listed above, or until the room block sells out (and they often sell out early - before the expire dates). Reservations received after the noted deadline or after the room block has been filled may be subject to significantly higher rates. IMAPS room blocks at most hotels historically sell out ahead of the discount deadline, so we encourage you to make your hotel reservations quickly for the best price and availability.

Hotel Scams Alert!
All reservations should be made directly with the hotel and within the IMAPS room block. We are not using a housing company. If any person or firm contacts you and offers to handle your reservations, please beware. They are completely unauthorized and possibly fraudulent. The convention industry is currently plagued by such groups. If you use one of them and experience any problems, including lost deposits and no reservation when you arrive, IMAPS may not be able to assist you. Please be aware in particular of one of these unauthorized firms – Exhibition Housing Services – whose salespeople have falsely claimed to be calling from IMAPS.

The only way to book a room in the official IMAPS Housing Block using the reservations information above.


Device Packaging Sponsorship (Need to be ahead of your competition? Join this list today!)


DPC/GBC Premier Sponsor: ASE US, Inc.

DPC Premier Gold Sponsor: Amkor Technology
DPC Premier Gold Sponsor: NAMICS
DPC Premier Gold Sponsor: Nanium
DPC Premier Gold Sponsor: Cadence
Corporate Sponsors
EMD Performance Materials - Corporate Sponsor
Mobile APP Sponsor: SETNA
Corporate Sponsor - NGK NTK
SPTS - Corporate Sponsor
Corporate Sponsor: Evatec
Corporate Sponsor: Takaoka Toko Co. Ltd.
Additional Event Sponsors

Exhibit Reception Sponsor: Metalor

Exhibit Hall Reception & Coffee Break

Exhibit Hall Reception Sponsor: Mentor Graphics

Exhibit Hall Reception

Mobile Station & Poster Session Sponsor: VEECO

Mobile Charging Station &
Poster Session Happy Hour

Poster Session Sponsor: Quantum Analytics

Poster Session Happy Hour

Poster Session Sponsor: SAMTEC

Poster Session Happy Hour

Poster Session Sponsor: Applied Materials

Poster Session Happy Hour

Panel Session Sponsor: Unity SC

Evening Panel & Reception

Notebook Sponsor: SMART Microsystems

Session Notebooks/Pens

Golf/Foundation Sponsors

"Eagle" Sponsor (3 holes):

DPC/GBC Premier Sponsor: ASE US, Inc.

Holes: #1, #12 - Closest to Pin, #16

"Eagle" Sponsor (3 holes):

DPC/GBC Premier Sponsor: NAMICS

Holes: #2, #8 - Closest to Pin, #18

"Birdie" Sponsor (1 hole):

Golf Hole Sponsor: Amkor Technology

Hole #3 - Longest Drive

"Birdie" Sponsor (1 hole):

DPC Premier Gold Sponsor: Nanium

Hole #6 - Closest to Pin

"Birdie" Sponsor (1 hole):

DPC Premier Gold Sponsor: Cadence

Hole #14 - Closest to Pin

"Birdie" Sponsor (1 hole):

ASM Pacific - Hole Sponsor

Hole #15

EMD Performance Materials - Corporate Sponsor

Hole #10 - Longest Putt

Golf Hole Sponsor: AGC Electronics America

Hole #4

Golf Hole Sponsor: Nikon

Hole #7

Mobile Station & Poster Session Sponsor: VEECO

Hole #5

Golf Sponsor: NxQ
Mask Aligners

Hole #11

Technic - Golf Hole Sponsor

Hole #13

Golf Hole Sponsor: Dixon Golf

Hole #9 - Straight Drive Competition
Hole #17 - Hole-in-One Competition

Golf Awards Sponsor: Advance Reproductions

Golf Awards Sponsor

Official Media Sponsors
Media Sponsor: MEMS Journal
Media Sponsor: Chip Scale Review
Media Sponsor: MEPTEC
3D Incites - Media Sponsor
Solid State Technology - Media Sponsor


  • Amkor
  • ASE
  • Canon
  • Corning
  • EMD Performance Materials
  • Honeywell
  • Indium
  • Kester
  • Kyocera America
  • Master Bond
  • Micro Systems Technologies
  • MRSI
  • Palomar
  • Promex
  • Qualcomm
  • Quik-Pak
  • Raytheon
  • Rochester Electronics
  • Specialty Coating Systems
  • Spectrum Semiconductor Materials
  • Technic